AN1730Using the MD1730 Ultra-Low Phase Noise CW Transmit

Beamformer for Medical Ultrasound Applications

INTRODUCTIONIn recent years, capabilities of medical ultrasound flowimaging systems have increased enormously. Colorflow imaging, Continuous Wave Doppler (CWD) andDoppler analysis that provide new flow image featuresare now commonly used. It is essential for theultrasound system to generate low-phase noise,high-quality CW transmission waveforms to get higher-quality Doppler echo signals.

This application note describes how Microchip’sMD1730 can help ultrasound systems achieve higher-quality, lower phase noise, focused CW arraytransmitters.

MD1730 is a very low-phase noise, 8-channel CWbeamforming waveform generation IC. It is designedfor CW Doppler mode in a medical ultrasound imagesystem.

CW BEAMFORMER TOPOLOGY

Normally, in CW mode, only ±2 to ±6V peak-to-peakvoltages are needed to drive the piezoelectric elementsin the ultrasound transducer probe. Therefore, theMD1730 circuit has been designed using thehigh-speed, low-voltage and low-time jitter CMOStechnology. The MD1730 provides an ultra-low phasenoise CW waveform, a high resolution CW frequencydivider and the per-channel delay timer for CWbeamforming function. These features help provideeight frequency-programmable CW sources withphase delay beamforming functions in a small 6 x6 mm QFN package. It helps save significant PCB realestate for portable medical ultrasound system. Figure 1shows a typical beamforming application for focusedCWD in a medical ultrasound system.

FIGURE 1: Forced CWD Beamforming in Medical Ultrasound System.

Author: Ching Chu Microchip Technology Inc.

B.F+Mixer

VCW-

-1 to - V

GND Ther.PAD

-10V

SUB

VGN CNF

EN

CW0

VNF

CLKP

CLKN

SDO

SDI

CSN

SPI

SCK

CW3

VPF

CWFre.Dvdr& PhaseDelay

CW2

CW1

TXRW

HIZ[7:0]

VLL

CLK

CLK

CBE1

CKB0

Ch0

SPIM

LVDS CLK

CBE0,1

VLL

CBE0

CKB1

U1 MD1730

VCW+

VCW-

+10V

VGP

+2.5V

VLL

+1 to + V

VCW+

+5V

VDD CPF

Ch7

CW4

CW7

CW6

CW5

VNF

VPF

VCW+

VCW-

Ch1~6

LNA

IN0

IN3

IN2

IN1

IN4

IN7

IN6

IN5

GND

U4 AFECW

Processor

+1.8V

VDD VCW

+3.3V

LNA

LNA

LNA

LNA

LNA

LNA

LNA

CW TxFocusBeamForming

CW RxEcho

U3 HV SW U3 HV SW

CW DopplerDetectingVolume

Where VS is he Sound Speed In Tissue.Where VB is the Velocity of the Flow.

MoreChannels

MoreChannels

MoreChannels

MoreChannels

with CW TxBeamformingDelay(PHDCh)

with CW RxBeamformingDelay(PHDCh)

B-ModeHV PulserOutput& T/R SWs

B-ModeHV PulserOutput& T/R SWs

UltrasoundTransducerProbe

2016 Microchip Technology Inc. DS00002307A-page 1

AN1730

MD1730 WORKING WITH HIGH VOLTAGE ANALOG SWITCHES

The ultra-low phase noise, high-speed and low-voltageoutputs of the MD1730 cannot withstand thehigh-voltage B-mode transmit pulse voltages.Therefore, HV analog switches must be used to blockthe Tx pulser outputs from the MD1730 during B-mode.Figure 2 shows an example implementation whereMicrochip's HV2201 8-channel analog MUX is usedwith the MD1730. HV2201 has eight high-voltageanalog switches that can withstand a ±100V peak

voltage of transmit pulses. When the HV switches areon, their low on-resistance has an extremely lowcontribution to the overall phase noise and phaseretardation of the CW waveforms. One MD1730, whencombined with one HV2201, can be used with four setsof MD1715s and TC8020s to form an 8-channel,5-level ±100V high-end Tx pulser with ultra-low phasenoise CW digital beamformer. During B-modeoperation, MD1730 is disabled using its EN pin, and theHV2201 switches are turned off using its CLR pin. InCW mode, the MD1730 is enabled and the HV2201switches are turned on.

FIGURE 2: MD1730 CW Working with HV2201 HV Switch and MD1715 + TC8020 ±100V ±3A 5-Level Tx Pulser.

+10V

VGP

+ to + VVCW+

CW0VPF

VNF

EN

+2.5V

VLL

TXRW

SPIB

SDICSNSCK

CLKN

CLKPLVDS / SSLTClock Input

SPI&

Registers

GND

CW1

MD1730ThermalPad

-10V

SUB

VLL

CLK CKB0

CW7VPF

VNF

- to - VVCW-

VCW+

VCW-

HIZ[7:0]

CPFVPF

VNF

CNF

SDO QMSB

D0

CKB1

CBE1

VLL

CBE0

+5V

VDD

VGN

CLK

PHD7~0[7:0] CWFD[7:0]

PHD1[7:0] CWFD[7:0]ENAENA Q

CLK CLKQ

PHD7[7:0] CWFD[7:0]ENAENA Q

CLK CLKQ

PHD0[7:0] CWFD[7:0]ENAENA Q

CLK CLKQ

864

CLK

SCK

VCW+

VCW-

XDCR

XDCR

DLECL

SW0

DLECL

SW1

DLECL

SW2

DLESW6

DLECL

SW7

CLK

8-BITSHIFT

REGISTER

DIN

DOUT

LEVELSHIFTERS

OUTPUTSWITCHES

VNN VPP CLR LE GND VDD

LATCHES

CL

TX7

EN

SELPOSNEG

B/CW

LVL[3:2]POS[3:2]NEG[3:2]

VDD2

High SpeedGate Buffers

VDD2

VDD1

VDD1

VSSVDD1

High SpeedGate Buffers

ControlLogic andLevelTransla-tion

GND

MD17151 of 2-ch

TC80206 of 12-FET

+10V

VDD2

+10V

VDD1

+10V

AVDD+90V

SP1

+50VSP2

-90V

SN1

-50V

DP1

DN1

DP2

DN2

SN2

SP3

SN3

DP3

DN3

GP1

GN1

GP2

GN2

GP3

GN3

OP1

ON1

OP2

ON2

OP3

ON3

-10V

VSS

-10V

AVSSPADGND PAD VSUB

TX0

VDD2

High SpeedGate Buffers

VDD2

VDD1

VDD1

VSSVDD1

High SpeedGate Buffers

ControlLogic andLevelTransla-tion

MD17151 of 2-ch

TC80206 of 12-FET

+10V

VDD2

+10V

VDD1

+10V

AVDD+90V

SP1

+50VSP2

-90V

SN1

-50V

DP1

DN1

DP2

DN2

SN2

SP3

SN3

DP3

DN3

GP1

GN1

GP2

GN2

GP3

GN3

OP1

ON1

OP2

ON2

OP3

ON3

-10V

VSS

-10V

AVSSPADGND PAD VSUB

HV22018-ch HVAnalog Switch

EN

SELPOSNEG

B/CW

LVL[1:0]POS[1:0]NEG[1:0]

GND

B/CW LE +3.3V-100V +100V

CW/ B

CW_START

FPGA

FPGA

DS00002307A-page 2 2016 Microchip Technology Inc.

AN1730

FIGURE 3: MD1730 with Two HV7321 as Low-Phase Noise CW Beamformer.

VCW-

- to - V

GND Ther.PAD

-10V

SUB

VGN CNF

EN

CW0

VNF

CLKPCLKN

SDO

SDI

CSN

SPI

SCK

CW3

VPF

CWFre.Dvdr& PhaseDelay

CW2

CW1

TXRW

HIZ[7:0]

VLL

CLK

CLK

CBE1CKB0

Ch0

SPIM

LVDS CLK

CBE0,1

VLLCBE0

CKB1

U1 MD1730

VCW+

VCW-

+10V

VGP

+2.5V

VLL

+ to + V

VCW+

+5V

VDD CPF

Ch7

CW4

CW7

CW6

CW5

VNF

VPF

VCW+

VCW-

Ch1~6

X0

0 to+80V

VPF1

VNN1

VPP1

RGND

TX0

-0 to-80V

VPP0

VNN0

0 to-80V

0 to+80V

1 of 4 Channels

+5V

VDD

Decode&

LevelShift

CWIN0

NEG0

SEL0

NEG3

SEL3

CWIN3 U2 HV7321

GND

OTPN

+2.5V

VLL

PWS

POS3

VSUB

SUB

MODE

REN

CLK

POS0

TX1-3

RX1-3

Rx0RX0

VPF0

VNF0

VNF1

RGND

RTZSW

CWSW

TRSW

RXDMP

TRSW

+10V

VGP

-10V

OEN

VGN

CWIN2

CWIN1

Tx FPGA I/Os

ToOtherICs

CTRN[3:0]

OTP

DT[63:0]

X4

0 to+80V

VPF1

VNN1

VPP1

RGND

TX0

-0 to-80V

VPP0

VNN0

0 to-80V

0 to+80V

1 of 4 Channels

+5V

VDD

Decode&

LevelShift

CWIN0

NEG0

SEL0

NEG3

SEL3

CWIN3 U3 HV7321

GND

OTPN

+2.5V

VLL

PWS

POS3

VSUB

SUB

MODE

REN

CLK

POS0

TX1-3

RX1-3

Rx4RX0

VPF0

VNF0

VNF1

RGND

RTZSW

CWSW

TRSW

RXDMP

TRSW

+10V

VGP

-10V

OEN

VGN

CWIN2

CWIN1

+2.5V

ToOtherICs

ToOtherICs

2016 Microchip Technology Inc. DS00002307A-page 3

AN1730

MD1730 WORKING WITH HV7321 TX PULSER

For the higher integration levels required in portablemedical ultrasound systems with tighter PCB spacing,Microchip’s HV7321 ultrasound transmit pulser, alongwith MD1730, offer a better and simpler solution. Referto Figure 3.

HV7321 is specifically designed to work withlow-voltage, ultra-low phase noise CW waveformgenerators such as the MD1730. HV7321 is afour-channel, 5-level ±80V, 2.6A ultrasoundtransmitter. HV7321 has integrated T/R switches(TRSW) and RTZ switches (RTZSW) along withhigh-voltage analog CW switches (CWSW).

When in B-mode, all CW switches are off and theyblock the high-voltage pulses. When the HV7321 is inCW Mode-1, these CW switches are turned on. Theinput terminals of the CW switches on the HV7321(CWIN0-3) connect to the MD1730’s CW outputs(CW0-7).

With the built-in CW switches, the HV7321 output pinscan be directly connected to the ultrasoundtransducers. The HV7321's built-in high-voltage analogswitches act like a high-voltage MUX, blocking the highvoltages in B-mode and passing through thelow-voltage CW signals to the MD1730.

CONTROLLING THE MD1730 AND THE HV7321

During B-mode, the MD1730 does not need to beenabled. Setting EN = 0 will reduce power consump-tion. The user can turn off the MD1730’s clock on CLKPand/or CLKN for power saving.

If MD1730’s EN = 1, the user must set TXRW = 0, tomake sure the CW0-7 output are all in high Z state. Atthe same time, HV7321’s CWSW0-3 must be turnedoff, by setting the pin to MODE = 0. When theMD1730's CW signals are expected, the HV7321 is setto CW Mode-1.

The following steps should be taken to ensure properoperation:

1. Apply all power supply rails to both chips and setHV7321’s to OEN = REN = PWS = 1 along withMD1730’s to EN = 1 to enable both chips. Set allother logic input pins to zero.

2. Adjust the VCW+ and VCW- power supplies to therequired peak-to-peak voltage levels for CWoutput transmission. Please note that a higherpeak-to-peak transmission voltage will result inthe MD1730 dissipating more power. The powerdissipation of the MD1730 is proportional to thesquare of the peak-to-peak voltage (about 2 to12VP-P).

3. Set HV7321’s MODE = 1.

4. Program the MD1730 with the desired CWfrequency divider and delay settings for CWtransmission.

For more details, please see the MD1730 datasheet "8-Ch Ultra Low Phase Noise CW Trans-mitter with Beamformer" (DS20005586).

5. To place a channel in receive mode, set thechannel's SEL, NEG and POS pins to 0, 1 and1 respectively on the HV7321. To place achannel in CW transmit mode, set the channel’sSEL, NEG and POS to any other combinationother than 0,1 and 1 respectively on HV7321.This will put that channel of the HV7321 high-voltage Tx output in high Z mode, but it will turnon the channel’s CW switch (CWSW).

To set the MD1730's CW pin in high Z mode, setthe corresponding bit in the high Z register to 1.

6. Once the system is ready to perform CWDoppler measurement, assert TXRW high tostart the CW transmission on the selectedchannels.

LOW PHASE NOISE CLOCK INPUTS AND OUTPUT BUFFERS

MD1730’s built-in eight independent channels shareone pair of synchronization clock input pins:CLKP/CLKN. The IC can accept a clock frequency upto 250 MHz. These clock inputs can be connected asdifferential LVDS input, or as single-ended LVCMOS2.5V input.

If a higher CW frequency step resolution is needed,then the differential LVDS or SSTL2.5V type clock inputmethod can be used, as shown Figure 4; a 100differential termination resistor must be connected asclosely as possible to the CLKP and CLKN pins.

LVDS clock line pair traces on the PCB should bedesigned as two 50 transmission lines with respect toGND plane, and the differential traces should be run asclosely as possible after they leave the multi-LVDSbuffer IC.

However, for the best phase noise performance, use anLVCMOS-2.5V single-ended type clock input, asshown in Figure 4. The clock frequency should be inthe range of 80 to 120 MHz. Select a very low phasenoise LVCMOS 2.5V clock buffer, like Microchip’sPL133-47. The input clock of the buffer IC should befrom an ultra-low phase crystal oscillator source.

If the CLKP input pin is connected to a single-endedLVCMOS-2.5V buffer output, then the CLKN input pinmust be connected to 1.25V with a 0.1 µF bypasscapacitor to GND.

DS00002307A-page 4 2016 Microchip Technology Inc.

AN1730

To use as an inverting phase of clock input, the CLKPand CLKN input pins can be swapped. CLKN should beconnected to the buffer output, and CLKP should beconnected to 1.25V and bypassed with a capacitor toGND.

In the single-ended clock input case, a 33 reversetermination resistor must be placed in-series with eachbuffer output. These resistors should be placed close tothe buffer output pins. The clock trace on the PCBshould be designed as a 50 transmission line withrespect to the GND plane. Figure 4 shows this reversetermination method. The clock trace reaches to theMD1730 clock input pin, so a 50 resistor will no longerbe needed to terminate to GND.

Following this method, the user can save powerconsumption for the clock distribution circuit. For thebest phase noise performance, the value of the reversetermination resistor should be optimized based on theCWD mode phase noise results.

FIGURE 4: Configuration as LVDS or LVCMOS - 2.5V Single-Ended Clock Inputs.

INTERFACE AND REGISTERS CONFIGURATION

MD1730 has two registers that can be configured viaSPI interfaces. The first register is the per-channelbeamforming delay register PHDch<7:0>. The secondregister is the CW frequency divider number registerCWFD<7:0>. Normally, it only needs to be configuredonce, and all the MD1730 chip’s CWFD registersshould have the same number.

Multiple MD1730s can be daisy-chained and pro-grammed as shown in Figure 5. Use the normal SPIoperation mode to write the first type (PHDch<7:0>) ofregister and use the Broadcasting mode to set theCWFD<7:0> quickly on each chip.

2.5V

CLK0

MD1730U2 U4U1MD1730 MD1730

PL133-47CLK Buffer

EN

TXRW TXRW

TXRW

TXRWEN ENEN

EN

CLKP CLKN CLKP CLKN CLKP CLKN

1.25V DC

0.1uF 0.1uF 0.1uF

Single-EndedLVCMOS Clock Line

VLL

2.5V

VLL VLL

2.5V 2.5V

80-150MHzClock OSC.

(from FPGA)

REF CLK1

CLK3GND 33ohm

GND GND GND

100VCC

MD1730U2 U4U1MD1730 MD1730

EN

TXRW TXRW

TXRW

TXRWEN ENEN

EN

CLKP CLKN CLKP CLKN CLKP CLKNDiffertial LVDSClock Line-Pair

CLK Buffer

2.5V

VLL

2.5V

VLL

2.5V

VLL

2.5V

ClockSource

(from FPGA)

Q0

Q1... ...Q3

IN

100 100

SY89832U

GNDGND GND

GND

2016 Microchip Technology Inc. DS00002307A-page 5

AN1730

NORMAL SPI MODE VS. SPI BROADCASTING MODE

The MD1730 SPI interface circuitry is designed todirectly connect to a normal SPI on a FPGA I/O pins. Towrite into the MD1730 SPI registers, the user mustalways send the MSB data bit first.

FIGURE 5: Multiple MD1720 Devices SPI Daisy Chain.

When SPIB = 0, the chip is configured in normal SPIread/write mode. In this mode, multiple MD1730s canbe configured using the daisy chain.

When SPIB = 1, the chip will support the Broadcastingmode, in which multiple MD1730s can be programmedwith the same value simultaneously. This high-speedBroadcasting mode reduces the programming timesignificantly and can be used to program thebeamforming CW frequency registers.

In addition, all the data being written into the registersin each chip during the broadcasting mode can be readout by the normal SPI read operations to be verified.This read-back feature helps with software debuggingand testing.

EXAMPLE OF SPI WRITE OPERATION

The following is a 1-byte writing example for theregister at ADD = 0011b with the dataD<7:0> = 01010101 when SPIB = TXRW = 0:

1. The write operation starts with setting CSN tolow.

2. SDI data is shifted into the shift register:

D<12> = 1 (W/R bit is set high); writing isenabled.

ADD<11:8> = 0011b, address for channel 3’sphase delay register.

D<7:0> = 01010101b, data to be written intochannel 3’s phase delay register.

The SDI data is shifted in at the rising edge ofSCK.

3. Once the complete data has been shifted in, theCSN should be set high to finish the writingoperation. The SDI data is latched intochannel 3’s phase delay register on the risingedge of CSN. CSN has to be kept high for aminimum of two SCK cycles for the data to bewritten into the appropriate register.

In the case of eight chips daisy-chained together, thereshould be 13 x 8 = 104 cycles of SCK before the CSNis set high.

MD1730 can also be used in Broadcasting mode towrite several daisy-chained chips with the same data.The Broadcasting mode can be used to reduce the timerequired to write using SPI if several MD1730 chipshave to be programed with the same data. An exampleof writing to MD1730 in broadcasting mode is givenbelow:

1. Set TXRW = 0 and SPIB = 1. Set CSN = 0(broadcasting operation starts).

2. Shift in the following SDI data to the firstMD1730 chip with SCK clock:

D<12> = 1 (W/R bit is set high), writing isenabled.

ADD<11:8> = 0011b, address for thechannel 3’s phase delay register.

D<7:0> = 01010101, data to be written into thechannel 3’s phase delay register.

SDI SDO

SCK CS

TXRW

13bit Shift Reg.

SPIB

D0

Q12

SDISDO

SCK CSN

TXRW

13bit Shift Reg.

SPIB

D0

Q12

MD1730U2 U8

TXRW

SCK

CSN

SDI

FPGA

SDO

U1MD1730 MD1730

SPIB

SDI SDO

SCK CS

TXRW

13bit Shift Reg.

SPIB

D0

Q12

SDISDO

SCK CSN

TXRW

13bit Shift Reg.

SPIB

D0

Q12

SDI SDO

SCK CS

TXRW

13bit Shift Reg.

SPIB

D0

Q12

SDISDO

SCK CSN

TXRW

13bit Shift Reg.

SPIB

D0

Q12

DS00002307A-page 6 2016 Microchip Technology Inc.

AN1730

The SDI data is shifted in at the rising edge ofSCK.

In broadcasting mode, the same set of datashifted into the first chip is sent to all theMD1730 chips along the daisy chain. WhenSPIB = 1, an internal switch connects the SDIand SDO directly, bypassing the shift register.

3. Once the complete data has been shifted in, theCSN should be set high to finish the writingoperation. The SDI data is latched into eachchip’s channel 3 phase delay register on therising edge of the CSN signal. CSN has to bekept high for a minimum of two SCK cycles forthe data to be written into the appropriateregister.

SPI READ OPERATION EXAMPLES

The following is an example to read 2-byte data fromthe MD1730 register at ADD = 0011b (channel 3’sphase delay register) when SPIB = TXRW = 0:

1. Set CSN = 0. Read-write operation starts.

2. SDI shifts in the following data:

D<12> = 0 (W/R bit is set low). Reading isenabled.

ADD<11:8> = 0011b, address for channel 3’sphase delay register.

D<7:0> = X, for a read operation, the data fieldis ‘don’t care’.

The SDI data is shifted in at the rising edge ofSCK.

3. Once the complete data has been shifted intothe SPI, the CSN is set high. While CSN is high,the MD1730 fetches the data located atADD<11:9> = 0011b and places it in its internalshift register.

CSN has to be kept high for a minimum of twoSCK cycles for the data to be fetched andplaced into the internal shift register.

4. CSN is set low and during the next 13 SCK clockcycles, the fetched data in the internal shiftregister is clocked out on the rising edge of SCKfrom the SDO of the MD1730.

POWER SUPPLY DECOUPLING

MD1730 is designed for ultra-low phase noiseoperation. However, the overall phase noise will not beonly be dependent on the MD1730 internal circuitdesign and manufacture, but also dependent on thefollowing application conditions:

• power supply ripple noise

• power supply switching spike noise

• power supply topology

• power supply circuit layout

• selection and layout of the decoupling capacitors for the MD1730's power pins

• PCB stack-up and ground planes

It is highly recommended that the user selects anultra-low ripple noise and well-filtered DC power sourcefor each one of the six power supplies required by theMD1730.

It is also recommended to use a low-noise, isolated,DC/DC power supply followed by a linear, low-dropout,post regulator.

A suitable power supply topology for this application isa push-pull converter. This converter has goodefficiency, low output noise and high common modenoise isolation.

Every design must pass EMI/RFI regulationcompliance for medical equipment. Typical methods tomeet these requirements include using low-inductancePCB layout techniques and adding R-C snubbers atswitching nodes.

The DC-to-DC converter circuit’s DC input and outputvoltage node to the ground must have considerablebypassing capacitors to achieve lower switching rippleand spike noise filtering. It is very important to selectlow ESR/ESL ceramic surface mount capacitors.

The switching power supply isolation transformerdesign must have good electrical and magnetic shield-ing, ground and flex bindings.

Ensure that the switching noise from the DC/DCconverter does not contaminate the MD1730's groundplane.

An example of a power supply ground connections toensure a low-noise power supply is shown in Figure 6.

It is recommended to define a localized copper area foreach circuitry block of the DC-to-DC converters aseach block circuitry common ground. All thecomponents within the circuitry block have to be placedon a localized common ground area. Then all localground traces, as short as possible, must connect toeach other first. Then, the local ground summing nodegoes through via(s) connecting to the second-layerground copper plane. After that, use only one point,such as one big via to connect this localized commonground to the GND plane of the PCB. This methodshould also be used for the post LDO linear voltageregulators.

Using an LDO at the output of DC-to-DC converterhelps improve voltage regulation, as well as reducenoise from the DC-to-DC converter in the100 Hz to 100 kHz range.

Selecting correct decoupling capacitors (value andtype) is important. It is recommended that the decou-pling capacitors used are low ESR/ESL, multi-layerceramic chip capacitors. Table 1 lists the recom-mended capacitors at each of the power supply pins ofthe MD1730.

2016 Microchip Technology Inc. DS00002307A-page 7

AN1730

The LDOs should be placed as close to the MD1730 asfeasible. It is recommended that the maximum tracelength used to connect the MD1730's power pins to thedecoupling capacitors does not exceed 5 mm. Therecommended width of the traces should be between0.3 mm and 0.5 mm.

The switching frequencies of the DC/DC convertersshould be synchronized to the CW frequency or theinput clock frequency.

FIGURE 6: Ultra-low Noise Multi Rail Power Supply Example.

MD1730 CW OUTPUT PHASE NOISEMEASUREMENT

Since the MD1730's phase noise is extremely low, themeasured phase noise can be very easily affected byexternal noise sources.

The equipment chosen to do the phase noise measure-ment should be able to measure a large amplitudesquare wave at 5 MHz.

The measurement setup has to be shielded so thatthere is no external background EMI/RFI noise thatcould affect the measurement.

Figure 7 shows the principle of the MD1730 CW outputwaveform phase noise measurement.

In this setup, an RF mixer is used as phase detector.The mixer must be a wide-bandwidth symmetric-diodering type. The two CW waveforms are at 90 degreesphase-shifted with respect to each other. The twochannels under evaluation can belong to one or twoDUT chips of MD1730. Both CW channels can bedriven by a single clock source CLK. The clock sourceand the buffers phase noise will be rejected by thesymmetric mixer. But the CW channel frequencydivider and channel phase delay counter circuits areindependent. The phase noise generated by the twochannels cannot be considered to be correlated toeach other. Therefore, the final phase noisemeasurement should be considered as the sum of thetwo independent MD1730 channels noises.

Phase noise measurements on the MD1730 are shownin Figure 8.

TABLE 1: POWER SUPPLY PIN DECOUPLING CAPACITORS

Supply Rail De. Cap. Value/Voltage Rating Capacitor Type

VLL to GND 1.0 µF/10VDC Low ESR/ESL CeramicX5R or X7R0603/0402

VDD to GND 1.0 µF/10Vdc

VGP to GND 2.2 µF/16VDC

VGN to GND 2.2 µF/16VDC

VCW+ to GND 1.0 µF/16VDC

VCW- to GND 1.0 µF/16VDC

CPF to VCW+ 1.0 µF/16VDC

CNF to VCW- 1.0 µF/16VDC

Note: One per each power supply pin.

+10V

D12

FB6

FB7 MIC5270-10V

D15

FB4

FB5

L5

D9

COM2

L6 D10

D4

D6

VREF VDD

SH

ISO

L1

D1

D5

D7

+10.8 to 12.6V

RTN1GND

RC

OUTA

OUTB

RAMPILIM

COMP

FB

Fd.FwrdRampCurrentLimit

FB1 +5.0VL2 L3D2

D3

D8

D11

FB2

FB3

COM1

+2.5V

D13

VDD VLL

MIC5209+1 to +8V

D14

FB10

-1 to -8V

D16

FB8

FB9

VGPVCW+

VCW-VGN

DAC

MIC5209

MIC5209MIC5209

VCW_ADJ

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

FB

FB

FB

FB

+11V

-11V

MIC3809

M1

M2

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

R14

R15

R16

R17

R18

R19

R20

L4

L7

GND GND

GND

GND

GND

GND

T1

1

2

3

4

5

6

7

8

910

+VDC

R22

R21

LM337

C8'

DS00002307A-page 8 2016 Microchip Technology Inc.

AN1730

FIGURE 7: MD1730 CW Output Phase Noise Measurement Setup.

FIGURE 8: MD1730 CW Output Typical Phase Noise.

Very LowPhase NoiseClock Source

Mixer

CW0

CW1

DUT

90o

0o

Low-PassFiler

SpectrumAnalyzer

CLK

0 1kHz

-180

-170

-160

-150

-140

-130

-120

-110

-100

0.01 0.1 1 10 100

Phas

e N

oise

(dB

c/H

z)

Offset Frequency (kHz)

MD1730 CW Output Phase Noise at 5 MHz, Offset 10 Hz to 100 kHzMixer + Lowpass + HP4195A with ATR -20 dB, RBW 10 Hz

2016 Microchip Technology Inc. DS00002307A-page 9

AN1730

NOTES:

DS00002307A-page 10 2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2016 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITYMANAGEMENTSYSTEMCERTIFIEDBYDNV

== ISO/TS16949==

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-5224-1032-4

DS00002307A-page 11

DS00002307A-page 12 2016 Microchip Technology Inc.

AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.com

AtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455

Austin, TXTel: 512-257-3370

BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088

ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075

ClevelandIndependence, OH Tel: 216-447-0464 Fax: 216-447-0643

DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924

DetroitNovi, MI Tel: 248-848-4000

Houston, TX Tel: 281-894-5983

IndianapolisNoblesville, IN Tel: 317-773-8323Fax: 317-773-5453

Los AngelesMission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608

New York, NY Tel: 631-435-6000

San Jose, CA Tel: 408-735-9110

Canada - TorontoTel: 905-695-1980 Fax: 905-695-2078

ASIA/PACIFICAsia Pacific OfficeSuites 3707-14, 37th FloorTower 6, The GatewayHarbour City, Kowloon

Hong KongTel: 852-2943-5100Fax: 852-2401-3431

Australia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755

China - BeijingTel: 86-10-8569-7000 Fax: 86-10-8528-2104

China - ChengduTel: 86-28-8665-5511Fax: 86-28-8665-7889

China - ChongqingTel: 86-23-8980-9588Fax: 86-23-8980-9500

China - DongguanTel: 86-769-8702-9880

China - GuangzhouTel: 86-20-8755-8029

China - HangzhouTel: 86-571-8792-8115 Fax: 86-571-8792-8116

China - Hong Kong SARTel: 852-2943-5100 Fax: 852-2401-3431

China - NanjingTel: 86-25-8473-2460Fax: 86-25-8473-2470

China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205

China - ShanghaiTel: 86-21-5407-5533 Fax: 86-21-5407-5066

China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393

China - ShenzhenTel: 86-755-8864-2200 Fax: 86-755-8203-1760

China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118

China - XianTel: 86-29-8833-7252Fax: 86-29-8833-7256

ASIA/PACIFICChina - XiamenTel: 86-592-2388138 Fax: 86-592-2388130

China - ZhuhaiTel: 86-756-3210040 Fax: 86-756-3210049

India - BangaloreTel: 91-80-3090-4444 Fax: 91-80-3090-4123

India - New DelhiTel: 91-11-4160-8631Fax: 91-11-4160-8632

India - PuneTel: 91-20-3019-1500

Japan - OsakaTel: 81-6-6152-7160 Fax: 81-6-6152-9310

Japan - TokyoTel: 81-3-6880- 3770 Fax: 81-3-6880-3771

Korea - DaeguTel: 82-53-744-4301Fax: 82-53-744-4302

Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or 82-2-558-5934

Malaysia - Kuala LumpurTel: 60-3-6201-9857Fax: 60-3-6201-9859

Malaysia - PenangTel: 60-4-227-8870Fax: 60-4-227-4068

Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069

SingaporeTel: 65-6334-8870Fax: 65-6334-8850

Taiwan - Hsin ChuTel: 886-3-5778-366Fax: 886-3-5770-955

Taiwan - KaohsiungTel: 886-7-213-7828

Taiwan - TaipeiTel: 886-2-2508-8600 Fax: 886-2-2508-0102

Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350

EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393

Denmark - CopenhagenTel: 45-4450-2828 Fax: 45-4485-2829

France - ParisTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany - DusseldorfTel: 49-2129-3766400

Germany - KarlsruheTel: 49-721-625370

Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44

Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781

Italy - VeniceTel: 39-049-7625286

Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340

Poland - WarsawTel: 48-22-3325737

Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91

Sweden - StockholmTel: 46-8-5090-4654

UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Worldwide Sales and Service

06/23/16