Using The HI5741 Evaluation Module3-2 Designing to Minimize Glitch One cause of Glitch is the time skew between bits of the incoming digital data. Typically the switching time of digital

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TM

AN9626

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Using The HI5741 Evaluation Module

IntroductionThe HI5741 is a 14-bit 100MHz Digital to Analog Converter.This current out DAC is designed for low glitch and highSpurious Free Dynamic Range operation. As a result, thisDAC is ideally suited for Signal Reconstruction and DDS(Direct Digital Synthesis) applications due to its inherent lownoise design.

ArchitectureThe HI5741 DAC is designed with a split architecture tominimize glitch while maximizing linearity. Figure 1 showsthe functional architecture of the device. The 10 leastsignificant bits of the converter are derived by a traditionalR/2R network to binarily weight the 1.28mA (nominal)current sources. The upper 4, or most significant bits, areimplemented as segmented or thermometer decodedcurrent sources. The thermometer decoder converts the

incoming 4 bits to 15 control lines to enable the mostsignificant current sources.

As shown in Figure 2, the thermometer decoder translatesthe 4 bit binary input data into a decode that enablesindividual current sources. For example, a binary code of0110 on the data bits D10 through D13 will enable currentsources I1, I2, I3, I4, I5, and I6. The thermometer decodingarchitecture ensures good differential non-linearity, which isfurther enhanced by the addition of laser trimming. Also,compared to a straight R/2R design, the worst case glitch isgreatly reduced since creating the MSB current is the sum ofcurrent sources I1 through I8. Overall glitch is thereforereduced by a factor of 16. This also reduces the theoreticalswitching skew from current source to current source byusing identically sized switches with identical gain, leakage,and transient responses.

UPPER

SLAVE

IOUT

(LSB) D0

D1

D2

D3

D4

D5

D6

D9

D7

D8

4-BITDECODER

R/2RNETWORK

IOUT

+- CTRL AMP

REF OUT RSET

CTRL AMP

25Ω

14-BITMASTER

REGISTER

OUT

AVEE AGND DVEE DGND VCC

15SWITCHEDCURRENT

CELLS

10 LSBsCURRENT

CELLS

D10

(MSB) D13

REGISTER

DATABUFFER/LEVEL

SHIFTER

OVERDRIVEABLEVOLTAGE

REFERENCE

INCLK

REF CELL

D11

D12

FIGURE 1. HI5741 BLOCK DIAGRAM

Application Note July 1996

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Designing to Minimize GlitchOne cause of Glitch is the time skew between bits of theincoming digital data. Typically the switching time of digitalinputs are asymmetrical, meaning that the turn off time isfaster than the turn on time. Unequal delay paths through thedevice can cause one current source to change beforeanother. To minimize this, the Intersil HI5741 employes aninternal register just prior to the current sources which isupdated on the rising clock edge. In traditional DACs theworst case glitch usually occurs at the major transition i.e.,01 1111 1111 1111 to 10 0000 0000 0000. But in the HI5741the worst case glitch is moved to the 00 0011 1111 1111 to11 1100 000 0000 transition. This is achieved by the splitR/2R segmented current source architecture. Thisdecreases the amount of current switching at any one timeand reduces the glitch by a factor of 16.

Since the glitch is a transient event, this leads designers tobelieve that a simple low pass filter can be used to eliminateor reduce the size of the glitch. In effect, low pass filtering aglitch tends to “smear” the event and does little to removethe energy of the transient.

Input Timing/Logic LevelsThe HI5741 has a maximum clock rate specification of100MHz. The data setup time before the 50% point of therising edge of the clock is tS = 3ns (Min) and the hold time istH = 0.5ns (Min). Logic levels are 0.8V (Max) for an input lowand 2.0V (Min) for a logic high. The HI5741 is both TTL andCMOS input compatible.

Integral LinearityThe HI5741 has a full-scale range of 20.48mA. When drivinga 64Ω load the full scale voltage swing is 0V to -1V (theinternal 227Ω ladder resistance in parallel with the 64Ω loadresults in an equivalent 50Ω load resistance). Most videoand communication applications use a 1VP-P voltage swingwhich yields 20.48mA full scale current sink capability. Witha 1VP-P voltage swing on the HI5741 output an LSB is:

LSB = Full Scale Range/(2N-1)

where N is the number of bits and the Full Scale Range is1VP-P.

The LSB size for this application is 62.5µV. To determine theIntegral Linearity of the HI5741 the bit weights of each majortransition is taken. The Best Fit Straight Line method is usedto calculate the overall INL. Measurements are taken at bits0 through 9 at each bit transition. Then all combinations ofthe upper 4 bits are measured. Finally some worst casecodes are measured and the full scale is measured. Oncethis is completed a best fit straight line is drawn through thedata points and the worst case deviation is determined.

BIT 10

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

SUMMINGJUNCTION (IOUT)

4-BIT BINARYTO

THERMOMETERDECODER

BIT 11

BIT 12

BIT 13 (MSB)

FIGURE 2. THERMOMETER DECODER

V

t(ps)

HEIGHT (H)

WIDTH (W)

GLITCH AREA = 1/2 (H x W)

FIGURE 3. GLITCH AREA

tHtS

CLK

D11 - D0

FIGURE 4. HI5741 DATA TIMING

Application Note 9626

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The worst case integral linearity of the HI5741 is specified tobe less than 1.5 LSB. The implementation of laser trimassures 14-bit match from current cell to current cell.Figure 5 graphically illustrates the typical linearityperformance of the HI5741.

Differential Linearity and Missing CodesFor a D/A Converter, the differential non-linearity is the worstcase deviation from the ideal step size throughout the entiretransfer curve. For the HI5741, this worst case deviation issaid to be at most 1.0 LSB in magnitude. For any given D/Aconverter o guarantee no missing codes the converter mustbe monotonic.

The definition of monotonicity is; as the input code isincreased the output should increase. When an input code isincreased and the output of the DAC does not increase orreverses direction, then this converter is assumed to be non-monotonic, or missing codes.

Monotonicity is guaranteed as long as a DNL value ofgreater than -1.0 LSB is maintained.

Shown in Figure 6, as the input code increases the outputvoltage should increase. When an error of -1.0 LSB or less isincurred, that bit can be assumed to be a missing code sincethe output did not increase but rather remained the same.

The Control AmplifierThe internal control amplifier converts the reference voltageappearing on the REFOUT pin to a reference current via thecircuit shown in Figure 7A. The bias voltage generated at thecontrol amplifier output is used to mirror this current in all ofthe precision current cells.

Adjusting Full ScaleThe RSET pin is used to set the Full Scale Output Current.The output current is a function of the reference voltageapplied to the CONTROL AMP IN pin and the value of theRSET resistor. To calculate the IOUT Full Scale Current usethe following formula:

IOUT Full Scale = 16 x (REFOUT/RSET)

So where REFOUT = -1.20V

and RSET = 931Ω

IOUT = -20.62mA

To adjust the output full scale current, use a potentiometer inrheostat mode as shown in Figure 7B.

The Evaluation BoardThe HI5741 Evaluation board is a 1/2 size daughter boarddesigned to interface to the HSP-EVAL board. When usedtogether these boards create a flexible and powerful DDSsystem. The HSP45116 board is used to generate the highspeed digital sine wave patterns for the D/A module. The

FIGURE 5A. INL TYPICAL PERFORMANCE CURVE

1.5

1.0

0.5

0

-0.5

-1.0

-1.50 5000 10,000 15,000

CODE

LS

B

FIGURE 5B. DNL TYPICAL PERFORMANCE CURVE

0.8

0.5

0.25

0

-0.25

-0.5

-0.80 5000 10,000 15,000

CODE

LS

B

00

01

10

11

INPUT CODE GREATER THAN ZERO

OUTPUTVOLTAGE

-0.5 LSB ERROR

(MISSING CODE)

GREATER THAN

ERROR-1.0 LSB

FIGURE 6. DNL EXAMPLE

CONTROL-+ AMPOUTREFOUT

VEE

RSET

FIGURE 7A.


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HI5741 board reconstructs the incoming digital data to ananalog representation that can be analyzed on a spectrumanalyzer or oscilloscope.

Plugging InAfter setting-up the HSP45116 board and the HI5741 board;power should be applied to the banana jacks. A +5V, and a-5.2V supply will be needed. To reduce noise the powersupply leads should be twisted pairs.

Connect the interface cable to an IBM PC or compatible’sparallel port. Power should be applied to the board and thenrun the software directly from floppy disk. To run the softwareplace the floppy disk into drive A: and type:

A: NCOMCTRL

the HSP45116 Control Panel will be loaded. To exercise theboard the following parameters should be set:

BINFMT = 0

and then set the Center Frequency to:

CENTER FREQUENCY = 01000000HEX

where the center frequency is in hex. At this point the outputof the HI5741 DAC module should be converting a sine waveat 48kHz. Connect the output of the HI5741 module to anoscilloscope.

DDS InterfaceThe HSP45116 board is a TTL/CMOS compatible logicboard. The HI5741 is a TTL/CMOS compatible logic D/Aconverter. The design of the DAC module is to interface tothe 14 Most Significant Bits of the NCO. The HI5741 moduleshould be plugged into P2 of the HSP-EVAL board.

Spurious Free Dynamic RangeThe Spurious Free Dynamic Range of the HI5741 DAC is themost important specification for communication applications.This specification shows how Integral Linearity, Glitch, andSwitching noise affect the spectral purity of the output signal.Several important things must be noted first.

When a quantized signal is reconstructed, certain artifactsare created. Let’s take the example of trying to recreate a1MHz sine wave with a 1VP-P output. In the frequencydomain the fundamental should appear at 1MHz as shown inFigure 8.

The fundamental of a pure 1MHz tone should appear as animpulse in the frequency domain at 1MHz. In a sampledsystem noise terms are produced near the samplingfrequencies called aliases. These aliases are related to thefundamental in that they are located at ±fN around thesampling frequency as shown in Figure 9.

So for a 1MHz fundamental and a 5MHz sampling rate analias term is created at 4MHz and 6MHz. A (SIN)/X functionshaping is also induced by sampling a signal. Aliasescontinue up through the frequency spectrum repeating aroundthe sampling frequency and its harmonics (i.e., 2fS, 3fS, 4fS).

Also, when dealing with devices that posses high degrees ofdynamic range such as the HI5741, one must contend withsome fundamental limitations of the measurement systembeing used. Since the HI5741 typically meets (and in somecases exceeds) the dynamic range of the spectrum analyzerused to evaluate the device, the use of a notch filter can greatlyalleviate the burden being placed on the equipment. By filteringout the fundamental, and in the process eliminating a largepercentage of the power as seen by the spectrum analyzer, onecan bring to bear the full dynamic range of the equipment,therefore truly evaluating the dynamic range of the DAC. Referto Application Note AN9619 “Optimizing Setup Conditions forHigh Accuracy Measurements of the HI5741” for further detailson the use of filtering for evaluation purposes.

A reconstructed sine wave out of the HI5741 is not ideal andas such has harmonics of the fundamental. The differencebetween the magnitude of the fundamental and the highest

RSET (17)

100Ω

909Ω

FIGURE 7B. FULL SCALE OUTPUT APPLICATION CIRCUIT

f

AMPLITUDE(dB)

1MHz

0

-85

-50

NOISE FLOOR

FUNDAMENTAL(PURE TONE)

fN

FIGURE 8. FREQUENCY PLOT OF 1MHz TONE

f

AMPLITUDE(dB)

1MHz

0

-85

-50

FUNDAMENTAL

fS4MHz

ALIAS(fS - 1MHz)

SAMPLING FUNCTION(SIN X)/X

fN

FIGURE 9. SAMPLING ALIAS PRODUCTS


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noise spur whether it is harmonically related to thefundamental or not, is the definition of Spurious FreeDynamic Range. Figures 10 through 15 are sample plotstaken of the HI5741 at various frequencies. In all the cases

presented, the fundamental has been notched out to makemaximum use of the dynamic range of the spectrumanalyzer. Oscilloscope plots of the unfiltered signals are alsoincluded.

Typical Performance Curves

FIGURE 10A. OSCILLOSCOPE PLOT FIGURE 10B. SAMPLE PLOT

FIGURE 10. A 1MHz FUNDAMENTAL TO . fCLK = 20MHz

FIGURE 11. A 1MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED

CH1 200mV~M 100ns

START 500kHz STOP 10.000MHz

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

SFDR = 80.17dBc

dB

fCLK2

---------------

CENTER 1.000MHz SPAN 1.000MHz

SFDR = 86.83dBc0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

dB


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FIGURE 13. A 1MHZ FUNDAMENTAL TO . FCLK = 40MHZ

Typical Performance Curves (Continued)

CH1 200mVM 50.0ns


0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

dB

SFDR = 87.67dBc

fCLK2

---------------

CH1 200mV~M 100ns START 500kHz STOP 20.00MHz

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

dB

SFDR = 79.34dBc

fCLK2

---------------


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Using the HSP-EVAL Test PlatformThe HSP-EVAL DDS platform allows quick testing of spectralproperties of a given DAC. The Numerically ControlledOscillator/Modulator (NCOM) generates digital sinewavepatterns that are loaded into the DAC. The analog output ofthe DAC is the reconstructed sinewave pattern. The programNCOMCTRL allows downloading of the desired centerfrequency. The clock or sampling frequency is 25MHz. Todetermine the center frequency codeword the followingformula is used:

Center FrequencyHEX = (Desired Frequency/25MHz) x 232

This 32-bit hexadecimal word will create the fundamental. Inorder to ensure zero phase offset the cursor should bemoved to the LOAD select. Pressing the spacebar the valueshould be toggled from 1 to 0 and back to 1 again. This willensure that any previous values in the phase register arecleared and the sinewave pattern is started at zero phase.

The HSP-EVAL setup is powered from the DAC modulepower-supply banana jacks. The output of the setup can beobserved on an oscilloscope or a spectrum analyzer.

FIGURE 14. A 1MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED



Typical Performance Curves (Continued)

CENTER 1.000MHz SPAN 1.000MHz

SFDR = 86.83dBc

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

dB

CH1 200mV~M 50.0ns


0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

dB

SFDR = 75.34dBc

fCLK2

---------------


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Evaluating Multi-Tone Power Ratio (MTPR)PerformanceFor cellular base station users, the HI5741 evaluationmodule provides accessibility to the digital inputs via theedge connector. Unlike DDS applications, base station usersprovide multi-tone inputs to the DAC, and evaluate thedynamic range performance under these conditions.

In testing for MTPR, a ten tone pattern is created and inputto the HI5741 at a clock frequency of 20MHz. One tone(typically the fifth) is removed in order to observe the thirdorder harmonic products (2f1-f2, 2f2-f1,etc.) created by theDAC in the resulting ‘dead zone’. The multi-tone power ratioof the device is then measured as the dynamic range frompeak power to peak distortion.

Figures 17 and 18 graphically illustrate two examples of testpatterns used to evaluate MTPR performance on theHI5741. In figure 17, a ten tone pattern is used with tonesranging from 2MHz to 3MHz with 100kHz tone spacing.Figure 18 illustrates a similar pattern, however 40kHz tonespacing is used. In both cases, the fifth tone has beenremoved to observe the third order harmonic products andthe amount of distortion they introduce into the spectrum.

PERSONAL COMPUTER

SPECTRUM ANALYZER

HSP-EVAL/HPS45116NCOM EVALUATION BOARD

HSP45116NUMERICALLYCONTROLLEDOSCILLATOR

50ΩSMA

CABLE

HI5741

DAC

CLOCKCIRCUIT

+5V -5.2V

HI5741DAC MODULE

INCLUDEDSOFTWARE

PC INTERFACE

POWERSUPPLY

FIGURE 16. INTERSIL HI5741/DDS EVALUATION SYSTEM SETUP BLOCK DIAGRAM


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Test Patterns

FIGURE 17A. SCOPE PLOT OF MTPR TEST WAVEFORM FIGURE 17B. MTPR PERFORMANCE

FIGURE 17C. SCOPE PLOT OF MTPR TEST WAVEFORM FIGURE 17D. MTPR PERFORMANCE

CH1 200mVM 2.00µs

START 1.500MHz STOP 3.500MHz

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

dB

MTPR = 77.17dBc

CH1 200mVM 200µs START 1.9500MHz STOP 2.4000MHz

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

dB

MTPR = 81.83dBc


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Schematic Diagram

3231302928272625242322212019181716151413121110987654321

DB0DB2

DB7DB9

DB11DB13

J1A

GND

3231302928272625242322212019181716151413121110987654321

J1B

GND

VCCD

3231302928272625242322212019181716151413121110987654321

DB1DB3DB5DB6

DB10DB12

J1C

GND

CLK

15

121110

987654321

16181728

CLKD0 (LSB)D1D2D3D4D5D6D7D8D9D10D11

DVDDDVEEDVSSDVSS

IOUTIOUTB

COMPINCOMPOUT

REFOUTRSETARETAVSSAVEE

HI5741

50ΩR20

212024252623192722

R164Ω

R264Ω

SMAJ3

GND

GND

C10.1µF

C90.01µF

AVEE

GND

DVDDDVEE

+5V

C610µF

DVDD

ECL SUPPLY

C710µF

VEE

GND

-5.2V

SYSTEM GND

DVEE

GND GND

C3C20.1µF 0.01µF

NOTE: Place as close to device pin 18 as possible.

AVEE

GND GND GND

C5C4C100.01µF10.0µF 0.1µF

NOTE: Place as close to device pin 22 as possible.

DB4

DB80ΩR19

1413

D13 (MSB)D12

200ΩR18

R17 200ΩR16 200ΩR15 200ΩR14 200ΩR13 200ΩR12 200ΩR11 200ΩR10 200ΩR9 200ΩR8 200ΩR7 200ΩR6 200ΩR5 200Ω

SMAJ2

R3 976Ω

DVDD

GND GND

C313C3120.1µF 0.01µF

R20

10ΩGNDGND

FIGURE 18.

NOTES:

1. All passive components are SMT devices, exceptpolarized capacitors.

2. Place ground shapes on top and bottom layers. Use splitplanes for analog, digital and power.

Ap

plicatio

n N

ote 9626

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FIGURE 19A. SILKSCREEN

FIGURE 19B. LAYER 1

FIGURE 19C. LAYER 2


3-12

FIGURE 19D. LAYER 3

FIGURE 19E. LAYER 4

FIGURE 19F. SILKSCREEN


3-13

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate andreliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may resultfrom its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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Documents

Using The HI5741 Evaluation Module3-2 Designing to Minimize Glitch One cause of Glitch is the time skew between bits of the incoming digital data. Typically the switching time of digital