Using the ETM PWM Function in the HT66F40 - Holtek · 2016. 12. 22. · Using the ETM PWM Function in the HT66F40 2 The counter clock source can be selected as fSYS/4, fSYS, fH/16,

Using the ETM PWM Function in the HT66F40

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D/N：AN0242E

Introduction

The HT66Fx0 series devices include Timer Modules (TM) which are composed of various

timer and PWM functions combined into the same module. Functions include general

timer, external counter, programmable duty/period PWM output or single pulse output and

input capture etc. The Timer Modules come in three types, namely Compact Type TM

(CTM), Standard Type TM (STM) and Enhanced Type TM (ETM).

This application content uses the HT66F40 to describe the PWM function in the ETM .

Operating Principles

At the core of ETM is a 10-bit count-up/count-down counter and three comparators as

shown in the following diagram:

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Enhanced Type TM Block Diagram


2

The counter clock source can be selected as fSYS/4, fSYS, fH/16, fH/64, fTBC or the TCK1

input by setting up the T1CK0~T1CK2 bits. Three internal comparators, CCRP, CCRA

and CCRB are used to setup the compare values. CCRP, having a 3-bit width, is only

compared with the high 3 bits of the counter. CCRA and CCRB are the same width as the

counter and are therefore compared with all counter bits. When the related registers are

setup and the TM is enabled, the counter will start counting up or down and the system

will compare the preset CCRA and CCRB values with the counter value. When the

counter overflows or equals the preset CCRA or CCRB values, it will overflow

automatically and generate an interrupt signal. It may also generate changes in the TM

output pins. The TM1DH/TM1DL counter registers are read only and cannot be modified

by the application program. The only way to manually clear the counter to zero is by

setting the T0ON bit from 0→1 The T1APOL/T1BPOL bits are used to control the TP1A

and TP1B output pin polarity. When set high the TP1A and TP1B outputs will be inverted.

HT66F40 Output Pin Description:

Pin Function Description TMPC0 PRM2

TP1A CCRA compare match output mode or input capture mode, external pulse output mode, PWM output mode

T1ACP0 : 1 : enable TP1A 0 : I/O or other functions

TP1APS : 0 : Set TP1A on PA1 1 : Set TP1A on PC7

TP1B_0 CCRB compare match output mode or input capture mode, external pulse output mode, PWM output mode

T1BCP0 : 1 : enable TP1B_0 0 : I/O or other functions

Admit TB1B_0 on PC0


T1BCP1 : 1 : enable TP1B_1 0 : I/O or other function

Admit TB1B_1 on PC1


T1BCP2 : 1 : enable TP1B_2 0 : I/O or other function

TP1B2PS : 0 : Set TP1B_2 on PC5 1 : Set TP1B_2 on PE4

There are four sub operational modes when the ETM is in the PWM mode.


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Mode 1: Edge-aligned Mode. When T1CCLR is 0, then CCRP controls the PWM

period, also CCRA and CCRB control the TP1A and TP1B channel PWM duty. When

T1CCLR is 1 CCRA controls the PWM period, and CCRB controls the TP1B channel

PWM duty. In this latter case the TP1A channel is not used.

Edge-triggered PWM waveform for T1CCLR = 1:

When T1CCLR=1, T1PWM[1,0] = 00, the ETM is in Mode 1. Set a value larger than 0 but

smaller than the CCRA value into CCRB. When T1ON is set to 1, the TP1B output inverts,

as setup by the condition of T1BOC, and the counter will start counting up until it matches

the CCRB value. Here the interrupt flag, T1BF, will be set high and TP1B will invert again.

When the counter count-up value matches the CCRA value, the counter will be cleared to

zero and the interrupt flag, T1AF, will be set high and TP1B will invert again. In this way

the PWM waveform is generated where the period is controlled by CCRA and duty

controlled by CCRB.

Note: In this condition, if TP1A is setup in the PWM mode, then it cannot generate a PFD

signal. If a PFD output from TP1A is required at the same time when the TP1B is

generating a PWM signal, then set TP1A into the compare match output mode. The PFD

period generated on TP1A will be twice that setup by the CCRA value.


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Mode 2: Edge-aligned mode. Here CCRP controls the PWM period, also CCRA

controls the PWM duty for the TP1A channel and CCRB controls the PWM duty for

the TP1B channel.

Mode 2 Timing:

When T1CCLR=0, T1PWM[1,0] =00, the ETM is in Mode 2.

For the TP1A channel, when T1ON is set to 1, TP1A will invert based on the value of the

TP1A0C bit, and the counter starts counting up until it matches CCRA. Now the interrupt

flag T1AF will be set and the TP1A pin will again invert. The counter will be cleared to

zero when it matches the CCRP value at which point the interrupt flag T1PF will be set

and once again the TP1A pin will invert. A PWM waveform cycle is thus generated in this

way with CCRP controlling the period and CCRA controlling the duty.

For the TP1B channel, when T1ON is set to 1, TP1B will invert based on the value of the

T1BOC bit, and the counter starts counting until it matches CCRB. Now the interrupt flag

T1BF will be set and the TP1B pin will again invert. The counter will be cleared to zero

when it matches the CCRP value at which point the interrupt flag T1PF will be set and

once again the TP1B pin will invert. A PWM waveform cycle is thus generated in this

way with CCRP controlling the period and CCRB controlling the duty.


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Mode 3: Center-aligned Mode. Here CCRA controls the PWM period and CCRB

controls the PWM duty for the TP1B channel.

Mode 3 Timing:

When T1CCLR=1, T1PWM[1,0] = 01/10/11, then the ETM is in Mode 3.

If T1PWM[1,0] =01, then the interrupt flag,T1AF, will be set to 1 only when the count-up

counter matches the CCRA value. If T1PWM[1,0] =10, the interrupt flag, T1PF, will be set

to 1 only when the count-down counter matches the CCRP value. If T1PWM[1,0] =11,

then the two interrupt flags will be set to 1 when a match occurs during either count-up or

count-down.

For the TP1B channel, it is necessary to give a value which is larger than zero and

smaller than CCRA for CCRB. When T1ON is set to 1, the counter starts counting up.

When the counter matches the CCRB value, the TP1B pin will invert. The counter will

start counting down after it matches the CCRA value. When the counter matches the

CCRB value, the TP1B pin will invert again. When the count-down counter becomes zero,

it will return again to counting up. The TP1B pin will invert again when the counter

matches the CCRB value. A PWM waveform whose period is equal to double the CCRA

value will thus be generated. The width of the PWM active level bit is equal to double the

CCRB value. The PWM active level is controlled by T1B0C. When this bit is 1, the PWM

signal is active high and active low when the bit is 0.

Note: No PFD signal can be generated when the TP1A channel is operating in the PWM

Mode.


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Mode 4: Center-aligned Mode. Here CCRP controls the PWM period, also CCRA

controls the PWM duty for TP1A and CCRB controls the PWM duty for TP1B.

Mode (4) Timing:

When T1CCLR=0, T1PWM[1,0] =01/10/11, then the ETM is in Mode 4.

When T1PWM[1,0] =01, the interrupt flag, T1AF, will be set to 1 only when the count-up

counter matches the CCRA value. When T1PWM[1,0] =10, the interrupt flag, T1PF, will

be set to 1 only when the count-down counter matches the CCRP value. When

T1PWM[1,0] =11, then both interrupt flags will be set to 1 when a match occurs during

either a count-up or count-down.

For the TP1A channel, when T1ON is set to 1, the counter will start counting up. When

the counter matches the CCRA value, TP1A will invert. The counter will then start

counting down after its value matches the CCRP value. When the counter matches the

CCRA value, TP1A will invert again. The counter will start counting up again when the

count-down value reaches zero. TP1A will invert again when the counter value matches

the CCRA value. A PWM waveform on the TP1A channel is thus generated with the

period equal to double the CCRP value. The PWM active level bit is double that of the

CCRA value. The PWM active level bit is controlled by the T1A0C bit. When this bit is 1,

the PWM signal is active high and active low if the bit is low.

For the TP1B channel, when T1ON=1, the counter starts counting up. When the counter

matches the CCRB value, TP1B will invert. The counter starts counting down when its

value matches the CCRP value. TP1B will invert when the counter matches the CCRB

value. The counter will start again to count up when the count-down value reaches zero.

TP1B will invert once again when the counter matches the CCRB value. A PWM

waveform on the TP1B channel is thus generated with a period equal to double the

CCRP value. The width of the PWM active level is equal to double the CCRB value. The

PWM active level bit is controlled by the T1B0C bit. When this bit is 1, the PWM signal is

active high or active low when the bit is 0.


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Before entering the PWM mode, set the related bits in the PRM2 register to configure the

TP1A and TP1B pins to their respective I/O lines, and then configure the TMPC0 register

to enable the TP1A and TP1B functions that corresponds to the I/O pins. The I/O ports

related to the TP1A and TP1B pins should be setup as outputs with a low value,

otherwise the PWM active level outputs will be inverted.

PWM output quick setup is shown in the following table:

Step Operation Register Bit Setting Function Description

1 Setup clock source TM1C0 T1CK0~T1CK2 Select ETM clock source

2 Setup PWM and Duty

cycle TM1C1

T1CCLR :

0 : to TP1A CCRP→cycle

CCRA→duty ratio to TP1B

CCRP→cycle CCRA→duty ratio

1 : to TP1B CCRA→cycle

CCRB→duty ratio

Select CCRP or CCRA to be the PWM cycle control register

TM1C0 T1RP2~T1RP0

3 Setup CCRP, CCRA,

CCRB registers TM1AH/TM1ALTM1BH/TM1BL

Low 10-bit digit Setup PWM cycle and duty

4 Setup Alignment

Mode TM1C2

T1PWM1、T1PWM0 : 00 : Edge-aligned mode

01 : Center-aligned mode 010 : Center-aligned mode 111 : Center-aligned mode 2

Setup counter mode

TM1C1 T1AM1、T1AM0=10 10 is the PWM output mode in TP1A channel

5 Setup ETM operation

mode TM1C2 T1BM1、T1BM0=10 10 the PWM output mode in TP1B

channel

6 Select ETM output

pin TMPC0

T1ACP0 : T1BCP0、T1BCP1、T1BCP2 Enable the related ETM pin function

TM1C1 T1A0C :

0 : output low level 1 : output high level

7 Setup TP1A, TP1B

initial output level bit

TM1C2 T1B0C :

0 : output low level 1 : output high level

Setup the TP1A,TP1B output level before first compare match

TM1C1 T1AIO1/T1AIO0 : 10 : output PWM

8 Setup TP1A, TP1B

output function TM1C2

T1BIO1/T1BIO0 : 10 : output PWM

10 means PWM output

TM1C1 T1APOL :

1 : output inverted 0 : output non-inverted

9 Setup TP1A, TP1B

output polarity

TM1C2 T1BPOL :

1 : output inverted 0 : output non-inverted

Invert control for TP1A, TP1B

INTC1 MF1E 10

Setup interrupt enable bit MFI1 T1PE , T1AE, T1BE

Enable ETM and multi-functional interrupts

11 Enable ETM TM1C0 T1ON 0→1 Reset counter, enable ETM

T1PAU 0→1 Disable ETM, keep the counter value12 Disable ETM function TM1C0

T1ON 1→0 Disable ETM, keep the counter value

TM1C1

T1AIO1/T1AIO0 : 00 : force TP1A to output

inactive output level 01 : force TP1A to output

active level 13

Setup output functions

TM1C2

T1BIO1/T1BIO0 : 00 : force TP1B to output

inactive level 01 : force TP1B to output

active level

TP1A/TP1B are forced to fixed output levels but the ETM keeps running. The active level, whether 1 or 0, is

controlled by T1A0C/T1B0C.


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Application Circuit

Description:

The ETM, in the PWM or Single Pulse mode, can provide two channels, TP1A/TP1B, as

PWM or single pulse outputs.

The first channel output is TP1A (Pin 24).

The second channel output is TP1B_0 (Pin 10), TP1B_1 (Pin 9) or TP1B_2 (Pin 13). The

second channel can select any single pin or any two pins. If all three pins are selected,

then the PWM output will be seen on each pin.


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S/W Flowchart (Mode 1)

Program Description (Mode 1)

The example describes how to generate a PWM Mode1 signal using the ETM.

Main Program Flow: The program starts with an initialization of all the data registers. Set

CP0C, CP1C to 08H and disable the comparator function. Clear ACERL and SOMEN to

zero and disable the analog inputs as well as the LCD functions. Set TMPC0 to 0F0H to

enable the TP1A, TP1B_0, TP1B_1 and TP1B_2 pins.

Set TM1C0 to 00000000B, namely T1PAU=0, to disable the counter pause function.

T1CK[2:0]=000B means the ETM clock source frequency is a quarter of the system

frequency. T1ON=0 is to disable the ETM. Set TM1C1 to 00111001B, namely T1AM[1:0]

=00, to select TP1A in the ETM to operate in the compare match mode. T1AIO[1:0] =11 is

to invert the TP1A output. T1CCLR=1 selects a TP1CCRA compare match to clear the

counter to zero.


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Set TM1C2 to 10100000B, namely T1BM[1:0] =10, to setup TP1B in the ETM to operate

in the PWM mode. When T1BIO[1:0] =10, TP1B will output the PWM signal. T1B0C=0

will set the PWM active level generated on TP1B to active low. T1PWM[1:0]=00 is to

select the edge-aligned mode. Set TM1AH/TM1AL=01H/00H and TM1BH/TM1BL=

00H/40H, to generate a PFD period with a value of 512 clock cycles on TP1A, and a

PWM signal with a period of 256 clock cycles on TP1B. The active level will be a low level

with a width of 64 clock cycles.

Program Example - Example 1

configuration option： High Freq.OSC: XTAL Low Freq.OSC: LIRC Fsub clock source: LIRC WDT clock source fs: fsub HIRC frequency selection: 4MHz PTC clock source fptc: LIRC WDT: Disable I/O or RESB Function: IO ;other option select by user.

Program code and description: see attachment.

Actual output waveform and description is shown below:

T1PWM=00 ; CCLR=1 ; AOC=1 ; BOC=0.

In the above figure, the upper part is the PFD output and the lower part is the PWM

output.

TP1A Compare output Duty is 1:1 256us

TP1B Duty : 64us

TP1B Period : 256us


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S/W Flowchart - Mode 2

Program Description - Mode 2

The example here describes how to generate a PWM Mode2 signal using the ETM.

Main Program Flow: The program firstly starts with an initialization of all the data registers.

Set CP0C, CP1C to 08H and disable the comparator function. Clear ACERL and

SCOMEN to zero and disable the analog inputs as well as the LCD functions. Set TMPC0

to 0F0H to enable the TP1A, TP1B_0, TP1B_1 and TP1B_2 pins.


T1CK[2:0] =000B means the ETM clock source frequency is a quarter of the system

frequency. T1ON=0 is to disable the ETM. The T1RP bits are setup for a value of 768

clock cycles.

Set TM1C1 to 10100000B, namely T1AM[1:0]=10, to have the TP1A in the ETM operate

in the PWM mode. When T1AIO[1:0] =10, the TP1A will output the PWM signal.

T1A0C=0 is to set the PWM active level generated on TP1A as active low. T1CCLR=0

selects a TP1CCRP compare match to clear the counter.

Set TM1C2 to 10101000B, namely T1BM[1:0] =10, to select the TP1B in the ETM to

operate in the PWM mode. When T1BIO[1:0] =10, TP1B will output the PWM signal.

T1B0C=1 is to set the PWM active level generated on TP1B as active high. T1PWM[1:0]

=00 selects the edge-aligned mode.


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Set TM1AH/TM1AL=01H/00H and TM1BH/TM1BL=00H/40H, so the PWM signal

generated on TP1A will be 768 clock cycles with an active low level of 256 clock cycles.

The PWM period generated on TP1B will be 768 clock cycles with an active high level of

64 clock cycles.

Program Example (Mode 2)

Configuration option : High Freq.OSC: XTAL Low Freq.OSC: LIRC Fsub clock source: LIRC WDT clock source fs: fsub HIRC frequency selection: 4MHz PTC clock source fptc: LIRC WDT: Disable I/O or RESB Function: IO ;other option select by user.


Actual output waveform and description is shown below.

In the above figure, the upper part is the PWM output waveform in the CCRA channel

while the lower part is that of the CCRB channel.

TP1PWM=00 ; CCLR=0 ; AOC=0 ; BOC=1.

TP1A Duty : 256us

TP1A Period : 768us

TP1B Duty : 768us

TP1B Period : 768us


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Program Description - Mode 3



CP0C, CP1C to 08H and disable the comparator function. Clear ACERL and SCOMEN to

zero and disable the analog inputs as well as the LCD functions. Set TMPC0 to 0F0H to



T1CK[2:0] =000B selects the ETM clock source frequency is a quarter of the system

frequency. T1ON=0 is to disable the ETM.

Set TM1C1 to 10100001B, namely T1AM[1:0] =10, to select TP1A in the ETM to operate

in the PWM mode. When T1AIO[1:0] =10, TP1A will output the PWM signal. T1A0C=0

sets the PWM active level generated on TP1A as active low. T1CCLR=1, selects a

TP1CCRA compare match to clear the counter.

Set TM1C2 to 10101011B, namely T1BM[1:0] =10, to select TP1B in the ETM to operate

in the PWM mode. When T1BIO[1:0] =10, TP1B will output the PWM signal. T1B0C=1 is

to set the PWM active level generated on TP1B as active high. T1PWM[1:0] =11 selects

the center-aligned mode.


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Set TM1AH/TM1AL=01H/00H and TM1BH/TM1BL=00H/40H. TP1A will not generate a

PFD waveform output. The PWM period generated on TP1B is 512 clock cycles with an

active high level of 128 clock cycles.

Program Example - Mode 3

Configuration option: High Freq.OSC: XTAL Low Freq.OSC: LIRC Fsub clock source: LIRC WDT clock source fs: fsub HIRC frequency selection: 4MHz PTC clock source fptc: LIRC WDT: Disable I/O or RESB Function: IO ;other option select by user.


Actual output waveform and description is shown as below:

TP1PWM=11 ; CCLR=1 ; BOC=1.

Duty : 128us

Period: 512us


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Program Description - Mode4



CP0C, CP1C to 08H and disable the comparator function. Clear ACERL and SCOMEN to

zero and disable the analog inputs as well as the LCD function. Set TMPC0 to 0F0H to



T1CK[2:0] =000B will select the ETM clock source as fsys/4. T1ON=0 will disable the

ETM. T1RP=110B means 768 clock cycles.

Set TM1C1 to 10100000B, namely T1AM[1:0] =10, to select TP1A in the ETM to operate

in the PWM mode. When T1AIO[1:0] =10, TP1A will output the PWM signal. T1A0C=0

will set the PWM active level generated on TP1A to active low. T1CCLR=0 selects a

TP1CCRP compare match to clear the counter.

Set TM1C2 to 10101011B, namely T1BM[1:0] =10, to select TP1B in the ETM to operate

in the PWM mode. When T1BIO[1:0]=10, TP1B will output the PWM signal. T1B0C=1

sets the PWM active level generated on TP1B as active high. T1PWM[1:0] =11 selects

the center-aligned mode.


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Set TM1AH/TM1AL=01H/00H and TM1BH/TM1BL=00H/40H. The PWM cycle generated

from TP1A is 1536 clock cycles with an active low level of 512 clock cycles. The PWM

cycle generated from TP1B is 1536 clock with an active high level of128 clock cycles.

Program Example - Mode 4

configuration option : High Freq.OSC: XTAL Low Freq.OSC: LIRC Fsub clock source: LIRC WDT clock source fs: fsub HIRC frequency selection: 4MHz PTC clock source fptc: LIRC WDT: Disable I/O or RESB Function: IO ;other option select by user.

Program code and description: attached file.

The actual output waveform is shown below.

TP1PWM=11 ; CCLR=0 ; AOC=0 ; BOC=1.

Conclusion

The application has described the ETM PWM function which the user can configure

according to their application requirements.

TP1A Duty:512us

TP1B Duty:128us

TP1B Period : 1536us

TP1A Period:1536us

Documents

Using the ETM PWM Function in the HT66F40 - Holtek · 2016. 12. 22. · Using the ETM PWM Function in the HT66F40 2 The counter clock source can be selected as fSYS/4, fSYS, fH/16,