Using Current Sense PROFETs and Speed TEMPFETs in a High

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PRODUCT APPLICATIONS

A high power bridge driver can be con-structed from Smart SIPMOS high side andlow side switches. Design issues areaddressed, including the use of simulationmodels and auxiliary protection circuits.

Using Current Sense PROFETs and Speed TEMPFETs in a High Current H-Bridge Motor Driver

Description/Overview of Bridge Drivers

TRILITHIC Smart Power full bridge drivershave been introduced in a single package usinga combination of PROFET high side switcheswith a low side MOSFET switching transistors.This synergistic combination relies on the PRO-FET high side switch to implement motor direc-t ion contro l and a var iety of protect ionfunctions, while including two fast low costMOSFET transistors in the same package toprovide PWM control of the motor speed. Withthe TRILITHIC bridge drivers it is possible toimplement H-Bridge drivers for specializedfunctions, such as automotive door locks, aswell as more general purpose low power motorcontrol, using sign-magnitude modulation (Fig.1). Available TRILITHIC H bridges range in con-tinuous operating current range from 3A for P-DSO-28 packaged parts like the BTS770, up to15A in the case of the BTS780. However, thereare applications which require lower RDS[on]than the BTS780, for reasons of maximum out-put current, efficiency or thermal performance.For these a different solution is required.

Concept for High Power Bridge

This Product Application Note will describea concept for a higher power, high efficiency H-

Bridge driver for 12-24 volt applications usingdiscrete Smart SIPMOS transistors instead ofa package integrated bridge driver. Thisapproach supports optimizing the choice of thehigh side and low side switch for very low over-all conduction losses. Capabilities of thesetransistors as regards switching speed, controlmethods, and protection functions will beexplored and discussed, with some recom-mendations for options using external circuitryto optimize the protection functions for specificapplication requirements. This will include abrief overview of new PSPICE simulation mod-els for these transistors, with examples of cir-cuit analysis of auxiliary protective circuits.

Current Sense PROFET

The high side switch used will be one ofthe family of Current Sense PROFET's. Theseare very low RDS[on] high side switches with acurrent sense output from the power transistor.This output pin provides a current output at aratio to the main transistor current, approxi-mately 1/5000 for the BTS650P, which can bemonitored by a system controller, or used totrigger protection circuits locally. In the case ofthe bridge drivers, the PROFET is chosen tohave a higher conduction resistance andhigher thermal impedance, so that the maxi-mum thermal stress is always on the PROFET,which has very comprehensive protection cir-cuits built in. Current Sense PROFET’s havevery low RDS[on] and low thermal impedance,so instead of using a more rugged low sideswitch, it is preferable at this power and cur-rent level to use a low side switch which alsohas at least some basic protection functions.

by Jon Hancock, Infineon Technologies

2 of 13 Using Current Sense PROFETs and Speed TEMPFETs in a High Current H-Bridge Motor Driver


Introducing Speed TEMPFETs

TEMPFET's are thermally protectedSmart SIPMOS transistors, introduced by Sie-mens/Infineon over 10 years ago. A small sen-sor chip is mounted on top of the base powerchip, and connections made from the sensorchip to the gate and source pins of the MOS-FET base chip. The sensor chip functions as ifit was a thermally triggered SCR; when thesensor chip temperature rises above 150°C,the SCR fires, clamping off the gate drive tothe MOSFET and turning off the transistor.Because the sensor chip must be made verysmall to have fast thermal reaction time, theclamp off capability of the SCR like structure islow, so the gate input current must be limited,typically by an input resistor, so that the gatethreshold voltage isn't exceeded in the trig-gered mode. This limitation on the gate inputcurrent also limits the switching speed, typi-cally to the range of 10 kHz or less.

The Speed TEMPFET is a new family ofTEMPFET transistors which have additionalpin connections so that the temperature sen-sor connection is available separately, and canbe connected elsewhere based on thedesigner 's preference. In this way, thedesigner has the choice of connecting the sen-sor pins as previously down with the originalseries of TEMPFETs directly to the gate andsource pin, or of connecting them to some

FIGURE 1: Typical H-Bridge Configuration for Motor drive with DMOS transistors

FIGURE 2: PWM Modulation for Sign Magnitude Operation of Bridge

Chip-on-chip construction of SpeedTEMPFET

Using Current Sense PROFETs and Speed TEMPFETs in a High Current H-Bridge Motor Driver3 of 13

PRODUCT APPLICATIONSother circuitry used to disable gate drive. Inthis way, the limitation of gate drive current canbe overcome, and the SPEED TEMPFET maybe used for higher frequency switching appli-cations.

H-Bridge Modulation Method

Because of the new connection methodo f the p ro tec t ion sensor i n SPEEDTEMPFETs, these transistors can be used forswitching frequencies from a few hundredhertz up to 100's of kilo-hertz. This gives a fastmodulation capability for the low side of thebridge. However, PROFETs, which feature aninternal charge pump and driver circuit, aredesigned for controlled, low EMI switching,and cannot be switched practically above afew hundred Hz. This imposes some limita-tions on the motor control PWM modulationscheme which may be used. The combinationof High side PROFET and low side SPEEDTEMPFET is suited to Sign-Magnitude control(Fig. 2), where the high side switch is used tocontrol direction, and also may be used forbraking, but is not run at the PWM clock fre-quency. In this mode, Synchronous Sign-Mag-nitude control or Locked-Antiphase control arenot practical, because they require fast switch-ing of the high side transistor as well as thelow side transistor.

When using Sign-Magnitude control withPROFETs and TEMPFETs, the high sideswitch is used principally for direction steering,and may also be used for braking. Referring toFig. 1 and 3, if the switch MH1 is turned on,then a PWM signal is applied to the diagonaltransistor ML2 to control the driving torque ofthe motor. Braking may be accomplished byturning on both high side switches, whilereversing direction entails turning on the otherhigh side switch MH2, and applying the PWMtorque control to ML1. Changing modesbetween different directions and braking mustaccount for the switching time of the PROFEThigh side switch, so setup delays of 350 - 500µsec should be planned, as shown in Figure 3.

There are some additional issues regard-ing switching behavior which have to be takeninto account for a bridge driver using PRO-FET's as the upper transistor. Because of atechnology limitation in the driver circuit forPROFETs, the impedance clamping off theinternal gate of the power MOSFET is deter-mined by the value of the polysilicon resistorused to limit turn-on speed. When the outputvoltage of one leg of the bridge (see Fig. 1) ishigh, the gate to drain voltage on that PRO-FET is low, and the internal gate to draincapacitance is high, as is the case for allDMOS transistors. When the transistor in the

MH1

MH2

ML1

ML2

On

Off

On

Off

On

Off

On

Off

"FORWARD" "BRAKING" "REVERSE" "BRAKE TO STOP" OFF

Setup delay Low-sideBraking delay Low-side

Brake to reverse actuate delay

Braking delay Low-side

FIGURE 3: Sign-Magnitude modulation scheme for four phases of H-Bridge used as motor drive


PRODUCT APPLICATIONSlower leg of the bridge turns on, pulling thesource low, the drain to gate capacitanceforms a divider network with the source inputcapacitance and the gate resistor. At higherdv/dt's, it is possible for enough charge to beinjected from the drain to gate to enhance thegate beyond the threshold voltage for conduc-tion, turning on power base chip of the PRO-FET. This will cause a brief current spikethrough the drain to source pins. As the rate ofdv/dt increases, the enhancement voltagegenerated at the gate internally will increase,raising both the level and duration of currentpulse through the PROFET that is nominally inan “off” mode. This affect shows up even in thesimulation model of the BTS650P, and can beseen in the simulation output in Fig. 14.

SIPMOS Simulation Models

“What-If” evaluation of potential circuitconfigurations and components through simu-lation can be a useful part of design processonly if device models with good accuracy andthe required characteristics are available tothe designer. To this end, Infineon has spentconsiderable effort developing componentmodels for both discrete SIPMOS transistorsand Smart SIPMOS transistors which are

strongly based on device physics, and incor-porate a number of characteristics necessaryfor power circuit simulation and evaluation.

The “core” SIPMOS power transistormodel which is now available is an electro-thermal macro model based closely on mathe-matical models of the device physics. Simula-tors such as SPICE, PSPICE, etc. do havesemiconductor models built in, but these aresingle temperature models based on the struc-tures and processes used in small signal inte-grated circuit components. There are manyand substantial differences in structure andelectrical characteristics between the lateralMOSFET transistors used in typical IC applica-tions, and the vertical DMOS power transistorstructures widely used in MOSFET power tran-sistors. Because of this, modeling powerMOSFET transistor requires a dif ferentapproach, combining a number of semicon-ductor model elements with analog behavioralelements with auxiliary equations, in order tocreate a model macro which behaves as thephysical device.

A built-in SPICE Level 3 model is usedfor the core of the device model, but this isaugmented with additional semiconductor and

23

300

⋅⋅= j

ddoRd

TIRV

Drain Resistance

21dXQsat VV ⋅= α

Quasi-Saturation

+−+=

n

digndigdepl V

VVVV 112

Miller capacitance Cdg

[ ])( depldigoxdg VVCdt

dI −⋅=

2

=

ox

dgn C

kVand

with

FIGURE 4: Physics based SIPMOS Macro Model for SPICE and SABER



passive components, plus a several mathe-matical function blocks which implement spe-cific functional areas of power MOSFET. Thebasic block diagram for the fixed temperatureversion of this model, with some of the keyanalog behavioral functions, is shown in Fig-ure 4. Special function blocks are used to cal-cu la te the non- l i nea r ga te to d ra incapacitance, the temperature dependent drainresistance, and the quasi-saturation behaviorof the drain. The operation and derivation ofthese functions has been described previously[1], and won’t be covered in detail here.

The net result of this development effortwas a model structure which provides a good

description of the static and dynamic behaviorof the power MOSFET in it’s primary operatingmodes, within the normal device SOA. This isshown in Figure 4, where comparison is madebetween measured switch response and thesimulated switching behavior using the Level 1model for a 55V BUZ103S SFET transistor.

However, the requirements for modelingmany power conversion applications gobeyond this capability, and require the devel-opment of an electro-thermal power MOSFETmodel. The concept for this type of model isbuilt upon the foundation of the device modeljust described, but also includes elements tocalculate the instantaneous power dissipation

External Heatsink

G

S

dsds IV ⋅

Tj Tc

Tamb

Rd (TJ )

Cth1 Cth2

Rth1 Rth6

Cth6Vth (TJ)

Gfs(TJ)

( )=tPv

FIGURE 5: Electrothermal SIPMOS model using physically based thermal network, with key parameters instantaneously dependent on Tj

FIGURE 4: Physics based Capacitance Model with dynamic ID as a function of VGS results in accurate switching behavior

0

5

10

15

20

25

30

35

10 20 40 50

Id [A]

Vds [V]

2x Vgs [V]

time [usec]



in the transistor, elements representing thetransient thermal impedance of the transistor,and a feedback system to modify key deviceparameters affecting the transfer functionwhich are dependent on the junction tempera-ture (Fig. 5). These parameters include thedrain resistance RD=f(TJ), the gate thresholdvoltage Vth=f(TJ), and the transconductanceGfs=f(TJ). While there are other device param-eters affected by operating temperature, theseare the key parameters affecting the conduct-ing transfer function within the normal deviceSOA. Accounting for this aspect of the MOS-FET’s characteristics makes it possible to pre-dict the circuit behavior even in many overloadconditions, as long as the junction operatingtemperature is within the range where parasiticbipolar currents don’t have an appreciableimpact on the transistor behavior (typically lessthan 250°C).

Figure 6 illustrates this capability compar-ing the measured and simulated behavior for aBUZ100SL 55V transistor in a low impedanceshort circuit test fixture. Note the close trackingof drain current as a function of time betweenthe measurement and the simulation. This isonly possible if both the static transfer functionbased on temperature and the transient ther-mal impedance are accurately modeled.

Bridge Design Example for 12V Application

Next, some design hints for a specificapplication will be reviewed, including issueswhich must be observed for all applications,and optional circuits for additional levels offunctionality or protection. This design exam-ple will address a motor drive for a small DCmotor having a 5-6A current unloaded, and upto 12A current loaded, and a nominal stall cur-rent of 30 - 36A. Selection of the most appro-priate devices for this application depends ona variety of criteria which vary from applicationto application. These include the maximumambient temperature for the electronics mod-ule, the available thermal impedance to ambi-ent, and the assembly and packaging goals forthe electronics.

A general trend in power electronics inrecent years as the available RDS[on] in lowvoltage transistors plummets is the movementaway from generous heatsinking, and a reli-ance on low conduction losses to improve thethermal behavior of power modules. For thisreason it is more common to select the transis-tors based on RDS[on] and thermal issues,rather than conventional MOS current ratings,though the ISO rating, based on a case tem-perature of 85°C instead of the MOS rating of25°C, may still be useful. While a nominal 100-

0

100

200

300

400

500

600

700

-2 0 2 4 6 14 16 18

Level-3 model

Id [A]

10x Vds

measurements

Time [usec]

Short circuitsimulation

FIGURE 6: Measured and simulated short circuit behavior for a BUZ100SL transistor in a low impedance short circuit test fixture


PRODUCT APPLICATIONS125 watt transistor may have the current ratingto handle the described load with margin, if theon-state resistance at maximum junctionresults in 25 watts of power dissipation, theresulting module will neither be small nor runparticularly cool. Working backwards insteadfrom thermal impedance and maximum ambi-ent and junction temperatures, let’s take as agiven that the best Rth(J-A) that the proposedpackaging concept can offer is 16°C/W foreach TO-220 packaged transistor in the motorbridge driver. With a maximum ambient of85°C and a maximum operating junction tem-perature of 150°C, the allowable power dissi-pation per package is found from:

(EQ 1)

This shows that for these conditions, we wantto limit maximum power dissipation per pack-age to 4 watts. In the case of the high sideswitch, switching only occurs when turning onand off, and changing motor direction or brak-ing. Switching losses therefore are negligible,but in addition to MOSFET conduction lossesin the forward mode, conduction losses in thebody diode in the freewheeling mode will needto be considered. These losses, unlike theMOS conduction losses, are not easy to calcu-late because the current level is proportional tothe on time of the PWM switch, but freewheel-ing time is inversely proportional to the on timeof the PWM switch, and the conduction loss isa function of these two plus the non-linear cur-rent dependent diode voltage drop. Becauseof the switching speed limitations of PROFETs,it is not feasible to operate in sign-magnitudesynchronous mode, a mode for which the freewheeling current would be handled by theMOS channel, not the body diode.

What are the worst case conditions forfree-wheeling current losses in the bodydiode? It turns out that the answer is not obvi-ous from looking at the rms voltage and cur-rent characteristic of the motor (Figure 7),because the motor is a very non-linear load.Figures 8 and 9 show switching waveforms

TJmax TAmax–

RθJ A–

----------------------------------- 150° 85°–16°( ) W⁄

-------------------------- 4.0625W= =

Measured & Fitted Motor Transfer Function, IRMS = f(VRMS) y=a(1-exp(-bx))+c(1-exp(-dx))

0 5 10 15VRMS

0

1

2

3

4

5

6

7

IRM

S

Figure 7: Nominal transfer function of example 12V motor, NL conditions

Figure 8: Voltage for switching leg and motor current, Vbb, at 10% duty cycle


Vbb

IOut

VOut

Vbb

VOut

IOut



and the motor current for a light drive (10%duty cycle, Figure 8) and at 20% (Figure 9)and 50% (Figure 10). When near the stall con-dition at 10% duty cycle, back emf from thegenerator effect is at the minimum, and thefreewheeling current time is relatively high,with the characteristic inductive reset. At 20%there is some reduction of the reset time com-pared to the charging time, as some generatoreffects come into play. As the driver duty cycleincreases beyond 25%, approaching 50%, themotor is running at much higher speed, andgenerator effects cause the inductive reset tobe terminated very quickly, in this case in lessthan 100 µsec. Clearly, the condition near stallis the worst case in this example. From theobserved behavior, the approximate loss canbe calculated from:

(EQ 2)

This suggests that the minimum power dissi-pation to expect in this example in the highside switch should be 1.5 to 2 watts, depend-ing entirely on the reverse diode current. UsingEquation 1, and solving for ,

(EQ 3)

This is the starting point for the maximum ther-mal impedance junction to ambient for the highside switch. In this example, staying with a TO-220 packaged device, we’ll use a BTS650P.

A starting point for looking at the low sidetransistor switching and thermal issues mustconsider the off state dv/dt limitation of thePROFET. As previously mentioned, to avoidturn-on of the highside switch, the maximumdv/dt in switching must be limited to a ratewhich avoids injecting charge from the drain togate capacitance so rapidly into the gate tosource capacitance that the internal gatethreshold voltage of the PROFET is exceeded.This maximum rate of dv/dt is roughly 0.7 voltsper microsecond. This places an upper limit onturn-on speed which needs to be taken intoaccount when estimating switching losses.However, this only affects the turn-on drive,and is likely to have a beneficial side effect, inthat the body diode of the PROFET will not besubjected to high peak Irrm. Turn-off switchingcan be set without a specific dv/dt limit. Fortu-nately, the motor inductance limits the rate of

PD

IP

2---- VF D×× 30

2------ 0.9 0.1×× 1.35W= = =

Rθ J A–( )

Rθ J A–( )TjMAX TaMAX–

PD

------------------------------------- 150 85–2

--------------------- 32.5 ° w⁄( )= = =


Vbb

Vout

IOut

Vbb

VOut

IOut

Figure 11: Turn-on and turn-off for normal low duty cycle stalled rotor condition.


PRODUCT APPLICATIONScurrent rise under normal stall conditions atlow duty cycles, so the turn-on condition is rel-atively benign, in spite of peak current almostfive times the normal run current, as is seen inFigure 11. Even at true locked rotor conditionsand 80% duty cycle, voltage reset occurs justbefore the onset of conduction, and driverpower dissipation is not excessive (Figure 12).Locked rotor impedance of the example motoris 60 µH, and about 0.44 ohms.

In the example circuit of Figure 13, drainto gate feedback capacitors are used with acontrolled gate input current to limit the maxi-mum dv/dt at the output nodes of the H-Bridge.The external capacitors are used to help “lin-earize” the switching behavior of the low sideswitch. Vertical DMOS power MOSFET’sinherently have a large variation of drain togate capacitance with varying VDS; it can

range over a 20 to 1 ratio or more. Though theideal driver would be a current source, a resis-tive mode driver is practical because drain

A K

Q1

BTS244Z

D1

1N4148

D51N4750

D7

1N5226

D91N5227

D111N5242

D21N4148

C11n

R3

1.0k

R5

10K

R94.7K

R11 1K

R610K

Q22N2222A

Q3

2N2222A

C3

2.7nF

AK

Q6

BTS244Z

D3

1N4148

D6

1N4750

D81N5226

D101N5227

D121N5242

D4

1N4148

C21n

R4

1.0k

R7

10K

R104.7K

R12

1K

R810K

Q42N2222A

Q5

2N2222A

C4

2.7nF

IN3

IS5

OUT 7

VB

B4

OUT 1

OUT2

OUT6

U1BTS650P

Q72N3904

Q92N3904

D131N4148

D14

1N4148

R173.9K

R110K

R19100K

R134.7K

Q102N3904

D171N5231B

D191N5228

+12V

C547n

R144.7K

IN3

IS5

OUT7

VB

B4

OUT1

OUT2

OUT6

U2BTS650P

Q82N3904

Q11

2N3904

D151N4148

D16

1N4148

R183.9K

R2

10K

R20100K

R15

4.7K

Q122N3904

D181N5231B

D201N5228

C647n

R164.7K

MH2

+12V

ML1 ML2

1 2

J?BP-DUAL

VBATT

Figure 13: Application Circuit, with optional overcurrent/short circuit protection areas shaded

Vbb

IOut

VOut

VDrvr

Figure 12: Locked Rotor Driver, Half-bridge output, and current at D = 80%


PRODUCT APPLICATIONSvoltage switching occurs during the gate pla-teau region when the gate voltage remains rel-atively flat, and the gate charge drives theintegrator function of the gate to drain capaci-tance. During this time the gate voltage of thedriving transistor changes relatively little.Driver charging current is defined by the effec-tive applied driving voltage divided by theseries resistance. The effective driving voltageis the applied drive voltage minus the gate pla-teau voltage for the actual load current. As anexample, if the driver voltage available is 10volts, and an inspection of the transistor’stransfer function in the data sheet shows theeffective plateau voltage for the normal loadcurrent will be about 3.5 volts, and the initialvalue for the gate resistor is 2K, then the drivercurrent is found from

(EQ 4)

For a 14V nominal switching voltage, the totalswitching interval at a maximum dv/dt is 20µsec. The capacitor value desired gate to

drain is calculated based on the total gatedriver charge over the switching interval, so

(EQ 5)

The value of Crss at the rated VDS for thelow side transistor should be subtracted fromthe value for CDrain, to select the value for theexternal resistor. For this example, using theBTS244Z, this value is approximately 500 pF,leaving the nearest standard value for theexternal capacitor at 3.9 nF. With the addi-tional paralleled gate to drain capacitance andthe specified driver, the maximum dv/dt will belimited to a safe value. If this limiting doesn’toccur during the initial voltage fall of the H-Bridge output node, then the charge transfermay turn-on the BTS650P, and shoot throughcurrent will occur on that side of the bridge.This phenomena is illustrated also by the sim-ulation results in Figure 14, because thedevice model is just as susceptible to this phe-

IGDrvrVDrvr VPlat–

RG

------------------------------ 12 3.5–2000

------------------- 3.25mA= = =

CDrainIGDrvr TSwitch( )

VDrain

------------------------------------- 3.25mA 20µs( )14

------------------------------------ 4.64nF= = =

Date/Time run: 08/02/99 14:46:09 Temperature: 27.0

(A) TEMPFET Test LS Switch H-Bridge.dat

50us 60us 80us 100us 120us 140us 150us

Time

V(VGate) V(Q1:C) V(V3:+) V(Isense650) V(VDrain) V(X2:TJ) -I(R5)

80

60

40

20

-0

“Shoot-through” Current from excess dv/dton BTS650P turning on internal MOSFET

Figure 14: Simulation with “Fast” driver showing affect of excessive dv/dt during critical initial fall interval and internal turn-on of BTS650P


PRODUCT APPLICATIONSnomena as the actual transistor. The criticalinterval is in the initial fall time, when Crss is ata minimum. In the simulation example shown,though most of the switching interval is thiscase is below the limit, the critical initial dv/dt istoo high.

Optimizing the low side switch

Other factors to consider for the low sideswitch are the total expected losses, thermalperformance with the intended mounting, andoptionally, optimization for short circuit currentlimiting vs. RDS[on]. With the typical range ofPWM switching frequencies for motor drivesbetween a few hundred Hz up to 20 kHz,switching losses for Speed TEMPFETs will below compared with the conduction losses. Thelatter are variable, depending on the currentprofile, which in turn is dependent on PWMsetting, motor speed, and required torque.

Device selection for SMD mounting isdriven by RDS[on] and total power dissipation,rather than by conventional device current rat-ings, because the standard current ratings arebased upon low external thermal impedancewith high junction temperature, and representthe upper bound for the transistor’s capability.The preferred trend is to minimize the totalpower loss in an SMD environment when pos-sible, or when using minimal external heatsink-ing. In either case, keeping power dissipationin the range of 2-3W, and Rth(J-A) in the rangeof 15 - 30 K/W will provide a compact powermodule with minimal heatsinking require-ments. Using the same conditions defined ear-lier for the high side switch, an Rth(J-A) of 16K/W is assumed, which gives a maximumpower dissipation “budget” of 4 watts.

For this example we assume a worstcase rms current of 10A under load. SpeedTEMPFETs are logic level devices, but theyfurther reduce the RDS[on] with increasing gatedrive. At 4.5 V of gate drive, the BTS244Z hasa maximum RDS[on] at Tj = 25°C of 18 milli-ohms, but with 10V of gate drive this reducesto 13 milli-ohms. Over the full operating range,

this RDS[on] will double at maximum junctiontemperature. With 10V of gate drive, the con-tribution of conduction losses to power dissi-pation at 10A rms with worst case TJ will be2.6 watts, requiring (from Equation 3 above)an Rth(J-A) of 25 K/W if the maximum ambientis 85°C. This fits within the goals above, mak-ing the BTS244Z a good choice.

Protection of the Low Side Switch

A remaining consideration and importantone is optimizing the protection for the SpeedTEMPFET. Because of the mass of the ther-mal sensor chip, there is a finite response timefor the sensor chip to match the base chip tem-perature. Under short circuit conditions withhigh drain to source voltage and high gatedrive, the short circuit current may be so highand the power dissipation so great that junc-tion temperature can exceed a safe operatingvalue before the sensor can respond and trig-ger, resulting in degradation or failure of thebase power chip. This consideration wasaddressed in the short circuit safe operatingarea graph in the TEMPFET data sheet, whichshows the maximum gate drive voltage whichcan be used, while limiting the short circuit cur-rent to a safe value, depending on the maxi-mum voltage applied drain to source. Thedrawback to this is that this usually results in arelatively low gate drive voltage, which raisesRDS[on] and increases power dissipation.

The shaded area in the low side switchdrivers of Fig. 13 shows one method of dealingwith this problem. This is a driver circuit withshort circuit and current limit protection func-tions, which under normal load conditionsallows the full 10 volts of gate drive to be used,optimizing the RDS[on]. However, when thedriver is turned on, and should the drain circuitvoltage rise due to high current flowing drain tosource, the NPN protection transistors Q3 orQ5 will turn on and clamp the gate voltage to alower level. For mild overloads, this results in arelatively slow, gentle response, as seen inFigure 15. With hard short circuits, theresponse is much faster, and prevents the


PRODUCT APPLICATIONSpossibility of exceeding the short circuit SOAof the Speed TEMPFET. Figure 16 shows asimulation schematic for this circuit with theBTS244Z. The additional R/C network con-nected to the lower right-hand part of theBTS244Z is the equivalent circuit model forSMD mounting with 6 cm2 of copper foil. Fig-ure 17 shows the response to a “hard” shortcircuit in what is called Short Circuit Mode 2.This is a short circuit test condition where theshort is applied after the transistor is turned onand in full conduction, with minimum drain tosource voltage, and maximum gate to sourcevoltage. This is the highest possible stressmode for short circuit, and produces the high-est peak short circuit current. This is the casebecause the gate to drain capacitance is at it’shighest, and when the transistor starts to de-saturate from the sudden short, the rise indrain voltage is transferred to the gate, andincreases the gate enhancement voltageunless the gate driver is very low impedance.

VOut

Vbb

VDrvr

IOut

Figure 15: Low side protection circuit response to locked rotor condition

Figure 16: Simulation Example for Short Circuit Mode 2, where the short is applied after the power transistor is turned on and operating at normal curre30

1 2

Q22N2222A/ZTX

R34.7K

1N4148

D4

D1N5227D12

0.004R8

120NH

L1

0.4863sCth2

1.218msCth1

3.336sCth3

37.977sCth4

sRth3

26.11283

sRth2

4.266

sRth1

0.8268

sRth4

7.371

R91MEG

1kR4

D1N5242

D9

D6 D1N4750

ts Tamb

TJ

TC

A K

BTS244ZX2

L2 0.8mH R7 1.4

R_Short 0.01

R210k

Q1

2N2222A/ZTX

R1 1k

+

-12.0VV1

C6 2.7n

U2tClose=400us

+

-

16.0

V2

0.003R5

+

-85

Vamb

+

-V3

1N4148

D3

R6 10K

1nC1

D10D1N5226

0

0

0

0

V

V

V

V

V

V

GATE_DRIVE

VDrain

Sens_Clamp


PRODUCT APPLICATIONSSummary

Low RDS[on] Smart SIPMOS transistorsmake it practical to implement an H-Bridgemotor driver in SMD technology at relativelyhigh current with minimal heatsinking. Byusing sign-magnitude modulation for variablespeed DC motor control, PROFET high sideswitches may be used for the direction steer-i ng and b rak ing con t ro l , and SpeedTEMPFETs for the low side PWM control.

PSPICE and SABER electro-thermal simula-t ion models are available which enabledesigners to test and evaluate the power cir-cuits under a variety of conditions. Analysiscapabilities with these electro-thermal modelsinclude junction temperature rise from thermaleffects due to the power dissipation from over-loads and normal loads, as well as switchingand protective circuit behavior.

Date/Time run: 08/03/99 16:10:03

* E:\Msim_8\Projects\PROFET-TEMPFET Bridge\TEMPFET Test LS Switch W Short2.sch

Temperature: 27.0

(A) TEMPFET Test LS Switch W Short2.dat

150us 200us 250us 300us 350us 400us 450us

Time

V(R1:1) V(X2:TJ) V(C1:2) V(R_Short:1) V(VDrain) V(GATE_DRIVE) -I(R5)

200

150

100

50

0

Current Pulse duringType 2 short circuit

Figure 17: Simulation Example for Short Circuit Mode 2, where the short is applied after the power transistor is turned on and operating at normal current; SC current pulse is limited to 10 µsec duration

Documents

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