Update Ic50.46.006 Readme

5/21/2018 Update Ic50.46.006 Readme

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=======================================================Softload Installation

Installing the IC5141 USR6 release from the physical mediamust be done using Softload, not Installscape.

Installing the IC5141 USR6 release from the Cadence download

site is done with Installscape.

========================================================FLEXlm v10.1 (or higher) license server must be used with theIC 5141 USR6 release. FLEXlm v10.10 is provided in thisrelease and all products in this release are integrated with it.Using FLEXlm v10.1 (or higher) is part of Cadence's commitment toprovide license management that is flexible, secure, anduncomplicated.For more information on Cadence's Next Generation licensing,please go tohttp://sourcelink.cadence.com/docs/files/ILS/Install_Lib.html

or contact your Cadence representative.The FLEXlm v10.1 (or higher) license server is backward compatiblewith older licenses.

=============================================================

The following list includes CCRs filed on behalf of Customers thathave been fixed and are integrated in the IC 5141 USR6 release.

CCRNumber Title--------------------------------------------------------------

3626 UNIX-like history command is needed for OCEAN script4380 Enhance Make Cell so Origin can be specified4533 Need a function to find the intersection of two waveforms4874 DM text view editing5069 The dB20 equivalent 20*log10 does not work in Calculator5151 figTrigger for change layer is meaningless in extracted view6559 Design lib not in Interface Elements parameter search order7108 Need function that filters selection before move or stretch7283 AEncv can not handle ~/.vlogifrc.7689 Spectre sweeps must update entire inline subckt7958 Verilog netlister instance based modelName property8155 Capacity problem with buses and iterated instances

8332 Composer search & replace checks out all library instances8600 pss step sweep parameter in Spectre direct Ocean is broken8608 dubiousData needs better treatment of path end segment12986 Marknet highlights through diffusion making it unusable13318 Need to be able to plot UCF values vs. time18048 Need an Enhancement for interleaved pin placement for buses18080 AWD needs ability to set resultsDir for Ocean calc exprs18541 Need way to change default ground net18961 Put hot keys next to picks on pulldown menus20875 Need to support both LSB and MSB type of busses21177 Let users define their own bindkeys21429 Netlister must check netType of supply1/0 for duplicates23582 Implementation of ivLVS in foreground job

23980 Provide copy, delete for testfixture.verilog in NC-Verilog25236 geCycleSelectNext does not work on text labels26191 Variables sim*Prefix are hardcoded in CDLOUT


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27312 HED log from DFII should follow CDS_LOG_PATH27603 Cloning does not check/recognize parallel/series connection31000 Composer check & save does not flag V31399 Need InhConn info from DFII signal object/supported function32195 VHDL ToolBox property to prevent component declaration32828 Need auto pin placement on instances using VCP33615 Support NC-Verilog Executable field to Simulation Setup.

33831 leqp can not handle error during NC netlisting33957 Pcell Stretch Point off cursor after pan, zoom34713 Verilog In generates schematic in off-grid.36068 Implement automatic update of viewInfo in libmanager36449 Make Artist work the same way in DP mode and in Local mode37093 Add an option to ignore portOrder mismatch41767 HNL with inherited connections creates unconnected globals41774 VerilogIn should support Verilog200142402 Add x/y zoom/lock feature for cursors & markers42927 Add vss_inherit and vdd_inherit components to analogLib42945 Des vars annotate as wave after parametric analysis plot50438 Need LSF support for AMS Designer

53638 cdlout : Allow Cap to pass width, length,area to the netlist54302 Write DP logfiles to psf directory rather than /tmp56301 Enhance DP to allow LSF/SGE online command56663 rodAssignHandleToParameter problem59992 To have Transfer Functions in Verilog-A model59995 Want to declare all single bit wires in Verilog netlist60040 modelFile should not be in Corner-generated Ocean script61917 DEFIN seems to create collinear points in paths62276 JobId error when running in Distributed Processing Mode63876 DFII needs to deal with the greater than 100k net name issue65400 ocnPrint hangs on large PSF data67219 Warning: Cannot convert string /usr/include/X11/bitmaps/sta67633 env. variable for composer schematic digits for annotation

69486 isource does not give terminal current due to wrong CDF70358 Stream file is huge70577 Need lxUseCell to work on different view types70737 Random number generation functs. fail in iteration functs.71113 Need a property to ignore shapes within an instance.71978 Select area option gives: WARNING: Component X not found72916 Enhancement to Component Types form73115 Edit component display does not work with iterated inst74213 Option to disable weak connect violation markers75112 Maintain nodesets/ics/saves when config changes77088 Explicit netlist option does not support bus bit declaration86919 LVS Error Display form cuts the top of font for message

86928 ADI/AMD need lxUseLibList type of env var (not Property)95814 Chop command should keep path object type96163 Customers want to set the edit properties form size.96687 switched cap filter ckt missing from rfExamples96892 Loading schPlotOptions template fails without papersize spec98002 HED ignores library list for hierarchical views99218 Problem while merging mpp, data lost100451 Marker coordinates change after zoom103297 ahdlUpdateViewInfo should return nil if it fails104286 VerilogIn global supply field defaults to VDD107469 PRFlatten must provide a possibility to short terminals109151 cannot do Components And Nets Comm. when decreasing mfactor109254 Want bundle nets to be listed vertically on Schematic

109265 Add Smart Justification to add wire label form109420 MSPS should support regular devices for a probing109885 Modifying pins should auto update Symbol/Schematic


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109895 IssuePI14 open symbol for edit of a schematic at same level109910 Using all selected in E.O.P form will change all parameters110774 The gdloss parameter in mtline gives the incorrect result112026 Specifying Viewer when opening text file in read-only mode112613 Implement SKILL and C APIs to create mosaic with PCELL.114190 Marker label incomplete if text added after coordinates115021 .cdsenv deleteJob environment variable not working

115276 Corrupt .adpState File Causing putprop Errors in ADE115287 GUI needed for measuring large signal s-params115919 Preview needs a way to create routing blockages115923 Pin Optimization should respect routing blockages116468 Block place should take into account routing blockages116508 Spectre S11 does not match other simulator when using Bsim4116581 support verilog-a module for hspiceD netlisting117416 cannot plot gain & stability circles after sp parametric run118049 Command Line Interface for CDB LEFDEF translator118194 Not able to generate netlist in hspiceD but can in hspiceS118799 Axis labels problem after font size changed123383 WIA Strip chart mode needs improvement for Family plot

123435 Support more options from the amsdesigner command line123459 Ask filename if data is too big and truncated to 1900 points123511 CDL Out GUI - Run In Background - enable for auCdl:123523 Enhance CDL IN to support more than one reference library124410 PIPO GUI enhancement needed for mapping text bus notations124615 Document netNameMode property125240 Cannot expand a bus that is loaded from a saved graph file125244 IP3 is not visible when located outside of PSS sweep range125950 DP email notifier not working for single jobs125998 Allow user control over ADE available simulator list127628 Calculator sample function is unacceptably slow128059 Wavescan calculator functions overshoot and convolve.128403 rodCreatePath does not apply begin/endSegOffset to subRect

128456 Current and power measurements in MDL result in NaN129381 Missing continuation charac gives SpectreMDL internal error129546 Spectre result differs between IC446 and IC5033.129576 gec3SkipLefTECH reduces resolution when exporting LEF130399 support of the derivative layer for DRD130405 Support of LOAD/DUMP function to the file for DRD130837 Move Strip Chart Visible Rows Under Graph Attributes132317 Would like a way to reset Corners UI132906 Update Components and Nets does not delete extra pins133370 asimenv.loadstate modelSetup=nil screws up Optim. load state134017 Place .simrc in different paths, directories134231 enableComponentUpdate is not effective for pcell parameter.

134411 amsdesigner should error out if ncvlog fails135069 VCP should recognize user define cell boundary135253 Enhance CDL IN to support M property for all primitive dev:135742 Cannot select command menu in LVS Analysis Job Monitor Form136992 hspiceD doesn't output r value when l and w values are set137347 How can we use a defaultVia during finish route in WE138863 Control process param data from being saved to mcdata file138873 UCN moves instances placed outside pr with no overlap139282 Give better error about conn2sch_other_options file for CDL139348 Clone command cannot handle Permutation correctly139419 spectremdl has problem with nodeset139703 problem creating netlist using extracted view with bus pins140257 Questionable behavior of techSetPrecision

140372 Are nets probed using layout window or Probe Option Window?140931 BSIM421 Spectre result differs from third party simulators140980 auCDL requested to output multiple *.PININFO lines


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141942 SpectreMDL gives wrong error message with cross function142019 Spectremdl gives Division By Zero warning message.142246 CDLin error/bug for long cell names142621 voMemory functions cannot link in itkDB c++ programs143277 ruleContactDevice needs to be fixed to accept variables143604 Problem with small slanting line shape display143718 V(out)/0 does not give correct error in calculator

143947 Virt_XL: Create Path will panic when infix is switched on144533 auCdl slowdown -- 5 min in IC446 vs 5 hours in IC5033144548 Display problem with Magnification function144920 rename simVerilogSupportDuplicatePorts145749 inherited connection pins and create symbol from schematic145784 restore waveform window when appending additional signals145950 Switch View List should change when switching simulators146280 output log is not updated when two parametric sweeps are run146300 dbGetTrueOverlaps function returns incorrect results on OA147734 Pcell instantiation by multi-users gives error in AFS148015 stability analysis probe incorrect on cmdmprobe w/ hierarchy148109 VCR CCAR options on export to router need updating

148205 Relative placement of cloned instances148225 DD-properties are always opened for edit in OA.148299 Corrupt data with too many MonteCarlo expressions148495 mdl deriv function gives wrong result149511 Bsim4 incorrect gate current in 5033149520 Add categories to Functional Library149715 SKILL procedure to create Diagonal wires returns nil149892 PSS/Pnoise hangs on a particular circuit150080 VXL: Multiple abutment is broken on IC5141150275 cdsdoc for CM needs updating for inhConn150432 aaSP performance is poor when using many ports150435 VAVO EM Signal Analysis does not include all nets in design150508 bsource voltage form not working

150833 portImplementation differ in highest schema and lower schema151291 Assertion failed in file shoot.c during PSS151595 mutual inductor does not output mutual inductance151642 Discontinue namemapping in ADE netlisting for Spectre direct152350 Move using Apply XY in move form gives incorrect results.152510 Wavescan displays new and old label after Monte Carlo152515 Wavescan plots labels off-sheet in histogram plot152765 Using SKILL to copy a cell causes icfb to crash152797 geTransformUserPoint(l_point l_list) explanation is wrong152830 UltraSim_IF needs to update to meet HED changes152883 segSnapMode should be documented in Schematic Editor manual152957 Phase noise should plot correctly with psfbinf data

152967 Finish routing on WE makes an illegal path153597 Lint message and severity for ivExtract is incorrect153791 Spectre BHT model wrong in DC sweep154002 pipo GUI should support file browser for gds & tech file154300 Output is incorrect for instances whose pins are ignored154305 spectreMDL finds wrong solution in search154526 gm based flicker noise is not right in spmos154585 VXL cloning problem154615 Don't netlist the Default value of the net Expression in OSS154837 Direction of IO pin should be translated to signal_direction154952 Failed binary search runs must still produce measure output154966 Is there a way to netlist GND in hspiceD?154991 Need to support external parameters in bsource udf

154994 Spectre should support user defined functions in subcircuits155133 OA Dump techfile operation gives a syntax error155262 STI simulation problem for bsim3v3 in Spectre 5033


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155311 hspiceD does not work with aelPushSignifDigits function155358 WARNING Ignoring ANTENNAMODEL OXIDE3 rule not supported155409 auCDL creates different netlist for different versions155453 rodCreatePath crashes the tool155486 SFE map on level 57 model is wrong155560 Ability to switch off netlisting for tasks in DP jobs155742 VXL hangs with long net name and sfactor > 1

155816 Frequency sweep on form should specify input or output155907 cdb2oa segmentation fault156060 cdsenv controls size of circle around node156388 Spectre: Convergence problem with Hicum on Op analysis156494 Need to implement a minimum limit for me parameter156756 The addition of Use Target Pin Narrow/Wide156789 Modify behavior of create pin form if adding net expression156836 improve placement of net expression text for pins156853 VXL gets rounded off parameter values during GFS157021 AMS Netlister Segmentation Fault157052 Missing skipdc value sigrampup in PSS options form?157204 Spectre Error while using VBIC model in IC5033

157224 IC does not update next simulation with hspiceD157331 Options to modify DATABASE MICRONS and USEMINSPACING157415 Add ADE ENV switch on Spectre lic suspense/resume (MMSIM60)157521 m-factor with tran chning/folding creates improper devices157638 Document tsgPinGraphicMasters and Pin Attribute form158000 List coupled cap totals between selected net and all others158067 Library Path Editor not responding to Ctrl+Shift+D command158074 VXL Area Estimator takes Cell Boundary into consideration.158297 Error of ictFormCreate with Preview158404 Customizing layoutXL.menus breaks the tool158599 MPP copy drops subparts158678 Make rundir not strictly dependent upon a config view158719 strange warning message on imax in vbic model

158771 Getting wrong answer with new parameter in altergroup159144 Spectre simulation fail. core dump.159178 pslNewTextSemantic - truncates first 2 chars of string data159284 SpectreRF Phase Noise inconsistent with silicon159351 can not use Create Wire command159478 Edit object property form should adjust scroll bar159638 Abstract verify problem if techfile edgeCap values are small159672 Wrong Inherited Connection in VXL 5.0.33159684 Wavescan zoom after stripping and dragging gives wrong data159697 Document layers used for schematic160094 VCP should use PR boundary to count unplaced components161092 Stopping Parametric Analysis sim. deletes sweep data dirs

161196 Direct Plot form in ADE shows wrong units for noise signals161213 Noise data has huge gain at 398.1MHz161262 Creating a wire in a schematic gives error161274 Direct plot form does not work after running PSS analysis161456 Need way to add instParameters in hspiceD161854 cdb2oa generates WARNING 702(size > 800Mb) when CV is 86Mb162146 module with trinary operator fails in 5.1.41 not in 5.0.33162320 SpectreRF UI PSS enhancement related to PCR 703954162578 Device Correspondence should work across libraries162642 error 33 when running distributed processing162646 Need X and Y enclosure on implants and wells for 90nm162739 VCP is very slow when preplaced cells are not locked162749 rodAlign constraint is nil right after opening the design

162827 Error message on wlod and llodvth in BSIM4.30162862 Enhance AMS netlisting to use effective CDF162904 Equation for threshold voltage in psitft is wrong


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163005 CDL netlist has too many pins163227 Cannot save snapshot in VSdE doc dir by default163236 hspiceD maps instance name when it is same as cell name163243 Virtuoso Multimode misses Substrate_Coupling_Analysis163461 strange results from VBIC model163501 Verilog netlist has PORT/NET name conflict with InhConn163865 Zoom In crashes Layout Editor

163905 DP script for version compatibility not working in 5141164234 simulation with hicum gives junk/dummy1 for op point164420 lefin of macro cells requires write access to techfile164542 Need warning when Lg. Coord. is greater than 31b164697 VCE crashes when a selection set is moved164875 message option for comp/elab and sim should be on by default164925 SKILL Lint rule cleanup (schematic, schView)164926 SKILL Lint rule cleanup (seCore)164943 auCdl - automatic netlist inclusion in CDL netlist165011 Ultrasim in ADE does not work if hspiceD context is missing165100 Slow tool performance due to FeatureExists checks.165245 Datatypes undefined in itkRod.h in IC5141

165262 amsDirect core dumps.165285 TEMPER is a reserved parameter name for Hspice165299 Need to support bsource udf inside subckt scope165605 Trace Markers movement is not acceptable in wavescan165614 Delta Cursor does not maintain position when you zoom in/out165821 Problem to descend into instances copied from instance name165827 array overflow crash165833 Description of dbGetq is incomplete in cdsdoc165997 Hspice G model simulation seems not right in 5141166037 Differences between AHDL and verilogA modul - opamp166083 DFT output display problem in wavescan166097 libPathEditor saving library info in irrelevant location166128 Edit-in-place pop-up not appearing in USR2 or USR3

166185 OA : Copying a functional view does not copy netlist.oa file166239 Need a .simrc variable to preserve buses for CDLout netlist166271 VXL extract level 0 does not recognize symbolic inst pins166281 Wire Editor does not route from other points166501 lefout does not output layers with number > 127166620 Cannot import amsdirect after 60 seconds172847 Layout crashing in IC5.0.33172866 rodCreatePolygon() size option gives a warning message172932 Explain warning message: No ddSvcLibEntry172934 Need a way to tell VCP which view to use for placement172945 assign syntax is wrong when patch is connected to global net172960 strobeperiod causes arithmetic exception in pss

173085 csfe option makes Spectre dump core173092 cdfDumpAll function should edit file from correct location173470 dbFix does not repair problem of continuous error messages173486 Incorrect Verilog netlist.173554 Print S-parameters enabled for PSP in ADE but not supported173561 Spectre bsource problem with hspice resistor equation173571 Remove un-used inherited ports from the netlist173583 Fix PCR 584602 in IC5033173683 amsdirect does not correctly netlist pPar in sqrt function173693 Wavescan creates 0 byte eps file for hardcopy in Ocean174021 Techfile Load error in OA174044 Need clamping of parameters during MVO search174261 Cell Substitution is not working using loCellSubstitutionMap

174315 vcvs comp does not restrict to min voltage if delta is set174574 Sweep simulation with alter statement gives internal error174590 Spectre parser csfe gives internal error for bsource


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174700 bsource simulates slower in 5141174739 Provide public API to control the size/location of WaveScan174838 Segmentation fault running corners with useAltergroup175014 Bug in inductor.c for noise computation175069 simulator lang = Spectre added to .includedModels file175185 Internal Error during transient analysis175433 Problem with Make Cell function after using Attach function

175486 Time domain noise results are based on wrong timepoint175747 terminal net name is lost when pin is swapped on VCAR175780 Spectre EKV AC drain current issue with nqs=1 flag175794 Enhance Plot Histogram form of Artist MC175843 Create VerilogA From Symbol reverses Bus order: 3:0 to 0:3175876 Binned model definitions should persist through alter175894 Mosaic cells are displayed empty175924 Wire model parameters not supported in Spectre175943 Increase on selected nodes and currents for ADE netlister175948 schVIC requires the design to open in Edit mode175952 SFE does not support scoped models176041 Compilation failure in verilogA module, simulation runs fine

176183 Import from router gives error *Error* SIGFPE caught:176550 Problem with Hierarchy->Refresh176559 Limit on selected nodes/currents for ADE Usim netlister176599 ITK func rodDeleteMPPChopHoles does not work176615 Add documentation for defining netSet type with CDF177150 UCN gives Warning:No template for pin XX , pin not created177259 DEF translator does not handle rectangles and polygons177298 Spectre errors out when using mtline in montecarlo sim177677 Tech File Checker not working on OA databases177784 Spectre gives warning during netlisting177904 Techfile Dump creates wrong lxRules section of techfile178163 Long lines truncated and lines skipped in dofile178262 The Common button of Edit Instance Properties dose not work.

178383 Off-grid MPP is created when instance bBox is off grid178388 Create Guard Ring causes spacing violations between contacts178403 Want to create a Default Prefix For Instances using DB API178550 leHiSearch() flags all instances w/same leading digit178575 EDIF200 default of replaceBundleWithArray taking as FALSE178627 Failed binary search should not return a warning178633 Wavescan aborts while opening results on HPUX 11.0178671 Aptivia cannot obtain Artist simulation environment license178786 EDIFout200 Stop Cell Expansion file allows spaces, not TABs179146 noise_table gives wrong output at low frequency179291 5.1.41 cdb2oa ERROR (CDBOA-401):Cannot open OpenAccess file.179631 Finger width cannot set in Qcell Install Form

179659 Syntax error in Modelwriter sdomain model179693 Stream-in importing geometries in 4x magnified179713 Corners labels missing after number 117179796 LEF import creates wrong enclosure on tech file180050 Check&Save erases information in CMX net-based section180213 unable to import ring/donut shape polygon180374 Getting internal error with large paramset array180391 Need to include 64 bit libraries with oasis kits180398 5033USR3 Crash on Update Components and nets180492 5033usr3 Autospace is broken - creates short181140 Need to place design with uneven utilizations.181154 Request to make pfile() function a public function181402 csfe throws internal error while handling alter statement

181696 cdfGetInstCDF() with dbSetIgnoreLib(TRUE) gives warning181762 Backspace should work as Delete on selected objects181824 Monte Carlo simulation seg faults on Linux.


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182034 vias within mosaics are in wrong location182051 Default cursor locks at X-axis halfway point182184 difference in results between MICA and Spectre at temp_105182444 No EOF delimiter in the modelsetup file in .artiststates DIR182445 Spectre new parser errors out on IBM platform182467 Spectre +csfe-new front end-fails on continuation character182499 useMfactorToIterateInstances needs to be documented

182554 Problem with Magnification in PIPO-StreamOut182659 problem with dbOpenCellViewByType() in IC5.1.41182815 Duplicate Instance names in Schematic182865 Missing top inherited connections with simGlobals set182978 Alias mulu0 with mulmu0 for bsim3v3 and bsim4183009 Update components and nets ignores changed property183145 Create-Wire does not add via to mask-purpose routing layer183282 lmgrDefineInits breaks ddGetObj due to libInit trigger183480 Dialog box is needed for dbSave failure when disk is full183536 Can't update source schematic when VXL opens from schematic183643 PCRID=749184: Inherited Connection doc has error on page 32183646 PCRID=749187: Inherited Connection doc has error on page 43

183752 Enhancement request about hspiceD netlist parameter control.184060 Incorrect fundamental frequency in 5033USR3184147 Effective Cell CDF not showing up correctly184205 nqsmod does not give correct answer after 5033USR1184347 How does MSPS calculate parasitic res val for backannotation184408 VCE crashes when stretching a route with marker selected184409 analogLib/mind cdsSpice netlist is different in 446 & 5141184493 Annotate resistance not working in distributed mode184663 Plotting using Template Files not working184715 Warning msg when running SpectreVerilog using av_extracted185069 Need wave button to override Select mode185106 autoSave code saves when the cv is a pcell sub-master185234 Cursor Offset field in trace attributes form has no effect

185410 UCN moves instance out of chain if chaining is not turned ON185464 Edit Properties for iterated instances causing problems185502 Annotate DC Node voltages is very, very slow in 5141185503 Spectre, during Monte Carlo, cannot communicate with artil185510 Wavescan Doc needs to describe differences btw MDL and SKILL185633 Plotting through the CIW always results in X trace symbols185692 Spectre sp analysis produce different NF result 446 and 5141185803 Spectre csfe errors out when function used in if statement186047 Content of Corners directory disappears after simulation186071 Enhance CDL IN to support substrate term for RES instances:186398 Virtuoso XL crashes using Netlist Driven Layout186453 Need information about how hnlReNetlistAll works

186544 incorrect result with memory186545 cannot change expression of memory186698 Problem with property mapping file in Xstream186921 VXL Template File Needs to be loaded once.187127 Cannot translate symbolic vias with DbIdPlusTime mode.187145 Enhance auto-refreshed lib data completely after pipo-in187158 After chop, stretch and reshape CIW displays the final area187166 hspiceD & hspiceS should have same subckt netlist line wrap187189 auCDL programmable node WARNING Message187388 envSetVal operations do not work in Wavescan187527 Spectre uses very small step size on simple circuit187565 split_vias creates single contacts in some cases187807 Invoking VXL causes crash

187921 Lock remains on layout after closing layout.187976 Option needed when stretch does not modify some shapes188002 want to keep selection condition after executing the flatten


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188087 Probing needed in VCE188160 Crosstalk check does not work in Wire Editor188284 Log file should display warning message for duplicate cell188287 PIPO fails in linux because of EXT2_MAX_LINK is 32000.188309 Spectre bsource resistor equation problem 5.1.41 OLD FE188367 Problem when doing a migration from cdb to oa188461 cdb2oa fails to recognize it is running 64bit

188724 dbCopySingleProp causes crash when copying cdf properties188741 Failed measurement returns a zero instead of NaN in 5141ISR188876 IC5141: Want LSW inst and pin selection controls as IC50188980 Wavescan runs out of memory for parametric results189027 cdfParseFloatString() behaves differently 5033/5141189206 Update Components and Nets is too slow189219 Rounding problem with via size on one port189708 Handle blank scale/scalem simOption params in control file189801 Stretch in simple route mode is broken189839 SpectreRF fails to find swap file under LSF189881 Need analog to digital capability in Wavescan190044 Incorrect entries in schGenParamFile not reported

190171 ICOA crash during EIP and stretch polygon.190202 Support YvsY for waveforms from different datasets.190217 Distorted waveform in the Type=VCCAP of the VCCS source190257 Port-range is not outputted for split bus port of inout.190360 DEFOUT escaping the instance names in components section190573 Questions about Spectre multithread runtime190633 Export DEF from DFII drops _StrongGroup_3 metal data190684 Small pulses with analog signal when running SpectreVerilog190872 Wavescan hangs when printing.190997 VerilogIn Internal memory error on Linux191130 Wavescan does not plot digital unknown value as latticed191133 OCEAN hangs in IC5141191166 schnetexprbuildevalnamesform enhancement

191260 ADE Spectre/usim netlisting takes long time in amap191928 auCdlCDFPinCntrl=t has no effect on inherited connections192241 Display Error : BadDrawable (invalid Pixmap paramater ).192261 Support of dbCreateXformPCell function on CDB database192568 Placer partitioning form forgets sort setting192614 / in power/ground netnames for reporting decoupled192753 Monte carlo simulation fails with Insufficient memory error192824 What percent of cpu is used during ultrasim run?192849 Error message in VXL for QCells (QCell Eval Fail)192974 NULL connection for port was found during netlisting193530 cdb2oa error message on .SYNC directory193636 Plotting transient operating points fails with infotimes

193817 Improve the MC Load/Save State functionality193829 Spectre simulation with scccs gives arithmetic exception194021 Get no connectivity on via layer which is an lxextract layer194022 PUBLIC PI: asiGetCommandLineOption write protected194045 Function hnlSetDef causes segmentation fault194239 .wsenv setting for printer does not work.194289 Pnoise NF inconsistent with silicon194439 Shadow mode not working in newer releases194447 Problem with Direct Plot Noise Figure for PNOISE/QPNOISE194580 copyGraphics does not work194647 Need to change violation limit twice to enable it194731 Confusing message about a non-hierarchical property194836 Need to create annotation label with calculator expression

195139 hnlMapInstName hangs during netlisting195148 Filler cells are not inserted correctly.195158 Load ipc context into dbAccess compile


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195424 QCell - Issue with Fold threshold units195535 aelPushSignifDigits needs higher limit for better precision195648 Getting QCells eval errors when using pPar195757 global_spine(fish bone style) option problem in VCAR195846 Zoom and probed nets display has changed196055 Problem with optimized routing with pre-routing patterns196139 Removing unused run dir causes amsdesigner to fail

196357 Update Layout Parameters causes system to hang196359 VCAR crashes on check command196493 shortEnhContactForm setting in cdsenv is not used196703 Internal error occurs when running Spectre with multithread.196734 Remove OCEAN dependency of reading netlist/netlist file196888 PIPO: Convert Simple Mosaic to array wording is incorrect196964 BSIM430 parameter vtl error197391 Fault when moving Keepout by Route Mode197742 Move command for wire_polygon moves Component together197867 Add blink argument to drMakeColor SKILL function198013 Support 64-bit awflib.a, needed for OASIS psf writing198183 Mixer in rfLib does not do ip2 clipping properly

198446 qcell eval failed with VXL if no mfgGridResolution198603 Copy from existing rundir not working199091 techLayerProperties lost in translation to OA199191 Violation markers not created for incorrectly abutted pcells199239 LSW doesn't default to the layer when creating a path199442 PCRID=766400: ICOA5141 doesn't read in overlap layer correctly from lef199454 BLOCKAGE section missing in DEF file after DEF-OUT.199558 Save As Verilog should be able to use data in tmp dir199569 pathCL not working correctly199607 lefin should create pin with purpose pin not drawing199640 Preserve the case in the hspiceD netlist199755 ldtrLefWrite returns nil after successfully creating LEF file199891 Line 758 of allFunc.scs needs a comment character

199921 The Fill Color Editor -- Example Colors form does not work200290 The abutment of std cell is disregarded by VCP.200308 Errors in itkDB documentation - in tech file chapter200712 Fail to streamin a GDS file in OA version.200876 Mind parameters should not be mapped200951 Questions about Qcell Auto Guardring.201607 Spectre transient Internal Error201781 VLE crash: when moving instances with maintainConnection=t201978 Separate Change Layer options for paths and other shapes202096 Warning message of Junction current exceeds imax202232 Extracted view fails when it exceeds 2G202374 VXL freezes when initIOPinLayer is set incorrectly (linux)

202491 Enhance the snap mode on the Create Wire form202495 Querying cdsVia property in VXL does not work.202677 Need In-context terminal probing on extracted views202832 Cannot push a segment from upper side or right side.202966 Need PIPO options or cdsenv to choose Up Bottom approach203030 conn2sch core dumps for large netlist cellviews203157 DracInter 5.10.41_USR1.7.43 and later ISR can not find net203214 Problem with open schematic after gen from source.203428 Gen From Source deletes User defined Cell Properties203434 hspiceD does not netlist mind device correctly203499 DEF-OUT does not map the hierarchy delimiter in net names.203558 Extractor does not delete empty nets203647 Need ability to select the layer VCP uses

203664 DEF out does not reflect the symbolic pin placement.203713 Cancel button in the cross probing GUI does not work203734 Scale command causing grid snap spacing problems


11/38

203772 Documentation change for new enhacements204035 Memory leak in Wavescan Java process204275 Mosaic via origin needs to be shifted during import204310 Connectivity broken on elliptical/ellipse contacts.204323 Place pins as in schematic broken with explicit Inh. Conns.204483 Local value of CDF is lost when pin inst master is changed.204529 Enhance the Spacings field in post-selected align function.

204635 Wire Editor resizes symbolic contacts.204637 Update res element in analogLib204639 MEASOUT option for HspiceD causes no change in simulation204742 CIW->Import Stream fails for long net names >128 characters204882 Wavescan cannot read parametric data from simulator205151 Backport support of basic config features in IC5141205280 Preview - Pin optimization requires license 14020205666 Spectre aborts when more than 32 files are opened205733 rodCreatePolygon reaches max value of pts parameter205782 cdsSpice netlisting error use hierarchical mode205892 CDlout netlisting behaves differently in IC 5.0205915 DEFout hangs when referenced objects found (for few objects)

206287 DFII fails with enterpoints function on PCell Parameter206289 LEFOut: gec3DBUPerUU precision multiplication206663 Monitor-Probe-Explain for CM works for top level only207174 Need to edit wire name in Edit Object Property form207191 Request to have Cross Hair marker option in Composer207445 IC5.33 crash after a copy (VLE)207484 Enable and disable modelFiles via SKILL in IC5141207498 deGetProbeContext causes icfb to crash207711 lqtimeout in SPECTRE_DEFAULTS207716 icfb crashes when using cdfGetBaseCellCDF(nil)207802 geAddNetProbe() doesn't highlight properly in lower hierarchy208249 Snapping and measurements in wavescan are poor208578 Spectre core dump when only the 32bits solaris is installed

208706 Provide a calculator icon in Wavescan waveform window208870 Stretch in WE ignores the grid when checking is Off209068 Unable to plot pnoise when the osc node is in hierarchy.209069 IC5141 USR1 layout crashes209240 Var schematic broadcast - dramatically impacts VLE commands209259 Support rdc and rsc as the model parameter209291 Instances in copied cell have wrong BBox209421 Abutting Qcells with different widths causes crash209463 Spectre Segmentation fault when using ibis_buffer209594 Different SpectreRF results209627 Compiling aborted because of oversized SKILL file209998 Evaluated CDF parameter displayed in suffix notation

210307 Violation display for device checking failed210338 Unable to resize the CIW window to a new location in GNOME210355 Map file syntax for useCell no longer supports cellName only210641 techStringToPurpose missing from itkTech.h210665 Request for port order: Out In In/Out in Verilog netlisting210830 Show Ignore Parameters documentation is incorrect210972 Spectre netlisting seg faults when invoked twice210987 dbRefreshCellView crash211099 Create Guard Ring command creates DRC errors211146 _mspsProbeInstanceMenuItem error when Parasitics is started211201 cdfGetCellCDF() failure causes prop editor to crash211273 selectResult with corners gives error with v function211307 Veriloga parser fails when inf is included in the range

211553 dbCreateXformPCell is not able to xform text display211651 iccTranslator.ImportEditor importView variable does not work211755 simInfo termOrder should not be automatically generated


12/38

211865 A Pcell parameter cannot be updated211947 Document optParamExprList in CDF User Guide211996 autoTrimPins=nil produces keepout identical to pin212203 Connectivity is not going through Vias212247 MPP Shape error when dbCreateXformPCell is used212501 Set transient step annotation by default for AMS ADE.212623 Suffix of verilogFile other than .v causes error

212648 Schematic check misses net name conflict at pin-pin connection212649 hiUndo failed checksum verify before Undo212734 Provide ability to display multi occurrence output as history212911 Preview: Performance issue with hilighting instances212995 Problem with edit in place in IC5141 base and ISR213282 Explain PDK213285 Do not use - MOS Diff AP on -213294 Inconsistent results with newer versions of SpectreRF213377 Problem with netsets when names contain dots213573 Get JAVA error when invoking design prep with AMSD213641 schPlot does not work on other than toplevel213705 Model breaks with new parser on type=-1

213867 Change in functionality in pick from schematic214045 Problem with pins in port list being defined as wires214180 Escaped names cannot be plotted from MDL Calculator214222 vcar does not consider an offset of the via.214233 Need ability to individually weakly-connect multiple pins214285 Edit verilogams checks-out/in cell prop.xx mult. times214324 Pcell loses abutment state w/ lxLocalAbutment t214384 SpectreVerilog netlists port order incorrect214899 Segmentation Fault occurs with GenFromSource command214990 Sub Rectangles disappear when chopping a MPP215277 Cannot use a use_via rule in the WE.215347 Spectre simulation runtime has been multiplied by 4215392 Using integers in parameter expressions: Spectre vs AMS

215417 Have SPP work with the model files215536 Constant value of Verilog prop is enclosed with quotation.215647 Pin Opt moves soft-pins outside to prBoundary215787 Parasitic terminal-to-terminal iterative inst probing error215799 Wrong value for Parasitics->Terminal to Terminal probes215835 ROD objects not translating properly in PCell215989 Need to support -maxwarns -maxnotes et al options in Spectre216025 DEFOUT changes pin geometry if aligned with boundary216066 Allow pCell usage of dbRead.cxt functions216136 Undo only works once in VXL although limit is set to 10216298 Inconsistent handling of Verilog property by AMS netlister216353 Schematic editor license issue

216366 Incomplete info from Design-Hierarchy-Tree when pcell is used216419 noise_table still cannot use result from calculation216560 Need netlist option for the top level schematic216649 Problem with outputs func with selectResults or openResults216827 5.10.41.169 VXL Auto-Abutment gives incorrect results217144 Ultrasim fails to netlist unit prefix symbols217165 HED GUI- Convergence/Accuracy field unreadable217189 Instance connectivity is wrong when auCdlCDFPinCntrl = t217310 CDL netlist with wrong termorder217396 amsdirect hangs while trying to netlist217923 VCP aborts when data has slant path that was attached to pin217949 Modify the UI for (automatic) hierarchical extraction218588 Problem with Outline FillStyle displaying as Solid FillStyle

218595 Relation between Last Checked&Changed and Components and Net218815 Create new environment variable MAP_SPECTRE_TO_SPICE218950 ICMS core dumps when very long inst.name should be expanded


13/38

219020 Display problem when creating mosaics219085 VXL UCN moves devices outside the P&R boundary219096 awd results browser not updating with AMS in ADE219098 StreamIn failed when tcDeclareDevice in technology file219333 AMS remote doesn't run ncsim on remote host219418 Can not plot histograms after Monte Carlo analysis219608 HED sourcefile support for ADE netlister

219782 Simple circuit does not converge in 5141 and MMSIM60220156 Spectre: corner environment saving does not work properly220192 Number of Ports field limited to maximum 20220321 Schematics placed as symbols do not display CDF values220331 Enhance amsdesigner to dump design hier info220387 Composer: Design--Probe--Add Net causes crash220450 nport does not netlist mapped net names correctly220457 STRETCH of WE does not do the same action as MOVE of VCAR220816 Edit CDF Form broken if cdsFuncs.cxt loaded220843 Category modified in LM does not refresh the category data221207 Calculator option OP does not work with iterated instances221310 Add force parameter to GUI for Spectre small sig analysis

221626 Need x-probing between Assura extracted view and schematic221658 cdb2oa has problems with symbol pcell parameters221979 Need whole net parasitic reporting in Assura extracted view222001 Terminal missing after lefin for NONDEFAULTRULE via defs222091 Write permission issue with hierarchical extraction222113 Netlist fails in AMS when inhconn is set to bit of the bus222126 Problem with tableSpacingRule translation222155 RunAbgen fails when abgen.rul file is used222212 pipo stream out truncates property lengths222506 Verilog Netlist Options not working in VSDE222576 Changing instance with Object properties form crashes tool222635 Option to add prefix or suffix for pcell sub-ckt instances222654 verilogA module hangs during compilation

222666 How does explicit netlisting decide module ports ?222884 OA Toolbox does not disassemble all routes223239 Asserts do not work in DC Analysis223296 Verilog In : An internal memory error has occurred. Exiting.223452 OA Toolbox (-toShapeBased) crashes223719 Make techfile electricalRules available in VCAR223819 VCAR is routing slowly223964 Composer extractor resets signal type db field224305 Label of vert/horiz cursor not correct when x-axis in log224329 Support DEFIN with Layout Views224668 cdsenv can not control Autorouting option224765 XLprobe gives segmentation fault with extract level set to 3

224809 Interactive chaining does not work as expected224856 techGetTechFile(id) causes seg fault under DM environment225057 VCP changes the location of locked component225185 Unable to select Instance Terminal close to solder dot225203 Internal error found in Spectre during DC analysis225292 cdb2oa divides all techfile minArea rules by 2000225302 Add more options to the VCE connectivity verifier225528 Spectre versions give differing measurement results225728 Label height=0 problem in 5.0.33 or later CDB225984 Want to change default Tool/Data Type of schHiViewToView().226061 Optional check for globals in Composer (in current level)226068 Guard Ring off grid issue226412 VXL extraction handles Must Connect pins differently in 5.1

226484 Problem with rodPath handles on 45 degree segments226850 VCE connectivity verifier fails to report all the shorts226878 IC5.1.41_USR1 not loading the amsDirect.simcntl variables


14/38

226974 SHM creation fails when SHMMAX is >= 2GB227274 Incorrect psf created when .print and sweep are in netlist227396 Truncate in Monte Carlo Mismatch analysis does not work227451 amsdirect fails with name map error227720 InstTerms lost after resetting vector inst range227730 DRE operations in icfb coredump using 24bit plane display227740 MC data file should be written out with higher accuracy

227828 Undocumented arg paramValues on the noiseSummary function228322 Problem with pipo 5.141 strmout on Linux 7.2 or 8.0228464 Provide CDBA label support for vertical bundle name228557 Make the env var that sets the sim name work228694 Internal node cannot be probed228695 Small timesteps when rgatemod=3 for bsim4 model228906 proute pin_trunk does not connect to pins under keepout229052 ddGetObj causes coredump when bad access mode used229311 cdsVia values wrong for Edit Contact Property - Contact Type229359 Need multi-occurrence frequency function229458 SKILL Lint rule for ddLockGetStatus is too severe229548 delmax option not available in hspiceD transient setup gui

229670 Hierachical update of connectivity reference of copied cells229747 Switch over wire grid effectively in Wire Editor.230072 Update documentation on sev SKILL functions230287 Spectre performance is SLOW when vtl default value is used230355 defout creates wrong syntax with variants of cdsVias230478 WARNING: invalid cell view -- 0(unknown) while stream-out230512 Need to have abstract add POLY obstruction in LEF230524 Need to use explicit tmp with AMS in ADE230868 Printing in wavescan does not work in the latest 5141 ISR230882 Annotating terminal currents using SKILL231140 Wrong *ultrasim: + continuation char for Other Spice options231220 Need repetitive ROD WARNING messages suppressed231268 *Error* parseString: argument #1 should... during PSP setup

231634 netSets are seen as pins in the schematic231925 AEL keywords are broken232122 Change docs to reflect var dbStatCacheOn not needed232136 AMS-ADE does not work in prefer implicit mode232290 OASIS 3rd party socket simulation runs twice in DP mode232299 cdsenv variables for all VCP UI232609 Parasitic symbol in extracted view does not highlight232744 Imaginary part of bjt504 base current jumps in sweep232970 Automatic Connectivity Extraction problems232987 groute crashes after user updates routing boundary233460 HDE in schematic side does not allow Pick from Schematic233829 Wavescan y-axis log lines incorrect for negative exponents

233876 Problems with connectivity reference lxSetConnRef233949 Be able to properly set the Hspice option BRIEF in ADE234194 Explanation required for large coordinates in VirtuosoXL234411 File->Export->DEF exports illegal row syntax234414 Warning in libManager.log while using assign in cds.lib234500 hspiceD inserts comment characters for long instance lines234593 Problem of ghost image during stretch command execution234647 Ghost image during Stretch for StretchHandle is strange234987 Net probe does not always work correctly on IC5141235068 ANTENNADIFFSIDEAREARATIO is printed with 2 digit precision235204 Gen From Source freezes VXL.235217 icfb crash if variable not declared in SKILL++ procedure235401 Property editor does not display 0.0 parameter correctly

235462 Why does R =NA in Report Parasitics Net of extracted views?235642 Registering a subType application gives error235873 Extraction error for shorting of named ports


15/38

235887 Docs for Design Data Xlater mapping is not correct236170 dbGetTrueOverlaps causing critical non-connection error236313 ncvlog parser produces out-of-date functional views236780 Wavescan calculator starts up with no calculator functions236838 Large Stipple pattern causes crash237034 VBIC model results are wrong if variable parameter is used237424 cond statement causes wrong compilation of cdsVias

237650 Avoid unexpected jog in WE.238188 DFII DEFIN supports BLOCKAGES with _+ COMPONENTS_ syntax?238301 Provide rmsNoise in WaveScan Calculator (MDL)238339 gdm_use_shlib_envvar not working correctly on HP machine.238349 Problem viewing property of a pin238535 Implement sourcefile in hierarchy editor for Spectre only238598 cdf parameter permuteRule not recognized by VXL239092 check and save should remove outdated netlist in master lib239384 Problem with setting Area Estimator Callback239527 Common button does not work too well for Ultra Pcell239816 Block cannot be move outside prBoundary once placed inside240037 Wavescan crashes with calculation on swept data

240096 Create Contact Form does not reflect the cdsenv parameter240334 Wrong axis in wavescan240376 lefout -readShapeBased does not output implant blockages240530 In read-only mode, ROD subparts are still editable240685 AMS Plugin crashes when processing long VHDL generics240711 Layer Selection Filter is ignored by leSetLayerAttributes240853 Severe memory leak with PSS in montecarlo240929 SpectreVerilog does not run on Solaris (Linux is OK)240960 ccpDFIIUpdtr should work for libraries with pcell designs241033 Angle brackets should not be converted to square241146 netTypes that expect trireg are renamed into trireg.241584 Netlisting error from AMS241739 Enhance tline netlist syntax for the hspice netlister

241771 Filler cells overlap with the preplaced standard cells.242099 In AMS in ADE, Direct Plot greys out after Simulation-Stop242392 CDL In reports an error if inst name exceeds limit242521 Problem with X Resource *borderWidth:2 and popup windows242587 Update documentation for OCEAN MC functions242656 GUI and AMS hang if direct plot runs during simulation242671 monteCarlo DP artfamily fails when loginShell csh is set242839 Document clocksync for DP242852 Auto calculate beat freq does not appear in pnoise form242942 Spectre does not delete xxx.tran.ckpt file when finishing SIM243046 DEFIN cannot build connectivity for filler cells243058 phaseNoise function errors out

243094 cdsfrb_lsf exists and gives lost connection error243172 Pin permutation breaks if pins defined in rule do not exist243274 Severe performance issues with Versionsync243709 Order of Performance Measurements for Corners tool243721 Document the int SKILL function244002 No CDF params displayed when tool filter set to Ultrasim.244414 Pnoise summary crashes on psfascii data244574 DFII crashes when descend to level of 43 downward.245013 Stack trace when lib spec for sourcefile property is missing245026 DFII crashes when from and to gdm specs are for same lib/cell245042 PSP stability K value seems very high for mixer ckt245474 auCdl seg faults when path to rundir is long - linux only245491 Cannot select Property radio button in Edit Properties form.

245766 Implement LEFaction property for Implant layers245886 NullPointerException in Wavescan when viewing sweep data246213 cdb2oa incorrectly instantiates magnified instance


16/38

253732 No DRD check for symbolic contact 1st with CreatePath253957 MDL gives the wrong answer in avg(trim)254210 Edit/Merge core dumps layout254599 cdsVia does not fit wire width when using Change to Layer254604 ADE Crash while netlisting with a long switch viewList (OA)254637 Comment after endmodule hangs genConnRulesFile script254760 DEFOut generates pin name with number instead of names

254773 Error message hard to understand254932 The selection highlight is not coincident to actual shape.254961 Spectre fails to report violations in dcOp255049 Display messages for instTerms not on extracted layer255051 Option to suppress Must Connect Violation in VXL255102 wavescan core dumps when using period_jitter255143 eyeDiagram function does not work in IC5141USR2255317 Device checking is failing for Inline subcircuit models255458 Incorrect s11 behavior for awd calculator255516 auProbeAddDevsForNet() does not work for bus/bundle nets255615 SpectreVerilog fails using Ocean255803 dbSave function documentation needs correction

255898 Improve Wired Editor usability255935 Preroutes get dropped when imported back to DFII255975 Sample mos.il not creating S pin model256007 Problem instantiating pin information from template file256064 Components properties not updated in USR2 users library256082 Cannot netlist a split bus with verilogA view256139 Can not chop shapes that have negative coordinates.256153 Verilog-A noise contributions not in output file256311 tline3 symbol from rfExamples library not simulating in DP256348 via_adjacency with LPP does not translate values256424 Problem with bitwise & function; documentation vs. use model256464 *WARNING* dbiUndoDemon: disable UNDO trigger received256484 Problem with schematic callback execution

256614 centerBox function casts coordinates values to integers256637 -ilPolicy does not show improvement; -ilPageMult needed256662 auCdl - automatic netlist inclusion within the Subckt Calls.256756 Load states form does not work on RHEL4256949 genConnRulesFile inserts wrong path to file257089 hiCreateRadioField shows wrong INFO while running SKILL Lint257285 defCONNMAP VXLDEF does not translating < and >257341 Set default trace mode for fft output as spectral257363 Packngo doesn't work with variables defined in cds.lib257373 Command line packngo won't accept another name for cds.lib257527 Strange Error message after changing an option for hspiceD257537 VSdE does not use burst licenses when Queue Command is used

257719 Problem with Direct Plot NF after s-param noise simulation258120 Remove and correct lxIgnoredParamForCAS from documentation258209 IUS55 AMSD simulation failure258607 Renaming a cellview fails when unrelated cellview is locked258865 Error when running job on linux from sun259187 rfLib entry incorrect in /tools/dfII/samples/cds.lib259320 Cannot annotate Component Params and Net Names259340 AWD hardcopy in EPSF format creates unbalanced paranthesis259502 MonteCarlo plotting passes/fails depending on release259595 Device correspondence cause session to crash259720 Fix the create path snap mode after press Default button.259762 Missing term definition for default net of inhConn data259855 OA cell copy prevents successful netlisting in ADE

260193 hiMoveField changes the buttonLocation260303 Cannot control position of Pin Labels260315 Bounding box has incorrect size


17/38

260353 CSI symbol compilation fails with SKILL error260361 Library Manager checkin in .inca and .pak files260397 icfb freezes on middle click in AWD after deleting sim dir260640 Add markers for the rest highlighted violation in VCAR261181 Incoherent warning message when markNet access mosaic insts261261 Why does TOM3 model give Ids=0A?261406 libSelect does not immediately update after a ddSetForcedLib

261513 Variable x is redefined after spectrei.cxt loading261523 Deleting highlight set w/ 24 thousand inst. takes too long261740 VXL corresponding layout not entirely highlighting in USR2261806 Asterisk is missing in .EQUIV in auCdl netlist261854 64bit cdba2icc hangs for versions after (cds) 5.0.33-64b.149261873 64bit icc2cdba hangs for versions after (cds) 5.0.33-64b.149261922 With 1st netlist line commented, VALUE missing in tran.tran262074 Want to specify default value of the Set Master Prop form262221 Print-> Noise summary does not work with Wavescan262254 ICC translator does not translate syEnhContact correctly262267 Placement status of the overlapped instance.262711 PIPO.LOG has lost affected library name on duplicate cells

263015 PhaseNoise not working with MonteCarlo263168 DEFIN causing icfb crash263284 Wavescan - unable to plot phaseMargin (core dump)263345 Spectre crashes while setting the output saved/plotted263356 Wavescan cannot read PSS/Fourier results from custom Spice263861 pnoise: noisetypeUI is not a valid parameter263909 Techfile wireextension has repeating decimal263978 Close file sits on a full disk with errset crashes icfb264062 amsLibCompile script missing in platform264411 Change default standalone mode of WaveScan to SKILL264603 .simrc changes do not take effect until second renetlisting264743 VXL: User Defined Area Estimation Function does not work.264851 DP gives same output waveform with graphical stimuli

264880 Fail to compile ahdlcmi265009 Unlike AWD, Wavescan doesn't display header with plot detail265142 Unit suffix not removed when applying EOP to all objects265335 Need hierarchical mfactor enhancement in cloning265388 UCN is broken265632 Problem with xor function in awv.cxt file265670 Spectre netlisting crashes on config files using long list265696 Pin/net highlighting problem with explicit Inh. Conns.266003 Edit Properties GUI for path doesn't work correctly266190 lefIn creates defaultAntennaRules for additional layers266205 Technology dumper is not dumping the correct antenna rules266386 Create a public function to create the runSimulation script

266489 Check abut class even when pcell super masters are the same266565 Modifying eg parameter in bsim3v3.1 doesn't alter sim result266617 5251 Composer Crash on Select266681 ddDeleteObj reports: Error concat illegal argument type-nil266910 Tool crashes when replacing via1 with via2 in layout267228 Missing module ports for inherited connections267500 Macro definition error in itkDB.h267507 Document -logFile- syntax/format for 3rd party integrators267636 Flexible balance presents incorrect number of tones267807 Retrieve WSF dumping support for digital data267826 Replay from Preview fails for a library with Tcl Interp267863 Flicker Noise implementation in VBIC needs improvement268235 Symbol properties are stacked for CDBA

268281 rpnMode breaks wavescan calculator268357 Checking incorrect in parameterization of indices & values268944 Rapid IP3 fails from Ocean


18/38

269131 Remote and local directories do not appear to be the same269172 Conversion tool for hspiceD outputs incorrect termMapping269341 Preselection Highlight within All Commands269511 vmsUpdateCellView does not support VHDLAMS cell269609 VXL crashes when GFSource with chaining on - 5141USR2269800 dcOp captab report incorrect when behavioral source used269843 Smith chart is NOT reloaded

269848 MPP after chopping shifts up by offset distance269917 Spectre aborts when subcktprobelvl > 2270016 SKILL Error When Netlisting AMS in ADE With Plotted nodes270039 Wavescan card mode broken in ADE270205 DRD to support individual rule checking control270254 Enhance: to change hierachical labels case sensitivity.270338 Wavescan - unable to mount table for read270457 Cloning crashes with selected instances270846 VXL crash with UCN with updateReplacesMasters=t on Linux271293 rexMatchp error when netlisting in Ultrasim or UsimVerilog271474 Inconsistent connections happen in CDLGenerateSubcircuitCard271532 simPrintInhConnAttributes causes direct netlisting to break

271750 DRD Setup Form Error Message needs to be more informative271766 bsim4 C-V curve discontinuity when capmod=1271799 Problem with ExportToRouter and missing path271967 deEditInPlace results in geEc errors272421 MDL prints wrong sweep data for paramset272559 Problem with savestate of cellview after Show Inc Net272603 cds_alias should be hardcoded to AMS272671 SKLINT - more descriptive message than transparent needed272946 dbfPDDCreateContact: Invalid layer/purpose warning273244 Appnote - DC device matching analysis tutorial273299 Select current into mixed signal pin shows no error message273390 asiSetEnvOptionVal does not trigger ncelab273415 Cannot use number as first character in library

273444 Line wrap in CDL include is defective for comments273661 Error when Virtouso_schem_option used tho 34500 is available273988 nmp Spectre namespace doesn't accept 1 a legal normal name274469 Need to have control over which mode is used for each net274561 Documentation of techCloseTechFile() is wrong274609 Path meeting a polygon skewed in IC5141USR2.274716 Issues with Spectre on certain platform in IC5141274936 Three separate steps to run AMS in USR3 will delete log file275048 PIPO error message difficult to understand275063 Enhance analogLib to support bsim 4.5.0 parameters275233 verilog-in reports corrupted net and illegal bus references275302 SKILL Lint does not report an error in IC5141

275515 An option enclose objects by rectangular shape of Guard Ring275517 The bus data numbers change by resizing the Graph Window275539 Add a browser to select file in Load Technology File form275562 Crash in SKILLPcellDataCallback while iterating instheaders275568 Reinstate Abgen menu item in Abstract menu275784 techSetLeLswLayers functionality is broken275804 cdlin is broken for subtypes in devMapping276367 Conversion toolbox adding subcircuit to componentName276547 ABS-1423 Exception Messages in abstract.log276646 Spectre simulation gives different result276821 SRC does not check the floating members of a bus.277086 How to output design variables by .PARAM in auCdl?277411 DEFin shd throw warning when the input DEF ver unsupported

277489 Var schematic broadcast freezes VLE commands277654 Internal error while netlisting split bus277816 CDLIN - Full P&R checked off not working for icfb workbench


19/38

277817 dbCreateStrongGroup has different functionality in CDBA/OA277910 API Enhancement to load in form information278231 a2d exhibits toggling behavior in MMSIM and IC278748 mpsImport hand-shake timed out of the Autorouting of VXL278965 VXL crashes when PFS with chaining on - 5141USR2279050 Cannot print noise summary form when running pnoise Jitter279116 Override Enclose By value in Guard Ring form.

279306 Autorouting cmd does not translate cell boundary correctly279323 Need AMS-ADE to output simulation data in WDF format279339 5141USR2 Extractor removes size zero attached wire label279412 Abstract generation creates wrong pin in the abs view279539 Provide time-domain waveforms for FB279853 QPSS flexible balance has no delete button280135 Fingers are not working correctly in VXL280229 streamIn gives FATAL(299) Error280257 A redundant pin description was output to the template file280488 *Error* close: Error closing file message in streamOut280499 *WARNING* Illegal Iteration280603 EMI: Unable to connect to Library Manager

280723 Respect GDSII Limits option in Stream Out280777 Behavior change in streamLayers between IC446 and IC5141280937 tableSpacingRules width enhancement280971 Power spectral density computation (PSD, PSDBB)281003 AG does not extract ANTENNADIFFAREA in some cases281267 Search and Replace causes crash281314 FATAL 369: Bad Stream record length -2 encountered281357 Editing properties causes crash or freeze using IC5141USR3281485 Subrects for diagonal ROD MPP segments281490 SRR with paramset results is not seeing all leaf signals281508 EMI: Over the coordinate max error needs to be in PIPO.log281739 Pick from schematic fails to chain devices281941 verilogIn creates different labels on the same wire

281960 pxf direct plot Output harmonic wrong when log sweep used282008 CDF param with a bin value causes AMS designer to fail282185 Align command fails when Multiplier is a large number282239 Explicit Verilog netlist on instances including split buses282306 Spectreverilog creates incorrect netlist for single bit bus282806 Unexpected Warning message on Copy command282937 Ports under the hierarchy not showing up in PSS GUI283129 Export to CCAR: error mpsImport handle obsoleted283171 geHiDragFig fails to respect the l_firstPoint argument283196 Label sizes lost when printing or saving as image283260 Hierarchy Ed updates are not passed to AMS netlister in ADE283468 cdsenv wavescan.graph objects forces background color

283585 Would like to plot QPSS fd data from direct plot form283626 ADE Create - netlist causes system to hang283632 Response to users input very slow due to license checking283753 ADOPTION ISSUE:Precision returning from techlib has changed283878 Want to merge the paths for selected at a time284029 Make ncvlog as default parser for Verilog-D views284133 auCdl : Severe Performance issue when auCdlCDFPinCntrl set284274 No documentation available for PIPO warning message284852 Get core dump when Device Correspondence is performed284891 Need message of duplication cells information in STREAMIN284903 Edit Contact Properties - Common option causes crash284916 Clone command does not clone the routed global wire285056 Data Refresh results in icfb crash

285161 Ghost is not displayed when rotating an object by Move285217 aelPushSignifDigits needs to be higher for RF analyses285292 Cannot plot terminal currents in AMS in ADE


20/38

285324 Incompatible SKILL of IC5141 USR3 and IC5141 ISR16285435 Via gets promoted to next level in VXL when it should not285563 @ button in the Wavescan Calculator not working in WIA285611 Ocean creates incorrect dcmatch netlist285702 Smart way searching cellName in Cell Name field of Open form285754 IC5141 Update Components And Nets does not work286007 schHiCreatePin() does not work in which t_mode is array.

286262 schHdlUseNcvlogForVerilog invokes AMS parser for verilog286282 Backport fix for PCR 760786 to 5141286343 Wrong Verilog template generated for vector pin with holes286690 Segmentation fault when retrieving cdf286707 Crashing DFII Data by Loading SKILL286847 Tool filter autoUpdate forces a schematic check and save287063 Problem plotting from Wavescan287271 Cannot create pseudo parallel conn for shared gate devices287447 asiMapOutputName strange behavior287461 Gravity does not work on non-rectangle pin figs287845 vpwl / vsource netlisting bug288298 Stream IN/OUT a layerNumber greater than 255 in CDB and OA

288344 Incorrect evaluation of integer variable in MDL.288404 LSSP seems to do an unnecessary sweep288406 Would like to be able to do single port LSSP288907 Schematic check rule verilogSyntax error289021 Edit Component Types is slow when run in DM environment289070 SKILL calculator evaluation is too long for large datasets289113 VXL: Gen from Source places pins off grid289124 IC5141USR3 : 64bit layoutPlus running out of memory at 2Gig289246 DRD: minExtension rule not working in techfile289280 Incorrect DEF when multiple segments combine into one path289388 Dag browser pulldown popup scrolls to top of the screen289556 Wavescan: wrong 0 degree (AC phase) plot289571 EMI for *WARNING* techLayerPurposePriorities: Failed to set

289629 Spectre netlisting failure for a given cell (auCdl works)289772 analogLib src components do not netlist correctly for ams289897 DRD support for minLength and maxLength rules290019 IC5141 USR3 - Not evaluating ADE output expressions290244 A Bug of auto-guardring.290442 ADE setup for pnoise analysis changes when netlisting fails290503 simNetNamePrefix has no effect in auCdl fnl mode290656 Get crash when long stop and view lists are used in ADE291455 Edit Search Feature in layout is slow in IC5141USR2 and USR3291673 Problem with hnl based hspice netlister292424 Unable to netlist an mtline primitive in AMS/ADE292578 *WARNING* Cannot re-register invokeNCTools

292708 ICOA5141USR3 crashes on Check & Save Schematic292727 VCP placer crashes when using STDSUBCONT292728 DRD does not understand 1D table rule if matchType provided292977 Currents in sst2 lead to different results structure292998 Sort by Function in LSW causes crash293035 Plotting corners current not working with SST2 format293199 LibManager reports view not found293273 Snap to peaks not working in USR3 for markers or cursors293358 Flight line does not updated during move command293384 Program aborted using Control + C293412 adpInitProc does not work293556 Preview: Checking partial overlap causes performance issues293589 Preview not creating m1 grid for non-preferred direction

293602 Loading through DRL too slow for large data293703 Wavescan marker table number not updated as markers update293726 Digital waveform in sst2 not plotted after simulation->stop


21/38

293773 AG extract extra ANTENNAMAXCUTCAR for non-existing via293851 ip3Plot broken: a macro must be defined before its use293853 Netlisting now gives error about split bus in explicit mode294115 leCheckMissingLayers: unbound layers not reported294116 AutoContact spent 5 minutes and did not generate294205 Need option to Zoom in on the given X & Y coordinates294466 DEFOUT shifting rotated via arrays

294598 MDL WaveScan gives strange messages in Unix window294610 Properties lxVcpSubContMinSpacing/ lxVcpSubContMaxSpacing295010 STDSUBCONTs are inserted at R0 regardless of row definition295113 Incorrect PIN orientation in DEF file on DEF out295161 Customer wants layertap behavior changed295185 Wavescan menu option Hide reveals previously hidden waveform295426 Extract step hangs on Linux machine295677 Check+Save with netSet CDF defaults crashes icfb295691 Loading state with no analyses shows old analyses in listbox295932 ansCdlCompPrim : M factor is netlisted in upper case296044 icfb crashes when reading a >8K long string296103 SpectreVerilog netlisting problem

296389 auCdl netlist fails when used auCdlCDFPinCntrl=t296508 cdba2icc is not setting LD_LIBRARY_PATH296533 EMI - WARNING define parameterized cell -296906 Wavescan - Parametric phasemargin in mdl mode296925 PIPO does not handle hierarchical PCells correctly296990 Remove iccDefaultOptions variable ref. from .cdsenv297151 TraceCursor has small interpolation error297453 CDS_AUTO_64BIT is not ignored on 32 bit machine297884 Noise Summary to work for pnoise after Swept PSS298109 Edifin fails with segmentation fault298224 mtline incorrectly generates netlist and rlgc file298428 CIF --Input File needs more description298489 pinTextPurpose environment variable is not working

298507 Objects get deselected when copying to read-only view fails298597 Axis labels do not match grids due to round off errors299078 Provide option for geDeleteAllMarker299284 Abstract generation on inductors299556 Incorrect WaveScan default paper size setting from icfb300035 Edit/Align creates shorts for pcells with rotation MY300049 Using parameters vdb, vgb and vgd in assert statements300075 Warning when loading display.drf300119 Warn about old-style asymmetric cdVia imported300131 verilogIn creating wrong connections when cds_thru involved300892 VXL crashing when descending the hierarchy301245 CDL import warnings can not be found

301289 TechFile Manager compiles wrong TechFiles successfully301352 Cannot plot net voltage for a net with parasitic resistance301753 Hide Global Nets forDraglines determines global nets by name301801 Saving to a DM library from layout editor causes looping301821 Wavescan fails to maintain plots between single run & parame302051 Pin labeling does not work with edit-in-place in layouts302170 analogLib mtline cdf form incorrect for strip and ustrip302563 Document the cdsLibManager.copy updateChoice variable302567 libSelect does not immediately update after a ddSetForcedLib302706 Polygon points allowed in emu. layer should be sync with OA303053 Model file path does not accept {}303147 cif erroneously sets CDSLIBCHECK ON in newly created files303209 VXL Transistor Folding not working and causing crashes

303522 Getting errors when reloading waveforms303555 AMS-ADE: cdsenv ams.compilerOpts broken in IC5141-USR3303669 amsdesigner command: need inherited view list switch


22/38

303896 AMS mistakes the connection of bus304278 Issues with new parameter of sine source304370 DIVA access to boundary shapes in ICOA304494 simIgnoreTerm variable breaks Spectre or spectreVerilog flow304838 The invisible option does not work.305150 Provide a way to ignore existing pins on layout305157 Syntax error in sampler Verilog-A example needs fixing

305394 Selected cell in LM is convulsed when cell dir mode is 000305432 Extractor aliases two unrelated nets into a connected net.305487 AG doesn't create pins from labels and intersecting shapes305747 Support s-parameter input for mtline symbol305839 Can not add Via with Wire Editor305876 Abstract Generator pin extraction problem305892 Provide a way to translate ties to netExpressions306091 Mapping * in bus name to _ using Verilog-XL Netlister306264 auCdl netlister does not include model= In Netlist306452 Model library setup form displays wrong section names307538 auCdl netlister truncating names at 127 chars307545 Abstract does not honor Pin Access Direction

307701 Always take the instName prefix for nlGetSimName307760 gec3TechFile is trying to map symContactdevices incorrectly308285 vpi_handle(vpiLowConn,vpiPort_Obj) return nil in IUS57-p001308415 Supports donut shapes for soft block308854 cdsEnv drdEditHierDepth not working308872 Chaining causes crash during Gen from Source309123 hiDisplayForm seg faults when form has many tab fields309338 Incorrect simulator grouping in ADE (--) dashed list309419 ADE Montecarlo does not update mcdata output file309585 Internal error with amsdirect313611 analogLib nport does not netlist correctly for AMS313640 DFII crashes when VCP runs on ROD instances313682 Lose implant layer when Devices section split with 2 files

313753 Add *ultrasim: for Other Options313800 Need a way to map metal filling from DEF to drawing313810 Waveform disappears if action is done during sim run313814 Transistor Chaining changes orientation unnecessarily313852 OCEAN - ParamRun in distributed mode with MMSIM causes error315343 Incorrect value displayed when the marker label font changed315465 Would like cdsenv for hePromptForm defaults316583 Model zero ANTENNAGATEAREA & zero ANTENNADIFFAREA317182 subckts-info and asserts-info do not appear on ResultBrowser317607 Document all identifiers for lxComponentType Property317751 CDL Out - pinOrder in inst, with implicit inhConn, incorrect317901 Expressions order differ between corners and results display

318079 Expressions->Edit messes up data and column labels in RDW318229 VXL extractor takes too long to open design with mosaics318440 Label display in out of context schematic appears to hang318476 AG crashes while generating blockages for layer via2318504 Using dB20 with dft displays incorrect output in wavescan318525 Wavescan displays data on the wrong log scale318573 VXL 5.1.41 USR3/ISR transistor folding still crashing318587 Antenna calculation differs when signals are extracted318751 Abstract Generator prints 0 value for ANTENNAMAXAREACAR318879 Modelwriter prevents VerilogA views from being edited318885 The display packet showed in LSW and DRE differently.319074 Label display does not show result of bitwise operation319328 Auto Abutment function did not remove the contact

319423 32-bit icfb crash319488 Divide by zero error when printing noise summary319494 Allow choice of none for input source in noise analysis


23/38

319503 Default EDEN proj dir setting does not work correctly319582 auProbeAddDevsForNet() warnings and not highlighting319595 HspiceS netlister gives incorrect port order319751 ncvlog shipped with DFII320515 hiCreateOptionsForm - invisible setting not used320634 Improve error when terminal current fails to plot320836 userDisciplines.vams not handled correctly in ADE

321012 Saving veriloga view checks out prop.xx many times321231 Unable to view digital signals during UsimVerilog sim321240 Incorrect mcparam file when add new output to Monte Carlo321519 AG creates CORE pins even though pins are not on core edge321908 Mismatched layer name was displayed in Properties form322053 Rotate causing crash322327 Different notation for COMPONENTS and GROUPS in Preview DEF322386 Wavescan legend value becomes unreadable after Zoom322417 Edit properties on attached schematic label gives warning322861 LSF and queues list in Distributed Processing mode322897 Spectre needs to start a new matrix for altergroup corners323235 dubiousData invalid graphic layer error

323241 CDSLIBCHECK ON breaks verilogIn323245 TechFile GUI: Can not edit table spacing rules.323548 dubiousData fails with geomCat323664 Stream In ignores cell even if the view name is different323714 ciwMenuLoadFile function documentation/behavior consistency324113 Interface Element bus not netlisted correctly in IC5033324152 ADE hangs if incorrect ports are specified for sp analysis324270 Can not plot the bulk node running AMSspectre in ADE324339 Problem with deOpen() return value for config views324620 ams.envOpts simExecName does not work325005 Line style changes for wires, when schematic is copied325558 EMI: Cannot get AMS environment License325706 Line style changes for wires when copied or moved

325838 AMS-ADE Save All doesn't save tasks325871 deOpen: Problem opening a config with zero size expand.cfg326204 Use rule order for LSW Layer Purpose Pairs326934 Add font fontsize arguments for titles and subtitles326984 Need method to determine lib when cell is in multiple libs326991 Flat vs hierarchical error traversal326994 When cell opened, add option to raise window or open new326997 Provide ability to select another cell from navigator window327032 ncvlog parser giving VAN parser error327123 Constants on Verilog port connections cause fatal error327482 dbWriteSkill misses Mosaic Pcell parameters327562 amsdesigner use relative path in project and run directory

327569 CDLIN Creates Duplicate Pins (G, S, D, B) with Different Net327912 phaseNoise function does not work with MonteCarlo in OCEAN328097 Extractor does not recognize the connection from via on cell328179 Set Default Application cannot set when I launch layoutPlus.328748 Update components and nets is crashing329014 VerilogIn: *internal* (getNetDecl: could not find net).329185 Doc should explain the effect of netlisting mode on labels329218 Create Rectangle and Create Path command crashes the tool329283 Fault which cannot do folding329373 modf function missing329734 aelPushSignifDigits: argument #1 should be an integer - EMI329933 CIF import completes successfully but the design is wrong330094 Enhance request for WARNING 181 while stream in

330175 Diva Shorts Locator perpetuates Assura_DV_LVS_checker330284 DEF in/out, via and pin problem330305 DraculaToDiva missing in IC5141ISR, exists in USR3


24/38

330327 DraculaToDiva generates garbage file and name in Linux330620 VCP does not align gates of P/N devices properly330746 Need itkDB library to be recompiled with -fPIC flag on linux331083 ASSERT failure in file dlp_violation.cpp, line 226: violation331124 Not able to cross probe the current data331137 Hierarchical mode in DIVA is disabled under 5.2.5.1331232 EMI: Error: request.il asiiFinish: error in finish function

331470 Unable to plot subckt terminal currents when using sst2331620 Wavescan table incorrectly prints negative swept data331824 UCN problem.332072 VCP leaves gaps between devices332076 Awd via Ocean grows to 100% Memory usage and errors out332300 SpectreVerilog Ocean fails when digital bus node saved332366 dbLayerAnd returns nil for overlap less than 0.001um332409 Stretch handle on diagonal edge of a poly gets corrupted332648 leSetInstSelectable not toggling the LSW switch in USR4332893 Shft tab does not work in Schematic Property Editor form332916 Internal error ABS-1423, assertion failed333062 Result Save-Open does not work for parametric analysis

333600 Make Cell deletes non-empty net at top level333638 PIPO doc is unclear on Keep Reference Library333923 Contacts disappear when stretching a guardring333955 Invalid orient warnings occurs when add probes to nets.334267 Local copy of icms breaks AMS in ADE in USR3334280 Core dump occurs when clone source contains MPPs334481 DRD enforce does not transpose coords correctly during EIP334572 EMI: Spelling mistake in warning for property bag334826 Documentation for env var drdEditMode is incorrect334904 Gravity depth set greater than zero causes wrong snapping334981 analogLib ind cell does not netlist model name for hspiceD335248 After Transistor Folding shared contacts disappears- problem335378 OP info shows diff polarity & value of Id in diff versions

335384 Composer crashes on one platform335445 PFS and UCN are not maximizing source335503 cdlin does not support bidirectional pins335525 The Partition option is not effective.335528 Delete All Markers does not work in hierarchy mode.335743 Problem plotting montecarlo histograms335744 Cell attributes set to nil when preCreateObj trigger called335802 XY axes are not displayed in the plot...335817 Enhance Netlister to Prefix pcell subckt instances uniquely336035 License checked out while opening cell with read only permi336198 The start of VXL is slow336334 enterPoint function to descend into schematic block - crash

336721 Verilog netlist takes 9 hours to produce336756 Wrong termOrder in auCDL netlist with ansCdlSubcktCall336999 Modifying VHDL entity does not prompt for symbol create337543 Offgrid result from layerAndNot337756 Transient current component display for .subckt not updating337879 UCN does not update the components correctly338102 lxGetLXInfo gives wrong info after descend edit and return338483 ilGetString error when loading a state saved to cellView338664 Can not display a Cursor on Wavescan when changing mode339493 Simulation much slower with monte-carlo than nominal339876 How to output implant obstructions into LEF340404 auCDL netlister does not netlist the value (M=1) .340608 symContactDevice vias in LEF creates problem in Encounter

340671 DIVA ability to save to OA boundary blockage objects342072 Explicit netlisting is causing core dump342212 Low speed of Virtuoso Custom Placer pin placement


25/38

342266 drSetPacket command slows session342297 CDL In does not use master cell of nor2 from refLib:342344 Verilog netlist with Support Escape Names turned on failing342422 Significantly longer extraction time upon initiation for USR342516 Wavescan: Retain Markers and Labels setup in Replace mode342836 rfExamples integrity issues for 5141USR4 CDB and IC61 OA343418 simPrintInhConnAttributes = t causing floating net cdsNet0

343859 Env var to disable extracting on non-extractable layers344326 Automatic generation of net expr fails with bus pin344340 EIP Search for area does not work344656 cdsDoc and Finder have a typo for dbGetOverlaps344792 Path stitching gives false error of maxWidth while DRD is ON344882 geAddInstProbe does not always probe the right devices344924 Align ignores pitch value when using Component Origin344986 Truncation Error in printvs in AWD for more than 2000 points345218 pipoIn is doing wrong mapping assuming that gds# = layer#345529 Bus with reversed bit vector netlists as bundle in Verilog346768 Insts dropped in presence of mosaics for name conflict346811 Tree widget stops work with GC errors

347588 Wavescan doesn't plot eyediagram properly from Monte carlo347712 Verilog netlister renames net to _clash348155 Symmetry R0 should not be allowed348218 Lower layer is past outside when make contact348379 Need a way to tell VCP which view to use for STDSUBCONT349060 leSetLSWFilter() function cause crash349656 HspiceD netlister does not netlist certain mapped parameters349813 Need a new interface to pass valid number of pins349841 *Error* rplaca: first arg must not be nil - nil349911 VXL crashes when wiring bus350235 Create Boundary Pins for Power Nets causes missing pins350529 Import from Router cmd is very slow if layout has MPP obj351362 VCP:Std. cells not being placed in to the default partition.

352189 cdfCopyCDF - change in destination cell CDF affects source352304 Stretch handles increment semantics have changed352370 ccpRenameReferenceLib not working properly352463 Abstract Gen creates obs geometries not on manufacturing grid353594 Print out signals from WaveScan becomes distorted354332 Need to be able to turn off recursion check357408 The derived layer cannot consider table spacing rule.357884 Output Log->Simulator Log... for AMS from ADE shows wrong lo357969 CDF param could not store even if storeDefault is set as t359121 34510 license is released when AMS simulation is running.360204 Wavescan markers not being updated361128 Avoid verilogIn to add property netType=supply0

361293 Xlib: Maximum number of clients reached361594 coeffgen unable to create Diva rule on Linux361684 Floorplan > Reinitialize form bug361883 ADE generates platform dependent netlist361919 L and W are changed to zero when cdl in to schematic362943 Error pslNewTextSemantic: Could not create semantic - nil363552 Dialog box with pss when errpreset not set is out of date363817 Wavescan bindkeys do not work for some SKILL functions364417 Enhance Tree command365717 Merging geometries in layout causes shapes to grow366112 GFS does not consider the signification digits.366386 Add the skipDbLocking option into PIPO GUI.366830 Diva extracted view is empty when ivExtract is run by CIW

367300 Spectre :61,5141USR4, latest AC analysis is slower368168 Direct Plot of Bussed signals in AMS does not work368755 DRD in USR4 slows down when moving large instances


26/38

368773 Does not allow DRC violation shape handling fixed by area368781 extratStopLevel to zero on arrayed instance causes delay368806 Abutment function getting incorrect connection value368988 AMS-ADE cannot find cells compiled into explicit TMP369127 Very slow loading of info data when more than 50K objects369324 deltaY snaps to deltaX while editing contact array in IC514369766 verilogAMS regeneration fails after netlist & run in AMS ADE

370012 ADE netlister does not netlist large designs370401 Indicate rule code into Marker Report370456 Wrong output after s-parameter analysis370485 Abstract Generator creates offgrid blockages370894 Error using sparameter 2 cti files in Spectre370960 Browse button in ADE-Model Libraries should NOT expand links371170 Sorting function for rule selection371740 CDF field on the property editor is limited to 2047.48371828 envopts OSS-based & ncverilog do not work if set in .cdsinit372017 Flyback and wavescan372847 CDL in crashes due to long subckt name372885 Vsource negative port current not saved correctly

372939 Chopped MPP causes errors when chopped near corners373330 Can not use veriloga model writer with Virtuoso_Spectre373611 No plot of pnoise jitter phase noise when nodes are saved373671 Can't set row/col > 69 in symbolic contact in IC5141USR4373682 Locked instances are moved (0.001um) when VCP is run373948 Un-localized variable in 5.1.41 USR4374138 cdsViaDevice movement distance doubles in VXL374458 ams.envOpts simExecName does not work for ncverilog flow374475 No uniform spacing around cdsViaDevice when using odd dimens374788 UCN always makes a new prBoundary.375147 CDLout macro ckt using _ansCdlSubcktCall outputs model twice375254 USR4 requires aelSetLineage, but USR2 does not375674 AMS in VSDE broken with Tools->Option Raw file location

375722 API is sending request but ViVA is not hiding the signal375917 EKV model implementation does not calculate drain and source375948 AMS Designer parametric analysis gives error375999 drLoadDrf resets valid layer set376260 Sym contact on non-drawing layer not displayed on Create form376343 Netlisting failed with a testcase376790 PcDots3.bit created wrongly by ICC translation378019 Locked instance is moved when VCP is run378115 Bugs in OSS inherited connections scheme.378219 Pin Placement locks up VXL378326 IL API leiCreateTechConnectLists() causes performance hit378965 Shorted nets not found by Check&Save

379485 AG creates rectangular instead l-shaped overlap boundary379715 Problem with minwidth and minNotch rule380293 IC5141USR4 crashes when calling SKILL function - dbCreatePol380957 ADE calculator write calc fcn, not Ocean functions,380997 Explicit netlisting of split-bus which no use some bits part381296 Alignment has offset in Edit in Place381316 fail to change terminal name in virtuoso layout editor381626 MC Load/Save State forms do not remember form values381931 Error output use dft function when start point = outputstart382003 Context files loading with errors - generic:nlGetNetlister c382169 Provide translateTopDown option in PIPO GUI382827 Output syntax error message when executed create wire382854 Copy pin property

382926 AMS_NETLIST_DIR not getting set properly for AMS DP383442 OSS AMS netlister not escaping reserved words383633 VXL crash after Gen From Source


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384513 Incorrect pxxx results when doing a reverted spss384750 Layout core dump by new DRC browser385187 Incorrect syntax used in cds_globals with OSS netlister385522 isFile error while passing CRs to ncverilog in ADE385736 Incorrect pmos length and width pa

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