UnitedSiC Cascode JFET 650V Family - systemplus.fr · This report provides a detailed manufacturing cost analysis of the JFET, the MOSFET and the package as well as the estimated

©2019 by System Plus Consulting | UnitedSiC Cascode JFET 650V Family | Sample 1

+33 2 40 18 09 16 [email protected] www.systemplus.fr

UnitedSiC Cascode JFET 650V FamilyGen3 Silicon Carbide JFET co-packaged with Silicon MOSFET

22 Bd Benoni Goullin44200 NANTES - FRANCE

SP19467 - Power Semiconductor report by Amine ALLOUCHE Laboratory Analysis by Guillaume CHEVALIER

August 2019 – SAMPLE

REVERSE COSTING® – STRUCTURAL, PROCESS & COST REPORT


Table of Contents

Introduction 4

o Executive Summary

o Reverse Costing Methodology & Glossary

o SiC Power Device Market

Company Profile & Supply Chain 10

o UnitedSiC Portfolio & Technology

o Supply Chain

Physical Analysis 18

o Summary of the Physical Analysis

o UF3C065030K3S

Package Analysis

• Package Opening

• Package Cross-Section

SiC JFET Die

• JFET Die View & Dimensions

• JFET Die Process

• JFET Die Cross-Section

Si MOSFET Die

• MOSFET Die View & Dimensions

• MOSFET Die Process

• MOSFET Die Cross-Section

o UF3C065030T3S

o UJ3C065030K3S

o UJ3C065080K3S

o UJ3C065080B3

Manufacturing Process 109

o JFET Die Front-End Process

o JFET Die Fabrication Unit

o MOSFET Die Front-End Process

o MOSFET Die Fabrication Unit

o Final Test & Packaging Fabrication unit

Cost Analysis 121

o Synthesis of the cost analysis

o Yields Explanation & Hypotheses

o UF3C065030K3S

o JFET die

JFET Front-End Cost

JFET Die Probe Test, Thinning & Dicing

JFET Wafer & Die Cost

o MOSFET die

MOSFET Front-End Cost

MOSFET Die Probe Test, Thinning & Dicing

MOSFET Wafer & Die Cost

o Complete Device

Packaging Cost

Final Test Cost

Component Cost

o UF3C065030T3S

o UJ3C065030K3S

o UJ3C065080K3S

o UJ3C065080B3

Selling Price 174

o Estimation of selling price

Comparison 181

o Comparison between the different devices

o Comparison with SiC MOSFET with close electrical performances

Feedbacks 194

Company services 196


Overview / Introductiono Executive Summaryo Reverse Costing

Methodologyo Glossaryo Market

Company Profile & Supply Chain

Physical Analysis

Manufacturing Process Flow

Cost Analysis

Selling Price Analysis

Comparison

Related Reports

About System Plus

Executive Summary

The silicon carbide (SiC) power market is taking off and its value will approach US$2 billion by 2024. The reason is that SiC-based device penetration is expanding in different applications. Taking advantage of this growing market, UnitedSiC,, announced a strategic investment and long-term supply agreement with Analog Devices, Inc. (ADI) in March 2019.

UnitedSiC offers a large portfolio of SiC devices, mainly with its unique cascode co-pack configuration.

In this design, a Silicon MOSFET is combined with a SiC JFET in one package.

UnitedSiC offers two types of cascodes: UJ3C for “ease of use” when upgrading from a silicon device and UF3C for high-performance designs with faster switching Moreover it proposes the latest solution in die assembling; the silver sintering

In this report, System Plus Consulting presents a deep technology analysis of the 650V cascode family: five components are analysed across the UJ3C and UF3C series, assembled in two different types of packages; whith and without silver sintering

Detailed optical pictures, scanning electron microscope cross-section, and energy-dispersive X-ray analyses are included to reveal UnitedSiC’s technical choices at the microscopic level of the die designs.

This report provides a detailed manufacturing cost analysis of the JFET, the MOSFET and the package as well as the estimated selling price of each one of the five cascode components.

Finally, this report compares the technological, physical parameters as well as the production cost and price of the Cascode JFET family’s devices.

A technology and cost comparison with a SiC MOSFET, with similar electrical performance, is also included.


Overview / Introduction


Physical Analysis o Synthesiso UF3C065030K3So UJ3C065030K3So UJ3C065080K3So UJ3C065080B3


Cost Analysis


Comparison

Related Reports

About System Plus

Summary of the Physical Analysis

UJ3C065080K3S (80mΩ - 31A):

o xx dimensions: xx mm²


UJ3C065030K3S (30mΩ - 85A):



TO-247

TO-247

UF3C065030K3S (30mΩ - 85A):



xx

xx

xxx TO-247

xx

UJ3C065080B3 (80mΩ - 25A):



D²PAK

xx

xx

xxx

xx

xx

xx

xxx

xxxx

xx

xxx

xx




Physical Analysis o Synthesiso UF3C065030K3S

Package xx Die xx Die

o UJ3C065030K3So UJ3C065080K3So UJ3C065080B3


Cost Analysis


Comparison

Related Reports

About System Plus

Gate Wire Bonding:

o xx Al wire.

o Diameter: xx µm

o Medium length: xx mm

Source Wire Bonding:

o xx Al wire.

o Diameter: xx µm

o Medium length: xx mm

Package Opening

Package Opening – Tilted View©2019 by System Plus Consulting

Package Opening – Optical View©2019 by System Plus Consulting

xxxxxx

xxx

xxx

xxx

xxx

xxx

xx

xx

xx

xx xx xx

xxx








Cost Analysis


Comparison

Related Reports

About System Plus

Package Cross-Section

Package Cross-Section – Optical View©2019 by System Plus Consulting

xx

DBCxx

xx

xx

o xx is used as substrate for xx.

o Xx is soldered with xx on xx leadframe.

o Layers thickness:

xx : xx µm

xx Top xx : xx µm

xx Bottom xx : xx µm

(x) xx layers : xx µm

o xx solder xx quantity : xx mm³

xxxx solder section xx mm²

xx

xx

xx

Copper leadframe

xx

xx layers

xx

xx

xx µm

xx

xxµm








Cost Analysis


Comparison

Related Reports

About System Plus

JFET Die Process – Pitch & Guard Ring

xxx

Die Process after delayering – SEM View©2019 by System Plus Consulting

o Pitch: xx µm

xx µm


Guard ring xx µm








Cost Analysis


Comparison

Related Reports

About System Plus

JFET Die Cross-Section – Source area

xx Cross-Section after oxide revelation – SEM View©2019 by System Plus Consulting

xx Cross-Section before oxide revelation – SEM View©2019 by System Plus Consulting

Cross-section axis

xx

Alxx

xxxxx

xx

xx

xx

SiC substrate

xx

xx xx

xx

xx

xx








Cost Analysis


Comparison

Related Reports

About System Plus

JFET Die Cross-Section vs Delayering

Cross-section axis

xx µm

xx µmxx µm

xx Delayering top views and Cross-Section – SEM View©2019 by System Plus Consulting








Cost Analysis


Comparison

Related Reports

About System Plus

JFET Die Cross-Section – Backside EDX Analysis

xx

xx solder

xx Xx Substrate

xx

xxxx

o xxlayers are detected on the xx die backside.

o Layers thickness:

xx : xx µm

xx : xx µm

xxxx

EDX Anlysis©2019 by System Plus Consulting








Cost Analysis


Comparison

Related Reports

About System Plus

MOSFET Die Process



xx µm

o Pitch: xx µm

xx µm








Cost Analysis


Comparison

Related Reports

About System Plus

xx

xx

xxx

xx

Die Cross-Section

Package Cross-Section – Optical View©2019 by System Plus Consulting

Package Opening – Optical View©2019 by System Plus ConsultingCross-section axis

Si xx

xx

xx

xx

xx xx

xx

xx

xx

xx








Cost Analysis


Comparison

Related Reports

About System Plus

MOSFET Die Cross-Section

xx

xx

xx

xx

xx

xx depth: xx µmxx depth: xx µm

xx

xx

xx Cross-Section after oxide revelation – SEM View©2019 by System Plus Consulting




Physical Analysis o Synthesiso UF3C065030K3So UJ3C065030K3So UJ3C065080K3S


o UJ3C065080B3


Cost Analysis


Comparison

Related Reports

About System Plus

xx Die Dimensionsxx mm

xx m

m

xx Die – Optical View©2019 by System Plus Consulting

o Die dimensions: xx mm² (xx x xx).

o No marking on the die.




Physical Analysis

Manufacturing Process Flowo Process flowo Front-End Fab Unito Back-End Fab Unit

Cost Analysis


Comparison

Related Reports

About System Plus

xx Process Flow (1/4)

Epitaxy

• N- Epitaxy

Doping Implantation

• xx deposition

• Pattern xx

• P well implantation

• N+ implantation

xxx• xxx deposition and pattern

SiC Substrate

N- Drift Region Epitaxy

SiC Substrate

SiC Substrate

00




Physical Analysis


Cost Analysis


Comparison

Related Reports

About System Plus

Description of the Wafer Fabrication Unit – xx

In our calculation, we simulate a production unit using xxx wafers.

xx wafer fab unit:

Name: xxx

Wafer diameter: xxx

Clean room class: xx

Capacity of xx line: xx wafers / month

Year of start: xx

Products: xx

Location: xx




Physical Analysis


Cost Analysis


Comparison

Related Reports

About System Plus

xx Process Flow




Physical Analysis


Cost Analysiso Yields Explanationo UF3C065030K3So UJ3C065030K3So UJ3C065080K3So UJ3C065080B3


Comparison

Related Reports

About System Plus

xx Front-End Cost

The front-end cost ranges from $xx to $xx according toyield variations.

The main part of the wafer cost is due to the xx (xx%).The xx steps represent a large part of consumable andequipment cost (see details in the following pages).




Physical Analysis




Comparison

Related Reports

About System Plus

xx Wafer Cost per process steps




Physical Analysis




Comparison

Related Reports

About System Plus

xx Die Cost

The xx die manufacturing cost ranges from $xx to $xx according to yield variations. Withxx margin, the die cost ranges from $xx to $xx.

The Front-End manufacturing represents xx% of the component cost, medium yield.

Probe test, dicing and scrap account for xx% of the component cost.




Physical Analysis




Comparison

Related Reports

About System Plus

Cost Breakdown Cost Breakdown Cost Breakdown

JFET Die Cost $2.490 80.8% $2.160 79.3% $1.889 77.7%

MOSFET Die Cost $0.038 1.2% $0.036 1.3% $0.035 1.4%

Alumina DBC cost $0.050 1.6% $0.050 1.8% $0.050 2.1%

Packaging cost $0.395 12.8% $0.392 14.4% $0.389 16.0%

Final test & Calibration cost $0.032 1.0% $0.032 1.2% $0.032 1.3%

Yield losses cost $0.077 2.5% $0.054 2.0% $0.036 1.5%

Component Cost $3.082 100% $2.724 100% $2.431 100%

Low Yield Medium Yield High Yield

UF3C065030K3S | (30 mΩ) - (TO247)

Component Cost

The component cost ranges from $xx to $xx according to yield variations.

The JFET die manufacturing represents xx% of the component cost.

The MOSFET die manufacturing represents xx% of the component cost.

The xx represents xx% of the component cost.

The packaging represents xx% of the component cost.

Final test and yield losses account for xx% of the component cost.




Physical Analysis




Comparison

Related Reports

About System Plus

Packaging Cost – xx




Physical Analysis


Cost Analysis


Comparison

Related Reports

About System Plus

Estimated Manufacturer Price

o The component manufacturing cost ranges from $xx to $xx for the cheapest to $xx to $xx for the most expensive, according toyield variations.

o With a gross margin estimated to xx%, the component selling price ranges from $xx to $xx for the cheapest to $xx to $xx for themost expensive, according to yield variations.



Company Profile & SupplyChain

Physical Analysis


Cost Analysis


ComparisonTechnology & CostComparison:o Cascode JFET Familyo SiC MOSFET vs SiC JFET

Feedbacks

About System Plus

Cascode Family – Cost Comparison




Physical Analysis


Cost Analysis



Feedbacks

About System Plus

Cascode Family – Cost & Price Comparison




Physical Analysis


Cost Analysis



Feedbacks

About System Plus

Cascode Family – Physical and Technological Comparison

Parameter UF3C065030K3S UJ3C065030K3S UJ3C065080K3S UJ3C065080B3

Package type TO-247 TO-247 TO-247 D²PAK

xx layer on xx xx xx xx xx

Resistance xx xx xx xx

xx Die Size xx mm² xx mm² xx mm² xx mm²

Wire bonding xx xx xx xx

Series UF3C UJ3C UJ3C UJ3C

Xx solder xx xx xx xx




Physical Analysis


Cost Analysis



Feedbacks

About System Plus

650V – SiC MOSFET vs SiC Cascode JFET

Manufacturer Year Device CodeSiC

TechnologyPackaging

Vds (V)

Id (A) @

25°C

Rdson(mOh

m)

Qg(nC)

SiC Die Size

(mm²)

Epitaxy (µm)

Pitch (µm)

Wafer Thick (µm)

CurrentDensity

(A/mm²)

FOM (Qg*

Rsdon)

FOM (Rsdon*

Area)

Wafer Cost

SiC Die Cost

Component Cost

$/A cost

Rohm 2013 xxx xx xx 650 xx xx xx xx xx xx xx xx xx xx xx xx xx xxUnitedSiC 2017 UJ3C065080K3S xx xx 650 xx xx xx xx xx xx xx xx xx xx xx xx xx xx

Package Opening – Rohm SiC MOSFET xxx

©2019 by System Plus Consulting

xxxx

xx

Package Opening – UnitedSiC Cascode JFET UJ3C065080K3S


• The co-packaged xx in cascode configuration from UnitedSiC costs xx than the SiC xx from Rohm. Although the 2 componentshave very close xx with the xx, the cascode component seems to have xx since it uses xx than xx from Rohm for a same xx.

• Besides this xx on the xx cost, the xx cost of the cascode (including xx cost) is xx..

• ….




Physical Analysis


Cost Analysis



Feedbacks

About System Plus

650V – SiC MOSFET vs SiC Cascode JFET

MOSFET Die SEM Cross-Section – Rohm SiC MOSFET xxx


JFET Die SEM Cross-Section – UnitedSiC Cascode JFET UJ3C065080K3S





Physical Analysis

Cost Analysis


Comparison

Related Reports

About System Plus

Related Reports

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UnitedSiC Cascode JFET 650V Family - systemplus.fr · This report provides a detailed manufacturing cost analysis of the JFET, the MOSFET and the package as well as the estimated