Unit_01

Chip Synthesis Using Synopsys Design Compiler: The Big Picture 1-131833-000-S35

The primary objective is to give you a quick,hands-on tour of the synthesis process.

Upon completion of this exercise, you will beable to describe the 4 basic steps involved inthe synthesis process. You will gain experiencein navigating through a designs hierarchyusing Design Analyzer, the graphical interfaceto Design Compiler.

This overview contains many forwardreferences; dont dwell on the details now,just proceed through the exercise. This earlyexposure is intended to pique your interest andaid your understanding of these concepts whenyou encounter them again (in much greaterdetail) in the following lectures and labs.

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UNIT Unit 1

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30 min

1-2 Unit 1 Lab Exercise

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In the Unit 1 lecture, the process of synthesis is described as translation plus optimization plusmapping.

In terms of the Synopsys tools, translation is performed by the analyze plus elaborate commandsequence. Optimization and mapping are performed by the compile command. This process isillustrated in the figure below. (Refer to this figure as you run the step-by-step instructions.)

Preliminary Definitions

analyze reads your (V)HDL files, performs syntax and synthesis-policy checks, then writesintermediate files to the directory specified as your design_library.

elaborate reads the intermediate files from your design library and builds the design usinggeneric components.

constrain is not a DC command, but a series of steps you perform to tell Design Compiler whatyour timing and area requirements are.

compile optimizes a design and maps it to real gates from your target_library, producing a circuitthat meets your constraints. The unmapped design in DC memory is overwritten by the new,mapped design.

write

gtech.db

GTECH

my_chip.v(hd)

write

OPTIMIZATION + MAPPING

include

DC_MEMORY

Y=A+BMY_CHIP

TRANSLATION

scripts

constraints.scr

mappedmy_chip.dbmy_chip.edif

compileDC_MEMORY

MY_CHIP

tc6a.db

target_library

readHDL source

unmappedmy_chip.db

read

analyze/elaborate

Synopsys Chip Synthesis Lab Guide 1-3

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8 Log in to the workstation using the appropriate UserID andpassword.

8 Change directories to the project directory Lab_1:

UNIX> cd Lab_1

UNIX> ls -a

This is your top-level directory for the Lab_1 project; notice the file called.synopsys_dc.setup and the various subdirectories. The scripts you will beexecuting in this exercise are stored in the scripts subdirectory.

8 Invoke Design Analyzer from the UNIX prompt:

UNIX> design_analyzer &

8 Open the Design Analyzer command window by clicking themouse through the following menu sequence:

Setup Command Window

The command window enables you to monitor the commands beingexecuted and any messages DC returns.

Resize and relocate the windows so that the Synopsys Design Analyzerwindow covers the top half of your workstation screen.

Resize and move the Command Window covers the next quarter of screenbelow it.

8 analyze the file my_chip.vhd by clicking the mouse through thefollowing menu sequence:

Setup Execute Script scripts/ 1_Analyze_my_chip.scr OK

Wait for the word Done to appear in the bottom left corner of the DesignAnalyzer window, and then look for the return code 1 (one) in thecommand window. These indicate that analyze has completedsuccessfully.

8 elaborate the design MY_CHIP_RTL by clicking the mouse through


the following menu sequence:

Setup Execute Script 2_Elaborate_my_chip.scr OK

You will see an equation icon for MY_CHIP in the Design Analyzerwindow.

The design MY_CHIP is now in Design Compiler memory, representedinternally in Boolean format, and schematically in terms of GTECHcomponents.

8 Push into the Symbol View by double-clicking the mouse on theequation icon.

You will see a block with input and output ports attached to it. This isreferred to as the symbol view of the design, as indicated in the lower rightcorner of the Design Analyzer Window. The symbol view shows theblock diagram of the design.

8 Push into the Schematic View by double-clicking the mouse onthe block in the Symbol View.

Notice that Schematic View is now indicated in the lower right corner ofthe Design Analyzer Window

You will see the structure of your design represented in terms of generictechnology-independent components, located in your Synopsys GTECHlibrary.

Is this structure similar to what you expected from the (V)HDL code?

8 Constrain the design by clicking the mouse through the followingmenu sequence:

Y=A+B

MY_CHIP


Setup Execute Script 3_Constrain_my_chip.scr OK

You will notice that a red square wave symbol has appeared above theClock_In port (the top left port on the design). The script file has declaredthat it will be treated as a clock with period of 100ns (10 MHz). Otherconstraints (operating conditions, input delays, etc) have also been applied.

You will learn how to view and change these constraints soon

8 Compile the design by clicking the mouse through the followingmenu sequence:

Setup Execute Script 4_Compile_my_chip.scr OK

You now see a schematic of your design represented in terms real ofcomponents (cells) from the target technology library.

Does this look like a solution you expected?

8 Save the design by clicking the mouse through the following menusequence:

Setup Execute Script 5_Save_mapped_chip_as_DB.scr

OK

This script saves your design in Synopsys internal (db) format. The nameof the file is my_chip.db. It is saved in the current subdirectory.

8 Run the design report by clicking the mouse through the followingmenu sequence:

Setup Execute Script 6_Report_my_chip.scr OK

This script writes two new reports to the current directory. You could viewthese files from UNIX, but everything contained in them just scrolled by inDesign Analyzers command window.

Look at the last few lines in the command window.

Does the report indicate that the constraints were met or violated?

(Look for the word MET or the word VIOLATED)


Dont worry about the details of the report at this point!

8 Exit Design Analyzer by clicking the mouse through the followingmenu sequence:

File Quit OK

Well done! You have just completed the core of a simple design in lessthan 20 minutes!


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(Youll answer these questions in later labs.)

How would you handle the following last-minute changes to the designsspecification?

1. Counter width increases from two bits to six? The bit width values can be changed by simple modifications to the HDL code.

With careful coding for design reuse, i.e., using parameters in Verilog orgenerics in VHDL, the code doesnt even have to change you can simplyspecify the new generic/parameter values when you elaborate the design.

2. Clock frequency increases to 100 MHz?Change the period of the clock in the constraints file, or simply change theperiod via the Design Analyzer menus.

3. Operating temperature range extends to +125C?

4. Operating voltage drops to 4.5 volts? Change operating conditions via the Design Analyzer menus or in the

constraints file.

5. Up_DownF input arrives 2ns later than before? Change one line in the constraints file and recompile

6. Internal scan and boundary scan circuitry is required? The commands insert_scan and compile -scan insert internal scan circuitry.The insert_jtag command can insert boundary scan cells and synthesize a TAPcontroller and all associated logic.

7. You want to automate this process? You could simply write one script file which includes all of the scripts you

have executed in this lab.

8. You have to switch to a different silicon vendor? Get the library file from your new vendor, install it on your workstation, point

your target_library variable to it, and recompile.


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Unit_01