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Unit V Fault Diagnosis

Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

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Page 1: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Unit V Fault Diagnosis

Page 2: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Syllabus

Logical Level Diagnosis – Diagnosis by UUT

reduction – Fault Diagnosis for Combinational

Circuits – Self-checking design – System Level

Diagnosis.

Page 3: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

©2005 David Lavo

What is Fault Diagnosis?

• A guess as to what’s wrong with a malfunctioning circuit

• Narrows the search for physical root cause• Makes inferences based on observed behavior• Usually based on the logical operation of the

circuit

Page 4: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

VLSI Fault Diagnosis (in One Slide)

TestsObservedBehavior

Defective Circuit

Diagnosis Diagnosis AlgorithmPhysical Analysis

Location or

Fault

Page 5: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

©2005 David Lavo

Two Types of Diagnosis

• Circuit Partitioning (“Effect-Cause” Diagnosis)– Identify fault-free or possibly-faulty portions– Identify suspect components, logic blocks,

interconnects• Model-Based Diagnosis (“Cause-Effect”

Diagnosis)– Assume one or more specific fault models– Compare behavior to fault simulations

Page 6: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

©2005 David Lavo

Circuit Partitioning

• Separate known-good portions of circuit from likely areas of failure

• Simplest method: identify failing flip-flops– Tester can identify failing flops or outputs– Input cone of logic is suspect– Intersection of multiple cones is highly suspect– Single clock pulse with scan can be used for

sequential/functional fails

Page 7: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Back-Tracing Failures

Page 8: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

©2005 David Lavo

Effect-Cause Diagnosis

• Reasoning based on observed behavior and expected (good-circuit) functions

• Commonly used at system and board-levels• Tries to separate good and suspect areas• Advantage: Simple and general• Disadvantage: Not very precise, often gives no

indication of defect mechanism

Page 9: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

©2005 David Lavo

Cause-Effect Diagnosis

• Start from possible causes (fault models), compare to observed effects

• A simulator is used to predict behavior of the circuit in the presence of various faults

• Match prediction(s) against observed behavior• Advantage: Implicates a mechanism as well as a

location• Disadvantage: Can be fooled by unmodeled

defects

Page 10: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Tests

Defective Circuit

Fault Simulator

010001010100010101010 …

Behavior Signature

010100110000101010100 …

101000100001011101100 …

010100010100011101100 …

000111000101010011110 …

Candidate Signatures

Diagnosis Algorithm

Comparison & Conclusion

Cause-Effect Diagnosis

Page 11: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

11©2005 David Lavo Fault Diagnosis Overview

Fault Dictionaries

• A fault dictionary is a database of the simulated responses for all faults in faultlist

• Used by some diagnosis algorithms for convenience:– Fast: no simulation at time of diagnosis– Self-contained: netlist, simulator, and test set

not needed after dictionary creation• Can be very large, however!

Page 12: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Diagnosis by UUT Reduction

Page 13: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-Checking Circuits

• Most important factors in designing a digital system: Speed, Cost and Correctness.• Some systems used in

1. medical equipment used in ICUs, 2. aircraft control systems, 3. nuclear reactor control systems, 4. military systems and 5. computing systems used in space missions.

• High reliability is of the utmost importance.• DSM technology: Signal Integrity problem

Page 14: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-Checking Circuits:

• Def: Error An incorrect output caused by a stuck-at fault.

• Def: Single Error An error that affects only a single component value

• Def: Multiple Error An error that affects multiple component values.

• The component value affected by an error may change form 0 to 1, or vice versa.•Def: unidirectional errors When all components affected by a multiple error change their values monotonically.

Page 15: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-Checking Circuit

Page 16: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-checking scheme

• Self-Checking scheme:1. a self-checking functional unit.2. a self-checking checker.

Self-Checkingfunctional unit

Self-checkingchecker

... ... ...

...

InputsX

OutputsY

Error signal

X: input code spaceY: output code space

Page 17: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-Checking Circuits

• During the fault-free operation: a normal input will produce a normal output.• If an incorrect output is produced due to a fault, the error should be detected by the self-checking checker.

Page 18: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-checking scheme

• Totally self-checking circuit:1. no erroneous results go undetected and 2. any fault will be eventually detected.

• Partially self-checking circuits:1. This approach is to restrict the set of faults for which the circuit has to be checked. 2. They are introduced to provide low-cost error detection.3. They may be used in non-critical applications.

Page 19: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-Checking Checkers

. , and ,

if only and if called iscircuit A

Y)F(x, XxY)F(x, Xx

intdisjocode

• Code-disjoint:

• TSC Checker:

. torespect withdisjoint -code

and secure-fault testing,-self isit if only and if

torespect withchecker TSC a called iscircuit A

Φ

Φ

With the code-disjoint feature, one may be able to test if the TSC checker is malfunction.

Page 20: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-checking scheme

X}x)|{F(x,Y

),x(F

.)F(x,

Xx

Φ:Φ

Φ

words) codeoutput the (all space codeOutput 5.

. :function free-fault a 4.

: and fault containing function a 3.

: infault a 2.

:faults phsical ofset the 1.

Page 21: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-checking scheme

• Fault Secure(FS): code word input to a faulty circuit must not produce an incorrect code word output.• Self-testing: a fault in a circuit must be detected by some input.

Page 22: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-checking scheme

• Fault Secure(FS):

• Self-testing:

.or ,

if only and if

torespect with called iscircuit A

) F(x, ) F(x, Y)F(x, XxΦ

Φuresecfault-

. ,

if only and if

torespect with called iscircuit A

Y)F(x, XxΦ

Φngself-testi

Page 23: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-checking scheme

• Totally Self-Checking:

• Partially Self-Checking:

. torespect with and isit if only and if

torespect with (TSC) called iscircuit A

Φuresecfault-ngself-testi

Φ glf-checkintotally se

.subset afor and for isit

if only and if

torespect with called iscircuit A

XIuresecfault-Xngself-testi

Φingself-checkpartially

Page 24: Unit V Fault Diagnosis. Syllabus Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design

Self-checking scheme

• Fault-secure-only circuits:1. No erroneous results go undetected.2. However, it is possible that some fault can never be detected.

• Self-testing-only circuit: 1. Any fault can produce undetected errors for a short time. 2. However, there is a code word input that can detect the fault.