UNIT - IV€¦ · UNIT - IV Sequential Circuits P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) 1 VIDYA SAGAR P. Department of Electronics and Communication Engineering, VBIT Sequential logic

Department of Electronics and Communication Engineering, VBIT

UNIT - IVSequential Circuits

P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)

VIDYA SAGAR P1

Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT

Sequential logic circuits

The main characteristic of combinational logic circuits is that their output values depend on their

present input values.

Sequential logic circuits differ from combinational logic circuits because they contain memory

elements so that their output values depend on both present and past input values

Sequential circuits can be Asynchronous or synchronous.

Asynchronous sequential circuits change their states and output values whenever a change in

input values occurs.

Synchronous sequential circuits change their states and output values at fixed points of time,

i.e. clock signals.

VIDYA SAGAR P2


Sequential Circuit Models

Universal model

VIDYA SAGAR P3


Sequential Circuits

Combinational

CircuitMemory

Elements

Inputs Outputs

Asynchronous

Combinational

Circuit

Flip-flops

Inputs Outputs

Clock

Synchronous

VIDYA SAGAR P4


S-R latch operation

S

R

QN

Q

0

0

0=

=1

S

R

QN

Q

1

00=

=0

=1

0=S

R

QN

Q

0

0 =1

=0

=1

S

R

QN

Q

0

1 =1

=1

=0

VIDYA SAGAR P5


Latches

SR Latch

R

S

Q

Q

• If S = 1 (Set), Q+ = 1

• If R = 1 (Reset), Q+ = 0

• If S = R = 0, Q+ = Q (no change)

• S = R = 1 is not allowed.

Present

value

Next

value

VIDYA SAGAR P6


Latches

SR Latch

R

S

Q

Q

S R Q

0 0 Q0

0 1 0

1 0 1

1 1 Q=Q’=0

No change

Reset

Set

Invalid

S’ R’ Q

0 0 Q=Q’=1

0 1 1

1 0 0

1 1 Q0

Invalid

Set

Reset

No change

S

R

Q

Q

VIDYA SAGAR P7


Controlled Latches Or Gated Latch

SR Latch with Control Input

C S R Q

0 x x Q0

1 0 0 Q0

1 0 1 0

1 1 0 1

1 1 1 Q=Q’

No change

No change

Reset

Set

Invalid

S

R

Q

Q

S

R

C

S

RQ

QS

R

C

VIDYA SAGAR P8


Controlled Latches

D Latch (D = Data)

C D Q

0 x Q0

1 0 0

1 1 1

No change

Reset

Set

C

Timing Diagram

D

Q

t

Output may

change

VIDYA SAGAR P9


Controlled Latches

D Latch (D = Data)

C D Q

0 x Q0

1 0 0

1 1 1

No change

Reset

Set

C

Timing Diagram

D

Q

Output may

change

S

R

Q

Q

D

C

VIDYA SAGAR P10


Flip-Flops

Controlled latches are level-triggered

Flip-Flops are edge-triggered

C

CLK Positive Edge

CLK Negative Edge

VIDYA SAGAR P11

Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT VIDYA SAGAR P12

CLK

D

Qlatch

CLK

D

Q

Latch Vs Flip-Flops


Flip-Flops

Master-Slave D Flip-Flop

D Latch(Master)

D

C

QD Latch(Slave)

D

C

Q QD

CLK

CLK

D

QMaster

QSlave

Looks like it is negative

edge-triggered

Master Slave

VIDYA SAGAR P13


Flip-Flops

Edge-Triggered D Flip-Flop

D

CLK

Q

Q

D Q

Q

D Q

Q

Positive Edge

Negative Edge

VIDYA SAGAR P14


Flip-Flops

JK Flip-Flop

D Q

Q

Q

QCLK

J

K

J Q

QK

D = JQ’ + K’Q

VIDYA SAGAR P15


Flip-Flops

T Flip-Flop

D = TQ’ + T’Q = T Q

J Q

QK

T D Q

Q

T

D = JQ’ + K’QT Q

Q

VIDYA SAGAR P16


Flip-Flop Characteristic Tables

D Q

Q

D Q(t+1)

0 0

1 1

Reset

Set

J K Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q’(t)

No change

Reset

Set

Toggle

J Q

QK

T Q

Q

T Q(t+1)

0 Q(t)

1 Q’(t)

No change

ToggleVIDYA SAGAR P17


Flip-Flop Characteristic Equations

D Q

Q

D Q(t+1)

0 0

1 1Q(t+1) = D

J K Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q’(t)

Q(t+1) = JQ’ + K’Q

J Q

QK

T Q

Q

T Q(t+1)

0 Q(t)

1 Q’(t)Q(t+1) = T Q

VIDYA SAGAR P18



Analysis / Derivation

J Q

QK

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

No change

Reset

Set

Toggle

VIDYA SAGAR P19




J Q

QK

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0

1 0 1

1 1 0

1 1 1

No change

Reset

Set

Toggle

VIDYA SAGAR P20




J Q

QK

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0

1 1 1

No change

Reset

Set

Toggle

VIDYA SAGAR P21




J Q

QK

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

No change

Reset

Set

Toggle

VIDYA SAGAR P22




J Q

QK

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

K

0 1 0 0

J 1 1 0 1

Q

Q(t+1) = JQ’ + K’Q

VIDYA SAGAR P23



Flip-Flop Applications

Parallel Data Storage

Frequency Division

Counting

VIDYA SAGAR P25


Registers.

Shift Registers:

Serial in, serial out shift register

Serial in, parallel out shift register

Parallel in, serial out shift register

Parallel in, parallel out shift register

Shift Register Applications

Counters:

Ripple Counters

Synchronous Counters

Counter Applications

Registers & Counters

VIDYA SAGAR P26


Shift Registers

Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle)

Shift Left is towards MSB

0 1 1 1 LSI

Q3 Q2 Q1 Q0

1 1 1 LSI

Q3 Q2 Q1 Q0

RSI 0 1 1 1

Q3 Q2 Q1 Q0

RSI 0 1 1

Q3 Q2 Q1 Q0

– Shift Right (or Shift Up) is towards MSB

VIDYA SAGAR P27


Serial In, Serial Out Shift Register

D Q

CLK

D Q

CLK

D Q

CLK

SERIN

CLOCK

SEROUT

For a n-bit SRG:Serial Out = Serial In delayed by n clock period

4-bit shift register example:serin: 1 0 1 1 0 0 1 1 1 0serout: - - - - 1 0 1 1 0 0clock:

SRG n>SI SO

VIDYA SAGAR P28


Serial In, Parallel Out Shift register

D Q

CLK

D Q

CLK

D Q

CLK

SERIN

CLOCK

nQ

2Q

1Q

Serial to Parallel Converter

4-bit shift register example:serin: 1 0 1 1 0 0 1 1 1 01Q: - 1 0 1 1 0 0 1 1 12Q: - - 1 0 1 1 0 0 1 13Q: - - - 1 0 1 1 0 0 14Q: - - - - 1 0 1 1 0 0clock:

SRG n>SI 1Q

2Q

nQ (SO)

VIDYA SAGAR P29


Parallel In, Serial Out Shift Register

SERIN

CLOCK

D Q

CLK

D Q

CLK

D Q

CLK

SEROUT

LOAD/SHIFT

1D

2D

ND

S

L

S

L

S

L

1Q

2Q

NQ

Parallel to Serial Converter

Load/Shift=1Di Qi

Load/Shift=0 Qi Qi+1

VIDYA SAGAR P30


Parallel In, Parallel Out Shift Register

SERIN

CLOCK

D Q

CLK

D Q

CLK

D Q

CLK

LOAD/SHIFT

1D

2D

ND

1Q

2Q

NQ

S

L

S

L

S

L

General Purpose:Makes any kind of (left) shift register

VIDYA SAGAR P31

Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P32


Types of counters

Counters are classified according to the way they are clocked:

Synchronous Counter :

Common clock is connected to all of the f/f’s and thus they are clocked simultaneously.

Asynchronous Counter (Ripple Counter):

The first flip-flop is clocked by the external clock pulse and then each successive flip-flop is

clocked by the output of the preceding f/f.

a counter is a device which stores (and sometimes displays) the number of times a

particular event or process has occurred, often in relationship to a clock signal.

VIDYA SAGAR P33

COUNTERS


Synchronous Counters

Binary Up Counters

A synchronous binary counter counts from 0 to 2N-1, where N is the number of bits/flip-flops in the

counter. Each flip-flop is used to represent one bit. The flip-flop in the lowest-order position is

complemented/toggled with every clock pulse and a flip-flop in any other position is complemented

on the next clock pulse provided all the bits in the lower-order positions are equal to 1.


In a binary up counter, a particular bit, except for the first bit, toggles if all the lower-order bits

are 1's. The opposite is true for binary down counters. That is, a particular bit toggles if all the

lower-order bits are 0's and the first bit toggles on every pulse.

Binary Down Counters


Binary Up/Down Counters :

VIDYA SAGAR P36

Binary Counter with Parallel Load:


Ring Counters,Johnson/Twisted-Ring Counters :

VIDYA SAGAR P37


Binary Ripple Counter

A binary ripple counter is an asynchronous counter where only the first flip-flop is clocked by

an external clock. Each subsequent flip-flop is triggered by the transition occurring in the

preceding flip-flop.

VIDYA SAGAR P38


BCD Ripple Counter

VIDYA SAGAR P39


Analysis of Sequential Circuits

• Analysis is describing what a given circuit will do

• The behavior of a clocked (synchronous) sequential circuit is determined from the inputs, the

output, and the states of FF

Steps:

• Obtain state equations

• FF input equations

• Output equations

• Fill the state table

• Put all combinations of inputs and current states

• Fill the next state and output

• Draw the state diagram

VIDYA SAGAR P40


Analysis of Combinational vs Sequential Circuits

–Combinational :

•Boolean Equations

•Truth Table

•Output as a function of

inputs

–Sequential :

•State Equations

•State Table

•State Diagram

•Output as a function of input and current state

•Next state as a function of inputs and current state.

VIDYA SAGAR P41


State Equations

–A state equation is a Boolean expression which specifies the next state and output as a function of the present state and inputs.

–Example:

•The shown circuit has two D-FFs (A,B), an input x and output y.

•The D input of a FF determines the next state

•A(t+1) = A(t)x+B(t)x = Ax+Bx

•B(t+1) = A’(t)x = A’x

•Output:

•y = (A+B)x’

VIDYA SAGAR P42


State Table

–A state table is a table enumerating all present

states, inputs, next states and outputs.

•Present state, inputs: list all combinations

•Next states, outputs: derived from state equations

4 sections

VIDYA SAGAR P43


State Table

2-D Form

–A state table is a table enumerating all present

states, inputs, next states and outputs.

•Present state, inputs: list all combinations

•Next states, outputs: derived from state equations

VIDYA SAGAR P44


State Diagram

• The state diagram is a graphical representation of a state table (provides same information)

• Circles are states (FFs), Arrows are transitions between states

• Labels of arrows represent inputs and outputs

VIDYA SAGAR P45


Analysis of Sequential Circuits

• Analysis is describing what a given circuit will do

• The behavior of a clocked (synchronous) sequential circuit is determined from the inputs, the

output, and the states of FF

Steps:

• Obtain state equations

• FF input equations

• Output equations

• Fill the state table

• Put all combinations of inputs and current states

• Fill the next state and output

• Draw the state diagram

VIDYA SAGAR P46


Example 1

Analyze this circuit?

• Is this a sequential circuit? Why?

• How many inputs?

• How many outputs?

• How many states?

• What type of memory?

VIDYA SAGAR P47


Example 1 (cont.)

Q(t) D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1

D Q(t+1)

0 0

1 1

Q(t+1) = D

Characteristic Tables and Equations

D Flip Flop (review)

VIDYA SAGAR P48


Example 1 (cont.)

VIDYA SAGAR P49


Example 1 (cont.)

State equations:

DA = AX + BX

DB = A’ X

Y = (A + B) X’

VIDYA SAGAR P50


Example 1 (cont.)

State equations:

DA = AX + BX

DB = A’ X

Y = (A + B) X’

State table:

VIDYA SAGAR P51


Example 1 (cont.)

State equations:

DA = AX + BX

DB = A’ X

Y = (A + B) X’

State table (2D):

VIDYA SAGAR P52


Example 1 (cont.)

State equations:

DA = AX + BX

DB = A’ X

Y = (A + B) X’

State table:

State diagram:

VIDYA SAGAR P53


Example 2

• Analyze this circuit.

• What about the output?

• This circuit is an example of a Moore machine (output depends only on current state)

• Mealy machines is the other type (output depends on inputs and current states)

VIDYA SAGAR P54


Example 2 (cont.)

Equation:

DA = A X Y

VIDYA SAGAR P55


Example 2 (cont.)

Equation:

DA = A X Y

VIDYA SAGAR P56


Example 3


• Is this a sequential circuit?

Why?





VIDYA SAGAR P57


Example 3 (cont.)

State equations:

JA = B, KA = B X’

JB = X’, KB = A X

by substitution:

A = JAA’ + KA’A

= A’ B + A B’ + A X

B = B’ X’ + A B X + A’ B X’

VIDYA SAGAR P58


Example 3 (cont.)

State equations:

JA = B, KA = B X’

JB = X’, KB = A X

by substitution:

A = JAA’ + KA’A

= A’ B + A B’ + A X

B = B’ X’ + A B X + A’ B X’

VIDYA SAGAR P59


Example 3 (cont.)

State equations:

JA = B, KA = B X’

JB = X’, KB = A X

by substitution:

A = JAA’ + KA’A

= A’ B + A B’ + A X

B = B’ X’ + A B X + A’ B X’

VIDYA SAGAR P60


Example 4


• Is this a sequential

circuit? Why?





VIDYA SAGAR P61


Example 4 (cont.)

State equations:

JA = BX’

KA = BX’ + B’X

DB = X

Y = X’AB

by substitution:

A(t+1) = JAA’ + KA’A

VIDYA SAGAR P62


Example 4 (cont.)

Current State Input Next State Output

A(t) B(t) X A(t+1) B(t+1) Y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 1 0 0

0 1 1 0 1 0

1 0 0 0 0 0

1 0 1 1 1 0

1 1 0 1 0 1

1 1 1 0 1 0

State equations:

JA = BX’

KA = BX’ + B’X

DB = X

Y = X’AB

by substitution:

A(t+1) = JAA’ + KA’A

VIDYA SAGAR P63


Example 5


• Is this a sequential circuit?

Why?





VIDYA SAGAR P64


Example 5 (cont.)

State equations:

TA = BX

TB = X

Y = AB

by substitution:

A(t+1) = TAA’ + TA’A

VIDYA SAGAR P65


Example 5 (cont.)

State equations:

TA = BX

TB = X

Y = AB

by substitution:


VIDYA SAGAR P66


Example 5 (cont.)

State equations:

TA = BX

TB = X

Y = AB

by substitution:


The output depends only on current state.

This is a Moore machine

VIDYA SAGAR P67


Mealy vs Moore Finite State Machine (FSM)

–Mealy FSM:

• Output depends on current state and input

• Output is not synchronized with the clock

–Moore FSM:

• Output depends on current state only

VIDYA SAGAR P68


Asynchronous Sequential Circuits

Asynchronous sequential circuits basics

No clock signal is required

Internal states can change at any instant of time when there is a change in the input

variables

Have better performance but hard to design due to timing problems

Why Asynchronous Circuits?

Accelerate the speed of the machine (no need to wait for the next clock pulse).

Simplify the circuit in the small independent gates.

Necessary when having multi circuits each having its own clock.

Analysis Procedure

The analysis consists of obtaining a table or a diagram that describes the sequence of

internal states and outputs as a function of changes in the input variables.

VIDYA SAGAR P69


Transition Table

Transition table is useful to analyze an asynchronous circuit from the circuit

diagram. Procedure to obtain transition table:

1. Determine all feedback loops in the circuits

2. Mark the input (yi) and output (Yi) of each feedback loop

3. Derive the Boolean functions of all Y’s

4. Plot each Y function in a map and combine all maps into one table (flow table)

5. Circle those values of Y in each square that are equal to the value of y in the same row

VIDYA SAGAR P70


Asynchronous Sequential Circuit

The excitation variables: Y1 and Y2

Y1 = xy1+ xy2

Y2 = xy1 + xy2

CUT

CUT

VIDYA SAGAR P71


Transition Table

Combine the internal state with

input variables

Stable total states:

y1y2x = 000, 011, 110 and 101

VIDYA SAGAR P72


Transition Table

In an asynchronous sequential circuit, the internal

state can change immediately after a change in the

input.

It is sometimes convenient to combine the internal

state with input value together and call it the Total

State of the circuit. (Total state = Internal state +

Inputs)

In the example , the circuit has

4 stable total states: (y1y2x= 000, 011, 110, and 101)

4 unstable total states: (y1y2x= 001, 010, 111, and 100)

VIDYA SAGAR P73


Transition Table

If y=00 and x=0 Y=00 (Stable state)

If x changes from 0 to 1 while y=00, the circuit

changes Y to 01 which is temporary unstable

condition (Yy)

As soon as the signal propagates to make Y=01,

the feedback path causes a change in y to 01.

(transition form the first row to the second row)

If the input alternates between 0 and 1, the

circuit will repeat the sequence of states

VIDYA SAGAR P74


Flow Table

A flow table is similar to a transition table except that the internal state are

symbolized with letters rather than binary numbers.

It also includes the output values of the circuit for each stable state.

VIDYA SAGAR P75


Flow Table

In order to obtain the circuit

described by a flow table, it is

necessary to convert the flow table

into a transition table from which we

can derive the logic diagram.

This can be done through the

assignment of a distinct binary value

to each state.

VIDYA SAGAR P76


Race condition Two or more binary state variables will change value when one input variable changes.

Cannot predict state sequence if unequal delay is encountered.

Non-critical race: The final stable state does not depend on the change order of state

variables

Critical race: The change order of state variables will result in different stable states. Must

be avoided !!

VIDYA SAGAR P77


Race Solution

It can be solved by making a proper binary assignment to the state variables.

The state variables must be assigned binary numbers in such a way that only one state

variable can change at any one time when a state transition occurs in the flow table.

VIDYA SAGAR P78


Latches in Asynchronous Circuits

The traditional configuration of asynchronous circuits is using one or more feedback loops

No real delay elements.

It is more convenient to employ the SR latch as a memory element in asynchronous circuits

Produce an orderly pattern in the logic diagram with the memory elements clearly visible.

SR latch is an asynchronous circuit

So will be analyzed first using the method for asynchronous circuits.

VIDYA SAGAR P79


SR Latch with NOR Gates

VIDYA SAGAR P80


SR Latch with NOR Gates

S=1, R=1 (SR = 1)

should not be

used

⇒ SR = 0 is

normal mode

should be

carefully

checked first

VIDYA SAGAR P81


SR Latch with NAND Gates

S=0, R=0 (S+R=0) should not be

used ⇒ S+R=1 is normal mode

(eq. S’R’=0)

should be carefully

checked first, so it is obtained

Y = S’ + Ry

VIDYA SAGAR P82

Documents

UNIT - IV€¦ · UNIT - IV Sequential Circuits P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) 1 VIDYA SAGAR P. Department of Electronics and Communication Engineering, VBIT Sequential logic