Unit 3

• The syllabus for mid sem will be Unit 1 & Unit 3.• There will be 5 to 6 questions from unit 1 and 2 to 3

questions from unit 2.• Unit 3 questions will be theoretical ones.

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Unit 3Interfacing Devices


L1Interfacing & Data Transfer

Schemes

Introduction

• Memories and input output devices are interfaced to microprocessor to form a microcomputer. In a microprocessor-based system the designer has to select suitable memories and input /output devices for his task and interface them to the microprocessor.

• The selected I/O and memory devices should be compatible with the microprocessor. If a particular device is not compatible, an additional electronic circuit has to be designed through which the device may be interfaced to the CPU.


Address Space Partitioning The Intel8085 has 16 bit wide address bus thus it can address 216 =64k

bytes of memory and I/O devices. The 64K addresses are to be assigned to memory and I/O devices for their addressing. There are two schemes for allocation of addresses to memories and input /output devices.

1.Memory Mapped I/O scheme 2.I/O mapped I/O scheme 1.Memory Mapped I/O scheme In memory mapped I/O scheme there is

only one address space. Address space is defined as the set of possible addresses microprocessor can generate. Some addresses are assigned to memories and some to I/O devices. An I/O device is also treated as memory location and one address is assigned to it. Suppose the memory

location is assigned the addresses 2000 to 24FF.One address is assigned to each memory location. Any of these addresses cannot be assigned to

I/O device. I/O devices may be assigned other addresses, such as 2500, 2501 ,2502 can be assigned to different I/O devices.


Address Space Partitioning 1.Memory Mapped I/O scheme(cntd) In this scheme all data transfer

instructions of the microprocessor can be used for both memory as well as I/O devices.The memory mapped I/O scheme is suitable for a small system.

2.I/O mapped I/O scheme In this scheme addresses assigned to memory locations can also be assigned to I/O devices, microprocessor issues a signal to distinguish whether the address on the address bus

is for a memory location or I/O device.The Intel 8085 issues an IO/M9 signal for this purpose .When this signal is high the address on the address bus is for an I/O device. When this is low then the address is for memory location. Instructions IN and OUT are used for addressing I/O devices. This scheme is suitable for large systems. – 8085 has a separate 8-bt addressing scheme for I/O devices – I/O address space: 00H to FFH


Data Transfer Schemes• In a microprocessor based system data transfer takes place between

two Devices such as microprocessor and memory, microprocessor and I/O devices, and memory and I/O devices. Usually semiconductor memories are compatible with microprocessor because the same technology is employed in manufacturing of the both. Hence there is less problem associated with interfacing of memory.

• A wide variety of I/O devices having wide range of speed and other different characteristics are available. A microprocessor based system may have several I/O devices of different speed. To solve the problem of speed mismatch between a microprocessor and I/O devices a number of data transfer techniques have been developed ,which can be classified into two broad categories.


Data Transfer Schemes1 Programmed Data Transfer schemes2 DMA data transfer schemes1 Programmed Data Transfer schemesProgrammed data transfer schemes are controlled by the CPU. In this

scheme, data transfer takes place under the control of a program residing in the main memory. So microprocessor executes a program to perform all data transfers between the memory and I/O devices through the CPU.This data transfer takes place under the control microprocessor. programmed data transfer is slow and suitable for small data. The programmed data transfer schemes are classified into the following three categories.

1.1Synchronous data transfer scheme1.2Asynchronous data transfer scheme1.3Interrupt driven data transfer scheme

Data Transfer Schemes1.1Synchronous data transfer scheme Synchronous means at the same time. The device which sends data and the device which receives data are synchronized with the same clock. In this scheme, timing characteristics of I/O device are precisely known. microprocessor always consider the I/O device to ready for data transfer. The I/O devices compatible with the microprocessor in speed are usually not available. Hence this technique of data transfer is rarely used for I/O devices. However memories compatible with microprocessor are available, and therefore this technique is invariably used for compatible Memory devices.1.2Asynchronous data transfer scheme Asynchronous means at irregular intervals. In

this scheme data transfer between external device and microprocessor occurs via handshaking process.

Data Transfer Schemes1.2Asynchronous data transfer scheme(cntd) In this mode of data transfer some

signals are exchanged between I/O device and microprocessor before the actual data transfer takes place. One example is interfacing of A/D converter with the microprocessor.

1.3Interrupt driven data transfer scheme In this scheme, microprocessor initates data transfer by requesting the device to get ready and then it executes its main program instead of wasting its time by continuously checking the status of input /output device. Whenever device is ready to accept or supply data, it informs microprocessor through a special interrupt line. It is an efficient technique as compared to asynchronous data transfer scheme because precious time of the microprocessor is not wasted in waiting while an I/O device is getting ready.

Data Transfer Schemes2 DMA data transfer schemes In DMA data transfer scheme CPU does not participate. Data is directly

transferred from the memory to an I/O device or vice versa.Data transfer is controlled by an I/O device or a DMA controller. This scheme is employed when large amount of data are to be transferred. If bulk data are transferred through CPU, it takes

an appreciable time and the process becomes slow.DMA data transfer scheme is faster as compared to programmed data transfer scheme.

DMA data transfer scheme is of two types:2.1Burst mode of DMA data transfer2.2Cycle stealing techniques of DMA data transfer 2.1Burst mode of DMA data transfer A scheme of DMA data transfer, in which the I/O device

withdraws the DMA request only after all data bytes have been transferred. By this technique a block of data is transferred.

Data Transfer Schemes2.2Cycle stealing techniques of DMA data transfer In this technique a Long block of data is transferred by a sequence of DMA

cycles. In this Method after transferring one byte or several bytes the I/O device Withdraws DMA request. This method reduces interference in CPU Activities. The interference can be eliminated completely by designing an interfacing circuitry which can steal the bus cycle for DMA data transfer only when the CPU is not using the system bus.

L28255


8255 PPIThe 8255 is a widely used ,programmable, parallel I/O device. It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O.Block Diagram/Pin Diagram Data Bus Buffer: It is an 8 bit data buffer used to interface 8255 with 8085. It is connected to D0-D7 bits of 8255.Read/write control logic: It consists of inputs R9D9,W9R9,A0 ,A1 ,C9S,FRESET.

R9D9(Read) This control signal enables the read operation. When the signal is low, the MPU reads data from a selected I/O port of the 8255. W9R9 (Write) This control signal enables the write operation. When the signal goes low, the MPU writes into a selected I/O port or the control register of the 8255.

8255 PPIRESET(Reset) This is an active high signal; it clears the control register and sets all ports in the input mode.A0 ,A1 ,C9S9 A0,A1 are Port select signals used to select the particular port

C9S9 is used to select the 8255 device .C9S9 A1C9S9 A1 A0A0 Selected portSelected port0 00 0 00 Port APort A0 00 0 11 Port BPort B0 10 1 00 Port CPort C0 10 1 11 Control RegisterControl Register11 X X 8255 is not selectedX X 8255 is not selectedGroup A and Group B Control Group A control consists of Port A and Port C upper. Group B control consists of Port B and Port C lower. Each group is controlled through software.

8255 PPIPORT A,B: These are bi-directional 8 bit ports each and are used to

interface 8255 with microprocessor or peripherals.

PORT C: This is a bi-directional 8 bit port controlled partially by Group A control and partially by Group B control .

• It is divided into two parts Port C upper and Port C lower each of a nibble.

• It is used mainly for control signals and interfacing with peripherals.

8255 PPI pin diagramPA0-PA7 PA0-PA7 I/O I/O Port A PinsPort A PinsPB0-PB7PB0-PB7 I/OI/O Port B PinsPort B PinsPC0-PC7PC0-PC7 I/O I/O Port C PinsPort C PinsD0-D7D0-D7 I/OI/O Data PinsData PinsRESETRESET II Reset pin Reset pin R9D9 IR9D9 I Read inputRead inputW9R9 W9R9 I I Write inputWrite inputA0-A1A0-A1 II Address pinsAddress pinsC9S F C9S F II Chip selectChip selectVcc , GndIVcc , GndI +5 volt supply, Gnd+5 volt supply, Gnd

8255 PPI Block diagram

Control Word D7 D6 D5 D4 D3 D2 D1 D0

0 / 1

B S R Mode I/O Mode

(Bit Set/Reset) Mode 0 Mode1 Mode 2For Port C -Simple I/O -Handshake I/O -Bidirectional No effect on for ports for ports A data bus forI/O Mode A,B,C and/or B port A -Port C bits -Port B:either

are used for in Mode 0 or 1 handshake -Port C bits are used for handshake


Control Word

• Previous slide shows a register called the control Register. The contents of this register, called the control word, specify an I/O function for each port. This register can be accessed to write a control word when A0 and A1 are at logic 1.This register is not accessible for a Read operation.

• If bit D7 =1,Bits D6- D0 determine I/O functions in various modes.

• If bit D7 =0, Port C operates in the Bit Set/Reset(BSR) mode.

• BSR Control word does not affect the functions of ports A and B.Group A consists of port cupper and port A

Group B consists of port clower and port B


I/0 Mode Control Word


Control Word D7 D6 D5 D4 D3 D2 D1 D0 1(1=I/O) GA mode select PA PCU GB mode select PB PCL I/O I/O I/O I/OD6, D5: GA mode select: – 00 = mode0– 01 = mode1– 1X = mode2

D4(PA), D3(PCU), D1(PB), D0(PCL): : 1=input 0=output

D2: GB mode select: 0=mode0, 1=mode1

BSR Control Word


D7 D6 D5 D4 D3 D2 D1 D0 0 (0=BSR) X X X B2 B1 B0 S/R (1=S,0=R)(Taking Don't care's as 0)• B2 B1 B0 PC bit Control word (Set) Control word (reset)• 0 0 0 0 0000 0001 = 01h 0000 0000 = 00h • 0 0 1 1 0000 0011 = 03h 0000 0010 = 02h• 0 1 0 2 0000 0101 = 05h 0000 0100 = 04h • 0 1 1 3 0000 0111 = 07h 0000 0110 = 06h • 1 0 0 4 0000 1001 = 09h 0000 1000 = 08h• 1 0 1 5 0000 1011 = 0Bh 0000 1010 = 0Ah • 1 1 0 6 0000 1101 = 0Dh 0000 1100 = 0Ch• 1 1 1 7 0000 1111 = 0Fh 0000 1110 = 0Eh

BSR Control WordThe BSR Control word is concerned with the 8 bits of port C,

which can be set or reset by writing an appropriate control word in the control register.


L38253/8254


8254• The 8254 is a programmable interval timer/counter designed for use

with Intel microcomputer systems.• The 8254 solves one of the most common problems in any

microcomputer system, the generation of accurate time delays under software control.

• Instead of setting up timing loops in software, the programmer configures the 8254 to match his requirements and programs one of

the counters for the desired delay.• Some of the other counter/timer functions which can be

implemented with the 8254 are: Real time clock, Event-counter, Digital one-shot, Programmable rate

generator, Square wave generator, Complex waveform generator, Complex motor controller


8254 Block Diagram


Pin Diagram


8254 Pin discription

8254 Block Diagram• DATA BUS BUFFER This 3-state, bi-directional, 8-bit buffer is used to

interface the 8254 to the system bus.• READ/WRITE LOGIC The Read/Write Logic accepts inputs from the

system bus and generates control signals for the other functional blocks of the 8254.

• A1 and A0 select one of the three counters or the Control Word Register to be read from/written into.

• A ``low'' on the R9D9 input tells the 8254 that the CPU is reading one of the counters.

• A ``low'' on the W9R9 input tells the 8254 that the CPU is writing either a Control Word or an initial count.

• R9D9 and W9R9 are ignored unless the 8254 has been selected by holding C9S9 low.

8254 Block Diagram• CONTROL WORD REGISTER The Control Word Register is selected by

the Read/Write Logic when A1,A0 is 11. If the CPU then does a write operation to the 8254, the data is stored in the Control Word Register and is interpreted as a Control Word. Control Word used to define the

operation of the Counters.• COUNTER 0, COUNTER 1, COUNTER 2These three functional blocks

are identical in operation. The Counters are fully independent. Each Counter may operate in a different Mode.

8254 Operational Description• After power-up, the state of the 8254 is undefined. The Mode, count

value, and output of all Counters are undefined.How each Counter operates is determined when it is programmed. Each Counter must be programmed before it can be used. Unused counters need not be

programmed.• Programming the 8254 Counters are programmed by writing a

Control Word and then an initial count. The Control Words are written into the Control Word Register, which is selected when A1,A0 are 11. The Control Word itself specifies which Counter is being

programmed. By contrast, initial counts are written into the Counters, not the Control Word Register. The A1,A0 inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used.

8254 Operational Description• Write Operations 1) For each Counter, the Control Word must be written before the initial

count is written.2) The initial count must follow the count format specified in the Control

Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte).

• Read Operations• It is often desirable to read the value of a Counter without disturbing

the count in progress. This is easily done in the 8254.• There are three possible methods for reading the counters:– A simple read operation– Counter Latch Command– Read-Back Command

8254 Control Word Format

Simple read operation1.Simple read operation To read the Counter, which is selected with the A1, A0 inputs,

the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in the process of changing when it is read, giving an undefined result.

2.Counter Latch Command • Like a Control Word, this command is written to the Control

Word Register, which is selected when A1,A0 is 11.• Also like a Control Word, the SC0, SC1 bits select one of the

three Counters, but two other bits, D5 and D4, distinguish this command from a Control Word.

Counter Latch Command

Counter Latch Command2.Counter Latch Command(cntd)• The selected Counter's output latch (OL) latches the count at

the time the Counter Latch Command is received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed)

• The count is then unlatched automatically. This allows reading the contents of the Counters ``on the fly'' without affecting counting in progress.

• Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counter's OL holds its count until it is read.

Read-Back Command3.Read-Back Command• This command allows the user to check the count value, programmed

Mode, and current states of the OUT pin and Null Count flag of the selected counter(s).

• The command is written into the Control Word Register. The command applies to the counters selected by setting their corresponding bits D3, D2, D1 = 1.

• The read-back command may be used to latch multiple counter output latches (OL) by setting the COUNT bit D5 = 0 and selecting the desired counter(s). This single command is functionally equivalent to several counter latch commands, one for each counter latched. Each counter's latched count is held until it is read (or the counter is reprogrammed).

The counter is automatically unlatched when read.


Read-Back Command

Read-Back Command• 3.Read-Back Command• The read-back command may also be used to latch status information of selected

counter(s) by setting STATUS bit D4 = 0. • Status of a counter is accessed by a read from that counter. • Status of the counter format is shown in next figure. Bits D5 through D0 contain the

counter's programmed Mode exactly as written in the last Mode Control Word. OUTPUT bit D7 contains the current state of the OUT pin. NULL COUNT bit D6 indicates when the last count

written to the counter has been loaded into the counting element(CE).• Both count and status of the selected counter(s) may be latched simultaneously by

setting both COUNT and STATUS bits D5,D4 = 0. If both count and status of a counter are latched, the first read operation of that counter will return latched status, The next one return latched count.


Read-Back Command: status byte

D5-D0 =Counter programmed modeStatus Byte

Modes

Mode 0 Interrupt on terminal countMode 1 Hardware Retriggerable one shotMode 2 Rate generatorMode 3 Square Wave GeneratorMode 4 Software Triggered StrobeMode 5 Hardware Triggered Strobe

8254 ModesMode 0 Interrupt On terminal count • Is typically used for event counting. After the Control Word is written,

OUT is initially low, and will remain low until the Counter reaches zero.

• OUT then goes high(this can be used as an interrupt) and remains high until a new count or a new Mode 0 Control Word is written into the Counter.

• GATE = 1 enables counting; GATE = 0 disables counting.Mode 1 Hardware Retriggerable One-Shot • In this mode ,OUT will be initially high. When the Gate is triggered,

Out Goes low, and at the end of the count, OUT goes high again, thus generating a one –shot pulse.


Mode 0Interrupt On Terminal Count


Mode 1Hardware Retriggerable One Shot


8254 ModesMode 2 Rate Geneartor• This mode is used to generate a pulse equal to the clock period at a given

interval.• When the count is loaded, Out stays high until the count reaches 1,and then

the OUT goes low for one clock period.• The count is reloaded automatically, and the pulse is generated continuously.• The count=1 is illegal in this mode. Mode 3 Square Wave Geneartor• In this mode, when the count is loaded, the OUT is high. • The count is decremented by two at every clock cycle, and when it reaches zero,

the OUT goes low, and the count is reloaded again. This is repeated continuously;

• Thus a continuous square wave with period equal to the period of the count is generated.

Mode 2Rate Generator


Mode 3Square Wave Generator


8254 ModesMode 3 Square Wave Geneartor(cntd)If the count (N) is odd, the pulse stays high for (N+1)/2 clock cycles and

stays low for (N-1)/2 clock cycles.

“Similarly you need to explain Mode 4 and Mode5 using timing diagram.”

L48259(Programmable Interrupt Controller)


8259(PIC)

• 8259 is a programmable interrupt controller designed to work with INTEL microprocessors 8085,8086,8088.

• The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU.

• It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single a5V supply. Circuitry is static, requiring no clock input.

Programmable Interrupt Controller 8259


Programmable Interrupt Controller 8259


Pin Description


• Vcc +5v, GND Ground• CS A low on this input will select the chip• WR A low on this pin enables the 8259A to accept the command words from

CPU.• RD A low on this pin enables the 8259A to release the status onto the data bus

for microprocessor.• CAS0-CAS2 In a multiple 8259A structure these lines are used as outputs for a

Master 8259A and inputs for Slave 8259A• INT The INT is connected to the interrupt pin of MPU. Whenever a valid interrupt is asserted, this signal goes high.• INTA interrupt acknowledge signal from MPU.• A0 It is connected to A0 address line of microprocessor. It is used along with

RD , WR, CS, to decipher various command words CPU writes, and status the CPU wishes to read.

• IR0-IR7 Interrupt Requests is executed by raising input low to high.

Block Diagram DescriptionINTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR) The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels which are being serviced.INTERRUPT MASK REGISTER (IMR) The IMR stores the bits which mask the interrupt lines to be masked. PRIORITY RESOLVER Examines these three registers and determines whether INT should be sent to the MPU. Control Logic The INT is connected to the interrupt pin of MPU. Whenever a valid iterrupt is asserted, this signal goes high The I9N9T9A9 is interrupt acknowledge signal from MPU.Cascaded Buffer/Comparator This block is used to expand the number of interrupt levels by cascading two or more 8259As

Interrupt Operation• Interrupt Operation To implement interrupts interrupt enable flip flop in

the microprocessor should be enabled by writing the EI instruction, and 8259 must be initialized by writing control words in the control

register.8269 requires two types of control words :Initialization Control words and Operational control words.

• The ICWs are used to set up the proper conditions and specify RST vector address. The OCWs are used to perform functions such as masking interrupts, Setting up Status read operations, etc. After the 8259 is initialized, the following sequence of events occurs when one or more interrupt lines go high:

1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting the corresponding IRR bit(s).

2. The priority resolver checks three registers: IRR for interrupt requests, the IMR for masking bits, and the ISR for the interrupt request being served. It resolves the priority , and sends an INT to the microprocessor when appropriate.

Interrupt sequence3. The Microprocessor acknowledges the INT and responds with an INTA

pulse.4. After INTA is received, appropriate priority bit in the ISR is set to

indicate which interrupt level is being served, and the corresponding IRR bit is reset to indicate that request is accepted. The 8259A will

also release a opcode of the CALL instruction onto the 8-bit Data Bus.5. When the MPU decodes the CALL instruction, it places two more INTA

signals on the data bus.6. When the 8259 receives second INTA ,The lower 8-bit CALL address is

released by 8259 on the data bus. the higher 8-bit address is released at the second INTA pulse.

7. In the AEOI(automatic end of interrupt) mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence.

Interrupt sequence8. The program sequence is transferred to the memory location

specified by the CALL instruction.

Priority Modes & Other Features1.Fully Nested Mode This is general purpose mode in which all IRs

(interrupt requests) are arranged from highest to lowest, with IR0 as the highest and IR7 as the lowest. In addition any any IR can be assigned the highest priority in this mode; priority sequence will then begin at that IR. In the example below, IR4 has the highest priority & IR3 has the lowest priority:

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 4 5 6 7 0 1 2 3

lowest highest priority priority2.Automatic Rotation Mode In this mode, a device after being serviced,

receives the lowest priority. Assuming that the IR2 has just been serviced, it will receive the seventh priority as shown next:www.yesnarayanan.blogspot.com

Priority Modes & Other Features2.Automatic Rotation Mode IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 1 6 7 0 1 2 3 43.Specific Rotation Mode This mode is similar to the automatic rotation mode, except that

the user can select any IR for the lowest priority, thus fixing all other priorities.END OF INTERRUPT

After the completion of an interrupt service, the corresponding ISR bit needs to be reset to update the information in the ISR. This is called End of Interrupt(EOI) command. It can be issued in three formats:1Nonspecific EOI command When this command is sent to 8259A, it resets the highest

priority ISR bit.2Specific EOI command This command specifies which ISR bit to reset.3Automatic EOI In this mode no command is necessary. During the third INTA, the ISR bit is reset.

L58257(DMA)


8257 DMA• Note:Before reading this chip read DMA data transfer scheme

mentioned earlier• It is a four channel programmable direct memory access controller.

Four I/O devices can be interfaced to the microprocessor through this device. It is capable of performing three operations :Read, Write and verify .

• During the Read operation data data are directly transferred from the memory to the I/O device

• During the Write operation data are transferred from the I/O device to the memory.

• DMA verify does not actually involves any transfer of data.8257 will gain the control of system bus and carry out some verification procedure.

• On receiving a request from an I/O device, the 8257 generates a sequential memory address which allows the I/O device to read or write directly to or from the memory.

Pin Diagram 8257


DMA8257 Block Diagram


DMA8257 Block Diagram• DMA Channels Each channel incorporates two 16 bit registers :DMA

address register & Byte count register. These registers are initialized before a channel is enabled. Initially, the DMA address register is loaded with the address of the first memory location to be accessed. During DMA operation it stores the next memory location to be accessed in the next DMA cycles.

• 14-LSBs of the byte count register store the number of bytes to be transferred.214 (16384) bytes of data can be directly transferred to the memory from the I/O device or vice versa. 2 MSBs of the byte count register indicate the operation which will be performed by the controller on that channel.

• Each channel accepts a DMA Request input DRQ & generates a DMA acknowledge output DACK.

DMA8257 Block Diagram• Data Bus Buffer This is three state ,bidirectional 8 bit buffer interface

which interface 8257 with the system data buffer.• Read/Write control logic • When the microprocessor is programming or reading one of the 8257

registers(when the 8257 is a slave device on the system bus) ,then read/write logic accepts (I9/O9R9) & (I9/O9WF) signals, and decodes the least significant address bits (A0-A3) and either writes the contents of data bus into the addressed register(if (I9/O9WF) is true or places the contents of the addressed register on to the data bus if (I9/O9WF) is true.

• During DMA cycles when 8257 is Bus Master read write logic generates the I/O read and memory write(DMA Write cycle) or I/O write and memory read (DMA Read cycle) signals which control the data link with the peripheral that has been granted the DMA cycle.

DMA8257 Block Diagram• Control logic This logic controls the sequence of operations during all

DMA cycles by generating appropriate control signals and 16 bit address that specifies the memory location to be accessed.

• Mode Set Register 8257 also includes an 8 bit Mode set register and a Status register. when set various bits in the Mode Set Register enable each of the four DMA channels, and allows four different operations of 8257.The 8 bit status register indicates which channels have reached a terminal count and other status information.

• Priority Mode set register has bit D4 bit as rotating priority bit. If this bit is set 1 each channel will get the priority on rotation basis. if the bit is set to 0 .there will be fixed priority for each channel with

channel 0 having highest and channel 3 having lowest.

Priority in 8257


8257 Pin description• DRQ0-DRQ3 These are DMA request lines. An I/O device sends its

DMA request on one of these lines. A high status of the line generates a DMA request.

• DACK0-DACK3 These are DMA acknowledge lines. The 8257 sends an acknowledge signal through one of these lines informing an I/O device that it has been selected for DMA data transfer.A low on the line acknowledges the I/O device.

• A0-A3 are bidirectional lines. • In the master mode these lines carry 4LSBs of16bit memory address

generated by the 8257.• In the slave mode these lines are input lines. The inputs select one of

the registers to be read or programmed.• A4-A7 Lines carry 4 through 7 of the 16 bit memory address generated

by the 8257• D0-D7 These are bidirectional tri state data lines.While programming

the controller ,microprocessor sends data for DMA address register, www.yesnarayanan.blogspot.com

8257 Pin description• D0-D7cntd ,byte count register and the mode set register through these data

lines .During DMA cycle, 8257 sends 8MSBs of the memory address through lines at the beginning of the DMA cycle. These MSBs

are then latched in 8212 latch, and data bus is made available to handle data transfer during rest of the DMA cycle.

• AEN This output is used to disable the system data bus and system control bus.• ADSTB A high on this line latches the 8MSBs of the address into INTEL 8212

connected for this purpose.• CS An active low input for selecting the chip• I/OR It is a bidirectional line. It is used to access data from the I/O device

during the DMA write cycle. • I/OW It is a bidirectional line .It allows the transfer of data to the I/O device

during DMA read cycle.• MEMR It is used to read the data from addressed memory location during

DMA read cycles.


8257 Pin description• MEMW It is used to write the data into addressed memory location

during DMA write cycles.• TC terminal count indicates byte count• MARK Modulo 128 mark. This output notifies the selected peripheral

that current DMA cycle is the 128th cycle.• CLK CLK input• HRQ This output requests the control of the system bus .it is

connected to HOLD input of the microprocessor.• HLDA This input is connected to the HLDA output of microprocessor. It

indicates that 8257 has acquired the control of system bus.


Operation


• Upon receiving A DMA request from enabled peripheral,8257:• Acquires control of the system bus• Acknowledges that requesting peripheral which is connected to the

highest priority channel.• Outputs the least significant 8 bits of the memory address onto the

system address lines A0-A7. Outputs the most significant 8 bits of the memory address to 8212 I/O port via the data bus( the 8212 places these address bits on A8-A15), and

• Generates appropriate memory and I/O read/write control signals that causes the peripheral to receive or deposit a data byte directly from or to the addressed location in memory.

• 8257 will retain the control of the system bus and repeat the transfer sequence as long as a peripheral maintains its DMA request.

• When the specified number of data bytes have been transferred, the 8257 activates its Terminal Count(TC) output informing the microprocessor that the operation is complete.

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Unit 3