unit 1 notes for microprocessor and microcontroller

7/28/2019 unit 1 notes for microprocessor and microcontroller

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Chapter # 1

Historical Evolutions of Microprocessors

The complete Microprocessor FamilyFeatures of 80286Features of 80386

Features of 80486Pentium FamilyPentium Features


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The complete Microprocessor Family

Features of 80286

16-bit microprocessor16 MB Address Space ( 1 GB Virtual Memory)80286 4 /8/16 MHz

Separate pins for Address & Data LinesBU, AU, IU, EUReal Mode and Protected Virtual Address ModeCompatible with earlier versions


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Features of 8038632-bit microprocessor4 GB Address Space ( 64 TB Virtual Memory)Pipelined Architecture (3-4 million Inst/sec)Switch OSDifferent Data Types (b/ B/ W/ DW/ PW/ QW/ TB)Real Mode, Protected mode and Virtual 8086 ModeCompatible with earlier versions

Features of 8048632-bit microprocessor4 GB Address Space ( 64 TB Virtual Memory)80486 25/33/50/66/100 MHz80486 DX/ 80486 SX

On-chip Memory Mgmt and Cache Memory UnitsPipelined Architecture ( 5-stage )Real Mode, Protected mode and Virtual 8086 Mode


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Features of 80486 (contd)

Built-in Parity Generator/Checker Unit

Burst mode memory read and write

New Instructions (XADD, CMPXCHG, BSWAP)

Supports Built-in-self-test ( BIST)

TR3-TR5

Compatible with earlier versions

The complete Microprocessor FamilyChip Year Data Bus Address Bus

4004

1970-80

4 48008 8 88080 8 168085 8 16

8086/8088 16/8 2080186/80188

1980-90

16/8 2080286 16 24

80386-SX 16 2480386-DX 32 3280486-SX 32 3280486-DX 32 32

Pentium 1993 64 32


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The Pentium Family

Processor Memory L1 CacheData-Code L2 Cache Bus Transfer Speed (MHz)

Pentium 4 GB 8K-8K - 60-66

Pentium Pro 64 GB 8K-8K 256K 60-66

Pentium II 64 GB 16K-16K 512K 100

Pentium II Xeon 64 GB 16K-16K 512K 100

Pentium III (1GHz) 64 GB 16K-16K 256K 100

Pentium III (1GHz) Celeron 64 GB 16K-16K 256K 66

Pentium IV (1.3,1.4,1.5GHz) 64 GB 16K-16K 256K 100

Pentium FeaturesWider Data bus width (64-bits)Faster Floating Point Unit (10 times faster)Improved Cache StructureSeparate data and code cacheDedicated TLBDual Integer Processor (2 Instn/clock)Branch Prediction Logic (2 pre-fetch buffers)


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Pentium Features (contd)Data Integrity and Error DetectionFunctional Redundancy Checking(2nd Processor Checker )Superscalar ArchitecturePentium-Pro ( 5 Instn/Execution)16K L1 and 256K L2 cache

Includes Error-Correction Circuitry4 additional address lines (64 GB memory space)

Comparison of 16 ,32 and 64 bit Microprocessors


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Comparison of 16 ,32 and 64 bit Microprocessors (contd.)

Comparison of 16 ,32 and 64 bitMicroprocessors (contd.)


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Comparison of 16 ,32 and 64 bitMicroprocessors (contd.)

PentiumArchitecture


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1. Reduce Access to Main Memory10ns vs 60nsCache

2. Keep Addressing modes and InstructionsSimple

Programmers use small subsetReduce complexity of Instruction decoder,addressing logic & execution unitLooks like CISC machine

3. Make good use of RegistersLarge set of registers16-bit, 32-bit, 80-bit

4. Pipeline everything2 pipelines

Instruction PipelineBus Cycle Pipeline

Branch Prediction


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5. Utilize Compiler Extensively

Optimization on Assembly LanguageSubstitute an Instruction

Pentium contains both CISC and RISCcharacteristics

Pentium Real Mode


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Pentium Real Mode

PentiumReal Mode


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Pentium Real Mode

Pentium Real Mode : Address Generation


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Pentium Real Mode

Pentium Real Mode: Interrupts & Exception


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Pentium Real Mode: Interrupts & Exception

Pentium Real ModeSupports Architecture of 8086 but can access 32-bit registersProgramming Model (Register Set : 8+8 = 16 )

CR0 (Control Register 0) : used to enter in Protected Mode ( PE)1 MB memory and 64KB I/O Space

Paging mechanism is not supportedLinear addresses are Physical addresses

(21-bit address allowed)Interrupts and Exceptions

From 000 H 3FF H (400 memory locations) are dedicatedfor IDT (Interrupt Descriptor Table or Pointer to ISR)

IDTR Re-locatable, 48-bit (32-base & 16-limit)


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Pentium Superscalar ArchitectureSuperscalar Machine:

Processor capable of parallel instruction execution of multipleinstructions are known as superscalar machines

Capable of 2 integer or 2 floating point instructionssimultaneously

Possible due to U & V pipeline

Restrictions for Pairing Instructions

Compilers role for ordering instructions during code generation

Pentium Superscalar Architecture

Floating point Instructions Pairing Rule


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Instruction Pairing Rules1. Both instructions must be Simple Instructions

Execute in 1 clock (hardwired)MOV R/R, INC, DEC, Near conditional Jumps (JZ, JNZ)Restriction to conditional instructions: it must be the 2 nd

instruction in the pair

2. Shifts or Rotates can only pair in the U pipe3. ADC and SBB can only pair in the U pipe

4. JMP, CALL and JCC can only pair in the V pipe

5. Neither instruction can contain both a displacement and animmediate operand . (Ex: MOV [SI+2], 0010H)

6. Prefixed instructions can only pair in the U pipe

Instruction Pairing Rules7. The U pipe instruction must be only 1 byte in length or it will

not pair until 2 nd time it executes from the cache

8. There should NOT be any DATA DEPENDANCY Read-after-write dependency Write-after-write dependency


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Pipelining

Is a valid technique for improving Instruction

Execution RatePipeline Stages of U & V Pipeline

Pipelining


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Pipelining

U pipeline can execute ANY instruction

V pipeline executes only SIMPLE instructions.

Under ideal conditions 2 INTEGER instructions my completeexecution EVERYclock cycle

Branch Prediction

The incorrect instructions that loaded wrongly, must bediscarded. This is called FLUSHING of the pipeline.

No work is done when the pipeline stages are reloaded.

These disturbances in the pipelined instruction execution arecalled BUBBLES.


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Branch Prediction : Dynamic

BTB ( Branch Target Buffer )

a special cache that stores the instruction and targetaddresses of any branch instruction that have beenencountered in the Instruction Stream.

BTB stores history bits . These are Initially set to 11 when anew target address is placed into the BTB.

If a new branch instruction is encountered, the prediction is

not taken . (no target address in the BTB / HB = 00)

Dynamic Branch Prediction


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Branch Prediction : Dynamic

Two 32-Byte Pre-fetch Buffers

Incorrect predictions or correct predictions with wrong targetaddress cause the pipelines to be flushed

Pentium sets the history bits to 11 for a new entry.

The Instruction and Data Cache


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Cache Organization


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The Instruction and Data Cache in PENTIUM



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Linear to Physical Address Generation


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FPU: Floating Point Unit


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FPU: Floating Point Unit Pipeline Stages

FPU: Pipeline Stages


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FPU Register File

FPU Data TypesInteger (Signed and Unsigned)

Byte IntegerWord Integer

Short Integer (Double Word)Long Integer (Quad Word)

Packed BCD (10 / 9 Bytes -18)Real Numbers

Short Real (Single-precision)

Long Real (Double-precision)

Extended Real (Extended-precision)


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Integer formatsin the FPU

Real, Long Real, Extended RealFormats in the FPU

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unit 1 notes for microprocessor and microcontroller