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UML / SysML – SystemC Génération de code - Simulation
SODIUS - Philippe Soulard – 14 Juin 2013 - NANTES
Journées Scientifiques de l’Université de Nantes
Colloque 3 - Logiciels de Qualité – Modélisation et Vérification
• SME, 2001, 15 p., Headquarter in France, US subsidiary
• Our mission: improve the engineering process through advanced interoperability solutions – Migration, Exchange and Synchronization of Engineering data
– Customized and Optimized Generation of Engineering artifacts
• Technology provider for IBM and No Magic – IBM Rational Rhapsody as “XMI Toolkit”, “Rhapsody in Ada” and “Rules
Composer” (2001), Statemate, Doors DXL
– No Magic as “Cameo Workbench” and “Cameo Inter-Op” (2010)
Company Profile
Model Driven Engineering
MDWorkbench
SODIUS Technology
Code Document or any textual output
Accessors
Rules
Transformed Output models
Input models or formats
MDWorkbench - Connection and Transformation Bus
ReqIF
Requirement Architecture
Implementation Generation
V&V
Integrity DOORS
Design
MATLAB Simulink
ARIS System Architect
Unit Testing
Simulation
New Connector*
ALM Implementation Reporting
*
ENGINE
RTC OSLC
Word
Excel
Rhapsody
Enterprise Architect
MagicDraw
MDWorkbench
Metamodeling Standards
Code Generation & Reverse Engineering
High-Level Model
HW Model
HDL Code
Syntactic Model
Conceptual Model
Code Generation
Reverse Engineering
m2m
m2t
t2m
m2m
m2m
m2m: model-to-model, m2t: model-to-text, t2m: text-to-model
MM
MM
Grammar
MM
MM
High Abstraction Level
Low Abstraction Level
Parsing
UML / SysML
Model-Driven Engineering (MDE) for Electronic System Level (ESL) Design & Simulation
MDWorkbench for ESL-EDA Ecosystem
MDWorkbench for EDA
Office
Doc
UML EDA
Model
Device
IP
HDL
System Level Design: Challenges and Needs
Challenge Need
System Performance Model system at multiple levels of abstraction in
order to study architectural tradeoffs
• HW/SW partitioning
• Power, time, space
• Micro-architecture
Time to Market • Enable early SW development against HW
models
• Incorporate and exchange existing legacy & IP
Quality • Employ a rigorous verification process
• Requirements tracking
Process • Effective workflow and methodology
• Tracing of design artifacts
- Models (SW and HW)
- Requirements
- Test cases
UML for System Level Design • UML as a widely accepted standard
– UML suitable for electronic modeling
• Extension for system-software-hardware co-design – Design, simulation, code generation, process documents
• Need for a common methodology (integration, tools) – Corporate benefits
• Need for data exchange between design teams – Model-based IDE
• Systems on a chip are more and more complex – Hardware-Firmware-Software integration
– Soft & Hard cores, external IPs
• Evolutions of hardware design languages & methods – Schematic → VHDL/Verilog → ESL, SystemC, SystemVerilog, UML
SysML Basics
• Modeling formalism based on UML – SysML is UML version intended for modeling Systems
– Born in 2001 from collaboration between INCOSE and OMG
• Simplifies UML
• Structural, behavioral and interaction views
• Use of standard programming languages including C and C++
• Strong industry support
Action Language Rationale
High-level UML semantic vs low-level expression Operation body, trigger/guard/action in Transitions/States, Declarations
Which language ? Textual notation versus model + transformations
General language versus HDL specific
Accessible to System, Software & Hardware designers
Best candidate: C++ Standard, mature, high-performance
C++ subset with macros (on events, ports ...)
C mastered by hardware designers
SystemC is a C++ library
Development Process
MDE for Electronic System Level UML / SysML
HW/SW System Level Design Flow
• System Model maintains integrity across HW and SW
• Models emphasize – Functionality – Composition – Interfaces
• Models are executable • Models remain
consistent • Ensures smooth
integration
System Model
Software Hardware
Model
Analysis
Integration
(Virtual) Platform
Continuous Integration
Development Process
SS1 - Enty and Exit Control System«Requirement»
SS11 - Security Checks«fromWord»
SS111 - Security Card«fromWord»
«satisfy»
«satisfy»
SS112 - Biometric Scan«fromWord»
SS12 - Access Priority and Time«fromWord»
«satisfy»
SS13 - Exit requirements«fromWord»
MA2 - Time monitoring«fromWord»
Three Attempts On Employee ID Entry
ID = SS11-7
«satisfy»«satisfy»
Three Attempts On Employee ID Exit
ID = SS11-9
«satisfy»«satisfy»
«satisfy»
Alarm Conditions
ID = MA2-2
«satisfy»
«satisfy»
Disabling User Account
ID = SS11-14
«satisfy»
«satisfy»
Denied Entry Notification
ID = SS11-10
«satisfy»
Out of Date Cards - Entry
ID = SS111-4
«satisfy»
Out of Date Cards - Exit
ID = SS111-5
«satisfy»
«satisfy»
Time Between Two Independent Checks
ID = SS11-5
«satisfy»
Exit Time
ID = SS12-3
«satisfy»«satisfy»
«satisfy»
Accesss Precondition
ID = SS111-2
«satisfy»
«satisfy»
Processing User Request
ID = SS12-1
«satisfy»
Alarm - Entry
ID = SS11-12
«satisfy»
«satisfy»
Alarm - Exit
ID = SS11-13
«satisfy»
«satisfy»
Employee ID Card Identification - Entry
ID = SS11-2
«satisfy»
Employee ID Card Identification - Exit
ID = SS11-3
«satisfy»«satisfy»
«satisfy»Visualization of Security Card Check Status - Entry
ID = SS11-15
«satisfy»
«satisfy»
Visualization of Security Card Check Status - Exit
ID = SS11-16«satisfy»
Security Card Information
ID = SS111-1
«satisfy»«satisfy»
Two Independent Security Checks
ID = SS11-1
«satisfy»«satisfy»
«satisfy»
Denied Exit Notification
ID = SS11-11
«satisfy»
Three Attempts On Biometric Data Entry
ID = SS11-8
«satisfy»«satisfy»
Visualization of Biometric Data Check Status
ID = SS11-17
«satisfy»«satisfy»
Approval of Biometric Data
ID = SS112-1
«satisfy»«satisfy»
«satisfy»
Biometric Scan
ID = SS11-4
«satisfy»
«satisfy»
Biometric Data Storage
ID = SS112-2
«satisfy»
MA1 - Image Capture«fromWord»
E1 - Emergency Exit«fromWord»
E2 - Security Lockdown«fromWord»
«satisfy»
Image Captue
ID = MA1-1
«satisfy»
Security Lockdown
ID = E2-1
«satisfy»«satisfy»
Emergency Exit
ID = E1-1
«satisfy»«satisfy»
«satisfy»
Time Recording
ID = MA2-1
«satisfy»
«satisfy»
Entry Time
SS12-2
«satisfy»
RD_SysReqsToSHReqsLinks
«satisfy»
Authorization of Security Card - Exit
ID = SS13-1
«satisfy»
ID =
SS1 - Enty and Exit Control System«Requirement»
SS11 - Security Checks«fromWord»
SS111 - Security Card«fromWord»
«satisfy»
«satisfy»
SS112 - Biometric Scan«fromWord»
SS12 - Access Priority and Time«fromWord»
«satisfy»
SS13 - Exit requirements«fromWord»
MA2 - Time monitoring«fromWord»
Three Attempts On Employee ID Entry
ID = SS11-7
«satisfy»«satisfy»
Three Attempts On Employee ID Exit
ID = SS11-9
«satisfy»«satisfy»
«satisfy»
Alarm Conditions
ID = MA2-2
«satisfy»
«satisfy»
Disabling User Account
ID = SS11-14
«satisfy»
«satisfy»
Denied Entry Notification
ID = SS11-10
«satisfy»
Out of Date Cards - Entry
ID = SS111-4
«satisfy»
Out of Date Cards - Exit
ID = SS111-5
«satisfy»
«satisfy»
Time Between Two Independent Checks
ID = SS11-5
«satisfy»
Exit Time
ID = SS12-3
«satisfy»«satisfy»
«satisfy»
Accesss Precondition
ID = SS111-2
«satisfy»
«satisfy»
Processing User Request
ID = SS12-1
«satisfy»
Alarm - Entry
ID = SS11-12
«satisfy»
«satisfy»
Alarm - Exit
ID = SS11-13
«satisfy»
«satisfy»
Employee ID Card Identification - Entry
ID = SS11-2
«satisfy»
Employee ID Card Identification - Exit
ID = SS11-3
«satisfy»«satisfy»
«satisfy»Visualization of Security Card Check Status - Entry
ID = SS11-15
«satisfy»
«satisfy»
Visualization of Security Card Check Status - Exit
ID = SS11-16«satisfy»
Security Card Information
ID = SS111-1
«satisfy»«satisfy»
Two Independent Security Checks
ID = SS11-1
«satisfy»«satisfy»
«satisfy»
Denied Exit Notification
ID = SS11-11
«satisfy»
Three Attempts On Biometric Data Entry
ID = SS11-8
«satisfy»«satisfy»
Visualization of Biometric Data Check Status
ID = SS11-17
«satisfy»«satisfy»
Approval of Biometric Data
ID = SS112-1
«satisfy»«satisfy»
«satisfy»
Biometric Scan
ID = SS11-4
«satisfy»
«satisfy»
Biometric Data Storage
ID = SS112-2
«satisfy»
MA1 - Image Capture«fromWord»
E1 - Emergency Exit«fromWord»
E2 - Security Lockdown«fromWord»
«satisfy»
Image Captue
ID = MA1-1
«satisfy»
Security Lockdown
ID = E2-1
«satisfy»«satisfy»
Emergency Exit
ID = E1-1
«satisfy»«satisfy»
«satisfy»
Time Recording
ID = MA2-1
«satisfy»
«satisfy»
Entry Time
SS12-2
«satisfy»
RD_SysReqsToSHReqsLinks
«satisfy»
Authorization of Security Card - Exit
ID = SS13-1
«satisfy»
ID =
Requirements Diagram: Visualization of Links between Stakeholder Requirements and System Requirements
Use Case Diagram:System Use Cases
UCD_SecuritySystem
Security System
Uc3ConfigureSecuritySystem
Uc2Control Exit
Uc1Control Entry
AccessPointAccessPoint
CameraCameraUserUser
AdminAdmin
UCD_SecuritySystemUCD_SecuritySystem
Security System
Uc3ConfigureSecuritySystem
Uc2Control Exit
Uc1Control Entry
AccessPointAccessPoint
CameraCameraUserUser
AdminAdmin
Security System
Uc3ConfigureSecuritySystem
Uc2Control Exit
Uc1Control Entry
AccessPointAccessPoint
CameraCamera
AccessPointAccessPoint
CameraCameraUserUser
AdminAdmin
Functional Decomposition
readSecurityCard
User
validateSecurityCard
[CardStatus Valid][CardStatus Valid]
scanBiometricData
User [else][else]
authenticateBiometricData
[else]
flagBiometricScanFailure
[else]
[else][else]
[else]
flagSecurityCardFailure
[else]
[else][else]
[BiometricData Authenticated]
logEntryData
[BiometricData Authenticated]
[BsFailCount==3]
disableUserAccount
Admin
[BsFailCount==3]
[ScFailCount==3][ScFailCount==3]
displayCardStatus
[Timeout BiometricScan][Timeout BiometricScan]
displayAuthenticationStatus
logAccountData
alarm
unlockAccesspoint
«MessageAction»
AccessPoint
[Timeout Unlocked]
lockAccesspoint
«MessageAction»
AccessPoint [Timeout Unlocked]resetAlarm
Admin
[else][else]
takePicture
«MessageAction»
Camera
[First Request][First Request]
Uc1ControlEntryBlackBoxView
readSecurityCard
User
validateSecurityCard
[CardStatus Valid][CardStatus Valid]
scanBiometricData
User [else][else]
authenticateBiometricData
[else]
flagBiometricScanFailure
[else]
[else][else]
[else]
flagSecurityCardFailure
[else]
[else][else]
[BiometricData Authenticated]
logEntryData
[BiometricData Authenticated]
[BsFailCount==3]
disableUserAccount
Admin
[BsFailCount==3]
[ScFailCount==3][ScFailCount==3]
displayCardStatus
[Timeout BiometricScan][Timeout BiometricScan]
displayAuthenticationStatus
logAccountData
alarm
unlockAccesspoint
«MessageAction»
AccessPoint
[Timeout Unlocked]
lockAccesspoint
«MessageAction»
AccessPoint [Timeout Unlocked]resetAlarm
Admin
[else][else]
takePicture
«MessageAction»
Camera
[First Request][First Request]
Uc1ControlEntryBlackBoxView
Use Case Black-Box Activity Diagram of Uc1ControlEntry
Definition of the use case functional flow (“storyboard”)
Use Case Activity
Sequence Diagrams
itsUc_Uc1ControlEntry1
ScFailCount
BsFailCount
t_Bs
t_Unlocked
AuthenticationStatus
CardStatus
reqReadSecurityCard
reqScanBiometricData
evAccessPointUnlocked
evAccessPointLocked
flagSecurityCardFailure
disableUserAccount
readSecurityCard
scanBiometricData
authenticateBiometricData
logEntryData
flagBiometricScanFailure
logAccountData
displayCardStatus
displayAuthenticationStatus
alarm
resetAlarm
reqResetAlarm
pAdmin
iAdmin_Uc_Uc1ControlEntry
pAccessPoint
iAccessPoint_Uc_Uc1ControlEntry
pCamera
iUc_Uc1ControlEntry_Camera
pUseriUser_Uc_Uc1ControlEntry
itsUser1
RequestEntry
ScanFingerprint
RequestExit
pUc1_ControlEntry
iUser_Uc_Uc1ControlEntry
itsAdmin1
reqProcessAlert
pUc1_ControlEntry
iUc_Uc1ControlEntry_Admin
itsAccessPoint1
reqUnlockAccessPoint
reqLockAccessPoint
pUc1_ControlEntry
iUc_Uc1ControlEntry_AccessPoint
itsCamera1
reqTakeSnapshot
pUc1_ControlEntry
iUc_Uc1ControlEntry_Camera
IBD_Uc1_ControlEntry
iUc_Uc1ControlEntry_AccessPoint
iAccessPoint_Uc_Uc1ControlEntry
iAdmin_Uc_Uc1ControlEntry
iUc_Uc1ControlEntry_Admin
itsUc_Uc1ControlEntry1
ScFailCount
BsFailCount
t_Bs
t_Unlocked
AuthenticationStatus
CardStatus
reqReadSecurityCard
reqScanBiometricData
evAccessPointUnlocked
evAccessPointLocked
flagSecurityCardFailure
disableUserAccount
readSecurityCard
scanBiometricData
authenticateBiometricData
logEntryData
flagBiometricScanFailure
logAccountData
displayCardStatus
displayAuthenticationStatus
alarm
resetAlarm
reqResetAlarm
pAdmin
iAdmin_Uc_Uc1ControlEntry
pAccessPoint
iAccessPoint_Uc_Uc1ControlEntry
pCamera
iUc_Uc1ControlEntry_Camera
pUseriUser_Uc_Uc1ControlEntry
itsUser1
RequestEntry
ScanFingerprint
RequestExit
pUc1_ControlEntry
iUser_Uc_Uc1ControlEntry
itsAdmin1
reqProcessAlert
pUc1_ControlEntry
iUc_Uc1ControlEntry_Admin
itsAccessPoint1
reqUnlockAccessPoint
reqLockAccessPoint
pUc1_ControlEntry
iUc_Uc1ControlEntry_AccessPoint
itsCamera1
reqTakeSnapshot
pUc1_ControlEntry
iUc_Uc1ControlEntry_Camera
IBD_Uc1_ControlEntry
iUc_Uc1ControlEntry_AccessPoint
iAccessPoint_Uc_Uc1ControlEntry
iAdmin_Uc_Uc1ControlEntry
iUc_Uc1ControlEntry_Admin
SysML Structural View
SysML System On a Chip (SoC)
SysML Behavioral View - Statechart
• Component Behavior specified by a combination of state machines and action language code (i.e. C++)
• Statecharts – Hierarchical and concurrent – Natural notation for specifying HW designs
and protocols
OPORT(pTx)->GEN(evData(regs[0]));
regs[2] = regs[2] & 0xFD;
if (regs[3] & 0x02)
OPORT(pCpuIrq)->GEN(evInterrupt(1));
Simulation or Execution on Host and Target
Hardware Description Language
SystemC
MDE for Electronic System Level UML / SysML
Hardware Description Languages VHDL & Verilog for Synthesis (and Simulation)
SystemC & SystemVerilog for Simulation (and Synthesis)
Trends of Electronic Design
• Register Transfer Level (RTL) synthesis mature, but…
• Hardware complexity continues to increase – RTL-based flows are becoming inadequate
• Industry pushing up to a higher level of abstraction – High-level synthesis
– HW/SW co-simulation (i.e., Virtual platforms)
• Trending toward standardization on the use of SystemC and Transaction Level Modeling (TLM)
• Architectural Exploration and Analysis – Partitioning
– Design trade-offs (i.e. fifo depth, latency, …)
– Provides loosely-timed hardware model for software development
– TLM mode – transaction level view
• Implementation – Generate SystemC synthesizable subset
– Generated SystemC flows into HLS tool chain for HW implementation
– Synthesis mode
• Verification – Cycle-level timing (Cycle Accurate mode)
– Increased concurrency in targeted framework
– Cycle-accurate SystemC reference model used to validate RTL
SystemC Use Cases
System Modeling with SystemC - TLM
• Intended to provide a model of the system that allows for software development and high-level architectural exploration.
• TLM 2.0 standard calls out two coding styles – Loosely Timed: Component interaction encapsulated as TLM transactions.
– Approximately Timed: Partial refinement of transactions to protocols.
• Goal is fast simulations (100 to 1000x over RTL)
• Optimize yields
SystemC HLS Synthesis
• OSCI is defining a SystemC synthesizable subset. Must generate code that conforms to the subset.
• Code intended for simulation need not reflect detailed hardware structures, but code that’s input to HLS must.
• HLS tool must be able to determine architecture by analyzing constructors.
• User level code cannot use many coding idioms: – Dynamic storage allocation
– Unbounded loops (in some contexts)
– Use of channels
• Interface specification – What are the protocols used to pass data in and out of design blocks
– Timing uncertainty: the time the outputs appear depends on the synthesis engine
Cycle Accurate Modeling
• Timing Accurate. Agreement between the simulated and actual time for communication and computation steps.
• Default Timing Model: – One step of a statechart takes one execution cycle – Communication takes one cycle
• Default timing model can be altered by user annotations (primarily wait statements).
• Concurrency using “and” states in statechart modeled with fine-grained (cycle accurate) concurrency.
Implementation
Rhapsody / SysML to SystemC
MDGen for SystemC
MDE for Electronic System Level UML / SysML / SystemC
Rh
apso
dy
– U
ML/
SysM
L
Do
ors
Requirements Analysis
Architectural Analysis
Functional Analysis/Allocation
Implementation
Integration and Test
Syst
emC
/HD
L
Tools and Technologies
SystemC Generator Requirements
• Seamless integration in a UML tool (Rhapsody) – Rhapsody-in-C++ base (same philosophy as Rhapsody-in-Ada)
• Generation from OMD, Statechart & Action Language
• Open rule-based generator – RulesPlayers scenarios
– RulesComposer Eclipse/EMF editor
– Much more than a single code generator ...
• Compilation, execution and simulation environments – Generate and edit SystemC code (with roundtripping)
– Compile & Run (with log and build windows)
• Microsoft Visual C++ (Windows)
• Cygwin/gcc (Linux)
– Simulate (traces, diagram animations)
MDGen for SystemC
Generation
from
Statecharts
Logs &
Build Links
with EDA
tools
Edition of
SystemC
code
OMD for
Application
& Platform
External Generator based on RulesComposer & RulesPlayer
Profiles
Hardware
Libraries &
Types
SystemC
Configuration
Application &
Platform
Packages
Timed Model Programmers View
http://sodius.com/ Rhapsody/SysML - SystemC http://sodius.com/products-overview/mdgen-for-systemc
SODIUS 14 Bd du Maréchal Juin, 44100 NANTES [email protected]
Thank you for your attention Comments, Questions ...
