Tutorial1_LNAs

Spring 2009: Radio Frequency Integrated Circuits (TSEK03) 1/18

Electrical Engineering Department (ISY), Linköping University [email protected]

Tutorial-1 Low Noise Amplifier (LNA) Design

By Rashad.M.Ramzan

[email protected] Objective: Low noise amplifiers are one of the basic building blocks of any communication system. The purpose of the LNA is to amplify the received signal to acceptable levels with minimum self-generated additional noise. Gain, NF, non-linearity and impedance matching are four most important parameters in LNA design. The objective of this tutorial is to outline the basic tradeoffs between different amplifying topologies w.r.t gain, NF and impedance matching. After this comparison it is concluded that inductor degenerated common source topology gives the best performance to meet the gain, NF, and impedance matching goals with minimum power consumption in case of narrowband designs.

Goals: After this tutorial, students should be able to

• Calculate the gain, input impedance and NF of common gate, common source, and shunt feedback amplifiers.

• Understand the basic equations and tradeoff between different LNA topologies.

• Perform the calculation for inductor degenerated common source topology and understand the tradeoff between the gain, NF, and impedance matching.

A supplement tutorial LNA lab is also part of this course which takes the circuit from Problem-1.8 and guides through different analyses to design a practical LNA.



VDD

RL

VGS x(t) NMOS

DC-bias

Problem-1.1(Tutorial) NMOS transistor is racing horse in LNA design arena due to its higher mobility compared to PMOS transistors. Calculate the IP3 of NMOS CS amplifier shown below. Assume that NMOS transistor is in saturation.

a) Consider simplified square law model. (HW)

2( )2

nD GS T

KI V V= −

b) Consider the short channel effects as (Tutorial) 2

1

( )2 1 ( )

,0.2 0.1

n GS TD

GS T

GS T

K V VIV V

Velocity Saturation Mobility DegradationV V V and V

θθ

θ −

⎡ ⎤−= ⎢ ⎥+ −⎣ ⎦=

− = =

Observe that this transistor is not a very “short channel” device as θ << 1. c) What conclusion can be drawn from part b) about the bias current and transconductance

of the transistor for higher IP3?

Solution: a). Homework answer: ∞=3IP b).

)()()()( 33

2210 txtxtxxy αααα +++= --------------(1)

3

1321 3

4coscos)(αα

ωω =⇒+= IPAtAtAtx



( ))(12

2

TGS

TGSnD VV

VVKI−+

−=

θ

Here we assume a small signal x(t) around the bias (VGS – VT), so

( )[ ]))((1

)(2

2

txVVtxVVKI

TGS

TGSnD +−+

+−=

θ

we define VVV TGS Δ=− --------------- Bias voltage

[ ]1))((

)(2

2

+Δ+Δ+

=VtxVtxKI n

D θ --------------------------------------------------------------(2)

( )( )Vtx

VtxRKVRIV LnoLDo Δ++

Δ+=⇒=

)(1)(

2

2

θ and we put KRK Ln =

2

1<<θ so ( )Vtx Δ+)( is also small 21

11 ρρ

−=+

⇒

( )( )

2)(1

)(11 Vtx

VtxΔ+

−≈Δ++

θθ

( ) ( )⎟⎠⎞

⎜⎝⎛ Δ+−Δ+=

2)(1)( 2 VtxVtxKVo

θ

( ) ( )2

)()( 32 θKVtxVtxKVo Δ+−Δ+=

)(2

)(2

3

)(2

322

32

232

txKtxVKK

txVKVKVKVKVo

θθ

θθ

−⎟⎠⎞

⎜⎝⎛ Δ−+

⎟⎠⎞

⎜⎝⎛ Δ−Δ+Δ−Δ=

-----------------------------(3)

Comparing (1) & (3)

21 2

32 VKVK Δ−Δ=θα , VKK Δ−=

23

2θα ,

23θα K

−=

⎟⎠⎞

⎜⎝⎛ Δ−

Δ=

Δ−Δ×== 2

2

3

13 32

38

2

232

34

34 VV

K

VKvKAIP θθ

θ

αα

θθVVAIP

Δ=

Δ=

3162

38

3 As 1<<θ 23 VΔ can be ignored.



( )θθ

TGSIP

VVVA−

=Δ

=3

163

163 -------------------------------(4)

Please, note that this formula only holds for small value of θ. For larger θ values compare the lecture notes. In any case a large gate bias voltage (VGS – VT) improves IP3.

Put -1V 0.1 V,2.0 ==Δ θV

VoltsAIP 27.31.02.0

316

3 ==

dBmmWdBmIIP 201501.

227.3log10)(3

2

≅⎥⎥

⎦

⎤

⎢⎢

⎣

⎡

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛=

c). From ( ))(12

2

TGS

TGSnD VV

VVKI−+

−=

θ the NMOS transconductance can be found as

( )( )2)(1

)(2)(2 TGS

TGSTGSnm VV

VVVVKg−+

−+−=

θθ

.

By comparison of those two formulas we find

2)(2)(1)( TGS

TGS

TGSTGS

m

D VVVVVVVV

gI −

≅−+−+

×−=θθ

and hence, (4) can be rewritten as

m

DIP g

IAθ3

323 ≅

As shown, IIP3 is decided by the ratio ID/gm which is constant for a given gate bias voltage. Using e.g. a wider transistor does not change this ratio and only the power consumption is increased.

Problem-1.2 (Tutorial) It is preferred in current RF designs that the input of LNA be matched to 50 Ω. The easiest way is to shunt the gate with a resistor of 50 Ω.

a) Calculate the gain, input impedance and NF in absence of gate noise. Assume that Rsh=RL for NF derivation.

b) What are the disadvantages of shunt resistor with reference to gain and NF?



gmVgs

S

D Vout

RLdi2

RL is noiseless

G

Rsh

RshnV ,2

RsnV ,2 Rs

VDD

RL

Rsh

Vin

Vout

Zin

Rs

(Biasing not shown)

Solution: a). (Please read assumption in the problem statement carefully)

sourceinputtoduenoiseOutputpowernoiseoutputTotalF =

fkTRV sRsm Δ= 4,2 LmGate

RgGain −=

fkTRV shRshm Δ= 4,2 ⎟⎟

⎠

⎞⎜⎜⎝

⎛+

=shs

shLm RR

RRgA for Rsh = Rs

fgkTi md Δ= γ42 2

Lm

RgA −=

Using superposition, considering one at a time and shorting / opening other sources. 2

22,

2,

2⎟⎟⎠

⎞⎜⎜⎝

⎛+

××=shs

shLmRsnRson

RRRRgVV

222

,2

,2

⎟⎟⎠

⎞⎜⎜⎝

⎛+

××=shs

sLmRshnRshon

RRRRgVV



Lddno RiV 22,

2 ×=

Rson

doRshon

Rson

dnoRshonRson

VVV

VVVVF

,2

,2

,2

,2

,2

,2

,2

1 ++=

++=

( )

( ) ( )2

222

2

2

222

2

222

4

4

4

41

shs

sLmS

Lm

shs

sLms

shs

shLmsh

RRRRgfkTR

RfgkT

RRRRgfkTR

RRRRgfkTR

F

+×

×Δ

×Δ+

+×

×Δ

+×

×Δ+=

γ

In case of impedance match Rs = Rsh

smLms

mL

S

LSms

mL

RgRgR

gR

RRRg

R

gRF

γγγ 42

4

2

4

11 22

2

2

222

2

+=×

×+=

××

++=

b). - Poor Noise Figure

- Input signal attenuated by voltage divider

- Rsh adds extra noise.

- At high frequency, shunt L is needed to tune out Cgs

- Reduced gain.

Problem-1.3 (Tutorial) Another approach to get 50 Ω input impedance match is shunt feedback amplifier shown below.

a) Calculate the gain, input impedance and NF neglecting the gate noise. The gate-drain,

gate-bulk, and gate-source capacitance can be neglected as well. b) What are the disadvantage of shunt feedback amplifier with reference to gain and NF?



gmVgs

Vout

RLnDI 2

(Equivalent noise model ignoring gate noise), RL is noiseless

Rs

RsnV ,2

RFnV ,2 RF

VDD

RL Vout

Zin

Rs

(Biasing not shown)

RF

Vin

gmVgs

Vout

RL

Rs RF

Vgs

iin

Vin

RL

Vout

Iin Rs

RFIin

Solution:

fkTRVfgkTI SRSmnD Δ=Δ= 4,4 22 γ

sourceinputtoduepowernoiseOutputpowernoiseinputTotal

VAVF

RStotv

outn ==2

,2

,2

Here Av,tot = Gain from Vin to Vout

Again using superposition theorem

RStotv

outDnoutRFnoutRSn

RStotv

outn

VA

VVV

VAVF

2,

2

,2

,2

,2

2,

2

,2 ++

==

Gain Calculation

( ) outFSinin VRRiV ++=

( ) Lgsminout RVgiV −=

oFings VRiV +=

( )LSmLFS

LmL

in

outtotv RRgRRR

RgRVVA

+++−

==1

,

If RF>>RS & gmRF>>1

Lm

F

SmL

F

S

Lmtotv Rg

RRgR

RR

RgA −≅+

+++

−= 11

,

Lmtotv RgA −≅,

Also Lm

LFin Rg

RRZ++

=1

By ignoring Cgs, we have considered real part only.



gmVgs

outRFV ,2

RL

Rs RF

Vgs

i RFV 2

gmVgs

outnDV ,2

RL

Rs RF

Vgs

i

DnI ,2

For source resistance

nRStotvoutnRS VAV 2,

2,

2 = ---------------(1) For feedback resistance

outRFRFFSgs VViRiRV ,+−=−=

( )gsmLoutRF VgiRV −=,

( )

( )SmF

LRF

smL

FSRFoutRF Rg

RRV

RgRRRVV +=

++

+= 1

11

1,

( )2

,2

,,2 1 ⎥

⎦

⎤⎢⎣

⎡+= Sm

F

LRFnoutRFn Rg

RRVV ---------------------(2)

Similarly

0,, =+

+++FS

outnDgsmnD

L

outnD

RRV

VgIR

V

FS

outnDSgs RR

VRV

+= ,

LnD

FS

Sm

FSL

DnoutnD RI

RRRg

RRR

IV ≈

++

++

=11

,,

So,

22,

2LnDoutnD RIV = ------------------------------------------(3)

Combaining (1) (2) & (3)



( )

RSntotv

LnD

RSntotv

SmF

LRFn

VARI

VA

RgRR

VF

,2

,2

22

,2

,2

2

,2 1

1 +⎥⎦

⎤⎢⎣

⎡+

+=

Lmtotv RgA −=, , fkTRV SRSn Δ= 4,2 , FRFM kTRV 4,

2 = & mnD gkTI γ42 =

SmSmF

S

RgRgRRF γ

+⎟⎟⎠

⎞⎜⎜⎝

⎛++=

2111

b).

NF ↓ gmRS ↑ & RF ↑ usually Ω= 50SR

- Better performance than CS amplifier

- RF induces noise

- At higher f ↑ a shunt inductor needed to tune out Cgs

- Broadband Amp @ Lower frequency

- To make NF ↓ RF > RS and gmRS >> 1

Problem-1.4 (HW) Common gate amplifier also offers 50 Ω input impedance match and solves the input matching problem.

c) Calculate the gain, input impedance and NF in absence on gate noise. Neglect gate drain

and gate to bulk and gate to source capacitance. a) What are the disadvantage of common gate amplifier with reference to gain and NF?

Problem-1.5 (Tutorial) The disadvantages of the amplifiers discussed in Problem-2, 3 & 4 can be circumvented by using the source degenerated LNA shown below.



VDD

RL

VS VoutRs

(Biasing not shown)

Ls

Lg

VS Rs

Ls

Lg iin Voutio

gmVgs

Vin Vgs

Zin

a) Calculate the input impedance. This inductor source degenerated amplifier presents a

noiseless resistance for 50Ω for input power match. How we can cancel the imaginary part of complex input impedance so that the LNA presents 50Ω real input resistance at input port.

b) Calculate the NF in absence on gate noise. Neglect gate drain and gate to bulk and gate to source capacitance.

c) Cgd bridges the input and output ports. The reverse isolation of this LNA is very poor. Why reverse isolation is important? Suggest the modification to improve reverse isolation.

Solution: a). From model above we can write

( ) soinsginin Ljicj

iLjLjiV ωω

ωω +⎟⎟⎠

⎞⎜⎜⎝

⎛++=

1 ---------------(1)

gsinmgsmo Cj

igVgiω

1×== --------------------------------------(2)

Substituting (2) in (1)

( )⎥⎥⎦

⎤

⎢⎢⎣

⎡+++=

gs

sm

gssginin C

LgCj

LLjiVω

ω 1



Vin

Rs Lg + Ls

gs

sm C

Lg Zin VgsCgs

Reference: For series RLC Circuit

R L

C VC Vin

RCRL

CL

RQ

o

os ω

ω 11===

and inSC VQV =

frequency of current gain equal 1

( )gs

sm

gssg

in

inin C

LgCj

LLjiVZ +++==

ωω 1

( )gs

sm

gssgin C

LgCj

LLjZ +++=ω

ω 1

For matching Lg + Ls are canceled out by Cgs. So at frequency of interest

( ) ( ) gssgo

gsosgo CLLC

LL+

=⇒=+11 2ω

ωω

And sgs

mS L

CgR =Ω= 50

Notes: a). Ls is typically small and may be realized by the bond wire for source. b). Lg can be implemented by spiral/external inductor.

b). From part a)

( )gs

sm

gssgin C

LgCj

LLjZ +++=ω

ω 1

We can draw this circuit as Here

( ) ( )STS

sgo

gs

SmS

sgoin LR

LL

CLg

R

LLQ

ωωω

+

+=

+

+=

gs

mT C

g≅ωQ

gsgs

SmSo

in

CC

LgRQ

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

ω

1 for match load

gs

SmS C

LgR =



RL Vin

Vout Rs

Ls

Lg

Zin Vgs

gssoin CR

Qω2

1=

Gain

inings VQV =

gs

outm V

Ig =

minin

mgs

in

outm gQ

VgV

VI

G ===

minm gQG =

so, Lmin

out RGVV

−= where minm gQG =

Noise Figure:

sourceinputtodueoutputatpowernoiseoutputatpowernoiseTotal

F =

For this calculation we ignore channel noise.

OUTnRS

OUTnD

OUTnRS

OUTnDOUTnRS

VV

VVVF

,2

,2

,2

,2

,2

1+=+

=

LDnOUTnD RiV 2,

2,

2 = fgkTi mDn Δ= γ4,2

LmRSnOUTnRS RGVV 22,

2,

2 = fkTRV SRSn Δ= 4,2 & minm gQG =

2222,

22,1

LminRSn

LDn

RgQV

RiF += mDn gkTi γ4,

2 = , SRSn kTRV 4,2 =

21

inSm QRgF

γ+=

Notes: - Very good NF value - Narrow band matching

- NF ↓with 2Q

- The Q is dependent upon Lg + Ls, Ls usually small so Q depends mainly upon Lg



VDD

RL

VS Vout Rs

Ls

Lg

VDD

LD

VS Rs

Ls

Lg CL RL generates noise so replace

RL with LD so that’s

LDo CL

1=ω

Reverse Isolation

Vout

Lo

VDD

LD

Rs

Ls

Lg

CL

Vb

(Final Design)

Cgd

C). Drawbacks i). The CL can be considered the input capacitance of the following mixer or filter. ii).

Reverse isolation depends upon capacitance between output and input. To make it less the cascode architecture can be used.

Problem-2.6 (HW) Fill-in the Table below, use the data from Problem-2.4, 2.5, 2.6 and 2.7

Type of LNA Zin Noise Factor Gain NF (dB)

Shunt Resistor Rsh 42m Sg Rγ

+ 2m Lg R−

Common Gate

Shunt Feedback

Source Degenerated



a) Calculate the NF for all above amplifiers. Assume γ=2, gm = 20mS, Rs = 50Ω, RF =

500Ω, and Qin = 2. b) Which is the best topology for Narrow Band LNA design at high frequency?

Problem-1.7 (Tutorial) Real Design: We will design the inductor-source-degenerated LNA shown in Fig below to meet the specification outlined for IEEE802.11b standard. The first cut approximate values are calculated as a starting point for simulation. In LAB3: Design of LNA you will take the same design and modify these component values to meet the specification.

LNA Specification:

NF < 2.5 dB, Gain > 15dB, IIP3 > -5dBm, Centre Frequency = 2.4 GHz

S11 < -20dB, S22 < -10dB, Load Capacitance = 1pF

Technology Parameters for 0.35um CMOS: 2 2 20.35 , 170 , 4.6 , 58 , 2eff n ox ox p oxL m C A V C mF m C A Vμ μ μ μ μ γ= = = = =

Solution:

Technology 0.35μm CMOS: ⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

===

==

mLmmFC

VACVAC

effox

oxpoxo

μγ

μμμμ

35.0,2,6.4

,58,1702

22

Design Parameters

NF < 2.5 dB, Gain > 15dB, IIP3 > -5dBm, f0 = 2.4 GHz



Component Description

Ls – Matches input impedance

Lg – Sets the Resonant Frequency fO = 2.4 GHz

M3 – Biasing transistor which forms current mirror with M1

Ld – Tuned output increases the gain and also work as band pass filter with CL

M2 – Isolates tuned input from output to increase reverse isolation, also reduces the effect of Miller capacitance Cgd

CB – BC blocking capacitor chosen to have negligible reactance at fO = 2.4 GHz

RBIAS – Large enough so that its equivalent current noise is small enough to be ignored. (Don’t consider it as voltage noise source. Why??)

Design Procedure

Size of M1:

From the noisy two-port theory (see the course book or lecture notes):

( )Ω

=−=50

115

2CCG gsopt γδαω ----------------------(1)

mmLCCWpFC effOXgsMgs 42/34 1 ≈≈⇒≅ ( not feasible – huge size, huge power ! )

We will not go for global minimum noise figure. Instead, we will look into the constraint power design approach.

Solution:

LNA NF will be optimized for given power that is less than the global minimum.

In this case the optimum transistor width is

Soxeffoopt RCL

Wω3

1=

while the minimum power-constraint NF :

LD RREF

Ls

Lg

M2

Vout M1

CL = 10pF

M3 RBIAS

RS CB Vin

VDD



Tp

Tp FF

ωω

ωω

αγ 6.514.21 min,min, +=⇒+= ---------------(A)

As compared to (A) from (1) we can derive

( )TT

CCFωωγ

ωω 3.211

521 2

min +=−+=

T

Fωω3.21min += -------------------------------------------------(B)

(A) is minimum NF for a given power consumption.

(B) is global minimum noise figure.

In practice the difference is usually 0.5dB to 1dB (no big deal for Lower Power)

Step - 1:

mAII 521 == (Limited Power consumption)

Step - 2:

SoxeffM RCL

W0

1 31

ω=

oM m

Wωμ ××××

=506.435.03

11

⎪⎭

⎪⎬

⎫

⎪⎩

⎪⎨

⎧

==

===Ω=

GHzff

mLVACmmFCR

ooo

effoxn

oxS

4.2,2

,35.0,170,6.4,50 2

πω

μμμ

41 109.3 −×=MW

mWM μ390109.3 41 =×= −

Step - 3:

oxeffMgs CLWC 11 32

=

pFmCgs 41.06.435.039032

1 =×××= μμ

11

1 2 DMM

oxnm IL

WCg ⎟⎠⎞

⎜⎝⎛= μ or

TGS

DMm VV

Ig

−= 1

1

2 (for short channel model)

VmAmgm 43535.0

39017021 =×⎟⎠⎞

⎜⎝⎛××= μ



SecradGpF

VmACg

gs

mT 104

41.043

1

1 ==≈ω

Assuming 2=γ

Now T

oFωω6.51min +=

dBG

GF 55.2104

4.226.51min ≈+=π

dBNF 55.2≈

This NF is very close to the specified value. If we increase ID then Tω should increase slightly as well and hence, a lower NF value can be achieved at expense of more power.

Step - 4:

Source and gate inductance such that they cancel Cgs and set Ω50 input impedance

SecradGfoo 154.222 === ππω

From previous problem

STgs

SmdTransformeS L

CLg

RR ω≅==

nHG

RLT

SS 5.0

10050

≅==ω

nHLS 5.0= can be implemented using the bond wire.

Now 1

20

1

gssg C

LLω

=+

( )nH

pFGLL sg 81.10

41.0151

2 =×

=+

nHLg 10≈

Step - 5:

pFCC

L LLo

d 112 == Q

ω

( )nH

pFGLd 4.4

11512 ≅×

=

nHLd 4.4=



Step - 6:

Size of M3 is chosen to minimize power consumption

mAIkRmW REFM 6.02,70 33 =⇒Ω== μ

Ω= kRBIAS 2 (Large enough so that it’s equivalent current noise can be neglected)

pFCB 10= ( Ω≈ 6.6CX so good value @ 2.4G Ω== 6.62

1

BoB Cf

Xπ

)

Step - 7:

Size M2 = M3

So that they can have shared Drain Area..

(Note: We will simulate same LNA circuit in LAB # 2)

Problem-1.8 (Point to Ponder): Connecting two inductor-source-degenerated LNAs as shown beneath makes a differential LNA. The differential LNA has the advantage of a higher common mode rejection ratio and less sensitivity to the ground inductance variation Ls compared to its single-ended counterpart.

a) Compare intuitively the NF of single ended and differential amplifier if both have same power consumption.

b) If low power is not a parameter on interest, which LNA has lower NF?

Instructions: For hand calculation of NF you can ignore the gate noise of the device and noise generated by the load resistance RL.

Documents

Tutorial1_LNAs