tutorial electronics for photodetectorsndip.in2p3.fr/beaune05/cdrom/Sessions/delataille-tuto.pdf · 20 june 2005 C. de La Taille Tutorial Electronics for photodetectors Beaune 2005

Electronics for photodetectors

BEAUNE 2005

C. de LA TAILLELAL Orsay

[email protected]::/www.lal.in2p3.fr/

20 june 2005 C. de La Taille Tutorial Electronics for photodetectors Beaune 2005 2

Contents

Overview of readout electronicsCharge preamplifiersNoiseAnalog shapingADCsAnalog memoriesDigital signal processing(R)evolution(s) of analog and digital electronics Evolution of technologiesEvolution of ASICs in particle phsycisExamples of designs

Thanks to : Eric Delagnes, Richard Hermel, Pierre Jarron, , Jacques Lecoq, Gisèle Martin, Joel Pouthas, Veljko Radeka, Nathalie Seguin, Jean-Charles Vanel


Overview of readout electronics

Most front-ends follow a similar architecture

Detector Preamp Shaper Analogmemory

ADC

fC V bitsFIFODSP…

V V

Very small signals (fC) -> need amplificationMeasurement of amplitude and/or time (ADCs, discris, TDCs)Thousands to millions of channels


Readout electronics : requirements

Lowcost !

(and even less)

Radiation hardness

Highreliability

High speed

Large dynamic

range

Low power

Lowmaterial

Low noise


Photodetector(s) ©JC Vanel

A large variety, but a similar modelization

6x6 pixels,4x4 mm2

HgTe absorbers, 65 mK12 eV @ 6 keV

APD matrix HPD

SiPM

PMT

CdTe

CMOS


Detector modelization

Detector = capacitance CdPixels : 0.1-10 pFPMs : 3-30pFIonization chambers 10-1000 pFCapa or transmission line?

Signal : current source Pixels : ~100e-/µmPMs : 1 photoelectron -> 105-107 e-Modelized as an impulse (Dirac) : i(t)=Q0δ(t)

Missing :High Voltage biasConnections, groundingNeighboursCalibration…

I in C d

Detector modeilization

Typical PM signal


Reading the signal

Signal Signal = current source Detector = capacitance CdQuantity to measure

• Charge => integrator needed• Time => discriminator + TDC

Integrating on CdSimple : V = Q/Cd« Gain » : 1/Cd : 1 pF -> 10 mV/fCNeed a follower to buffer the voltage…Input follower capacitance : Ca // CdGain loss, possible non-linearitiescrosstalkNeed to empty Cd…

-+

I in C d

Q/Cd

Impulse response


Monolithic active pixels © R Turchetta RAL

Epitaxial layer forms sensitive volume (2-20µm)Charge collection by diffusionCharge collected by N-well

Vreset Vdd

Out

Select

Reset

Column-parallel ADCs

Data processing / Output stage

Rea

dout

con

trol

I2C

co

ntro

l

MAPS readout


Ideal charge preamplifier

ideal opamp in transimpedanceShunt-shunt feedbacktransimpedance : vout/iinVin-=0 =>Vout(ω)/iin(ω) = - Zf = - 1/jω CfIntegrator : vout(t) = -1/Cf ∫ iin(t)dt

« Gain » : 1/Cf : 0.1 pF -> 10 mV/fCCf determined by maximum signal

Integration on CfSimple : V = - Q/CfUnsensitive to preamp capacitance CPATurns a short signal into a long oneThe front-end of 90% of particle physicsdetectors…But always built with custom circuits…

-

+

Cf

I in C d

vout(t) = - Q/Cf

- Q/Cf

Charge sensitive preamp

Impulse responsewith ideal preamp


Non-ideal charge preamplifier

Impulse response withnon-ideal preamp

Finite opamp gainVout(ω)/iin(ω) = - Zf / (1 + Cd / G0 Cf)Small signal loss in Cd / G0 Cf << 1(ballistic deficit)

Finite opamp bandwidthFirst order open-loop gain G(ω) = G0/(1 + j ω/ω0)

• G0 : low frequency gain • G0ω0 : gain bandwidth product

Preamp risetimeDue to gain variation with ωTime constant : τ (tau) = Cd / G0ω0 CfRise-time : t 10-90% = 2.2 τRise-time optimised with wC or Cf


Charge preamp seen from the input

Input impedance with ideal opampZin = Zf / G+1Zin->0 for ideal opmap« Virtual ground » : Vin = 0Minimizes sensitivity to detectorimpedanceMinimizes crostalk

Input impedance with real opampZin = 1/jω G0Cf + 1/ G0ω0 Cf

Resistive term : Rin = 1/ G0ω0 Cf• Exemple : wC = 109 rad/s Cf= 0.1 pF =>

Rin = 10 kDetermines the input time constant :

t = ReqCdGood stability= (…!)

Equivalent circuit :

Cd10pF

Rf100kΩ

Leq100µH

Input impedance or charge preamp


Crosstalk

Capacitive coupling between neighboursCrosstalk signal is differentiated and with same polaritySmall contribution at signal peak Proportionnal to Cx/Cd and preamp input impedanceSlowed derivative if RinCd ~ tp => non-zero at peak

Inductive couplingInductive common ground return“Ground apertures” = inductanceConnectors : mutual inductance


Noise in charge pre-amplifiers

Parallelnoise

Seriesnoise

Noise spectral densityat Preamp output

2 noise generators at the inputParallel noise : ( in2) (leakagecurrents)Series noise : (en

2) (preamp)

Output noise spectral density : Sv(ω) = ( in2 + en

2/|Zd|2 ) / ω2Cf2

= in2 /ω2Cf2 + en

2 Cd2/Cf

2

Parallel noise in 1/ω2

Series noise is flat, with a « noise gain » of Cd/Cf

rms noise Vn

Vn2 = ∫ Sv(ω) dω/2π -> ∞ (!)

Benefit of shaping…


Equivalent Noise Charge (ENC) after CRRCn

Noise reduction by optimising usefulbandwidth

Low-pass filters (RCn) to cut-off highfrequency noiseHigh-pass filter (CR) to cut-off parallelnoise-> pass-band filter CRRCn

Equivalent Noise Charge : ENCNoise referred to the input in electronsENC = Ia(n) enCt/√τ⊕ Ib(n) in* √τSeries noise in 1/√τParalle noise in √τ1/f noise independant of τOptimum shaping time τopt= τc/√2n-1

Peaking time tp (5-100%)ENC(tp) independent of n

Complex shapers are obsolete :Power of digital filteringAnalog filter = CRRC ou CRRC2

Step response of CR RCn shapers

ENC vs tau for CR RCn shapers


Equivalent Noise Charge (ENC) after CRRCn

A useful formula : ENC (e- rms) after a CRRC2 shaper :

en in nV/ √Hz, in in pA/ √Hz are the preamp noise spectral densitiesCtot (in pF) is dominated by the detector (Cd) + input preamp capacitance (CPA)tp (in ns) is the shaper peaking time (5-100%)

ENC = 174 enCtot/√tp (δ) ⊕ 166 in√tp (δ)

Noise minimizationMinimize source capacitanceOperate at optimum shaping timePreamp series noise (en) best with high trans-conductance (gm) in input transistor => large current, optimal size


ENC for various technologies

ENC for Cd=1, 10 and 100 pF at ID = 500 uAMOS transistors best between 20 ns – 2 µs

ParametersBipolar :

gm = 20 mA/VRBB’=25 Ω

en= 1 nV/√HzIB=5uAin = 1 pA/√HzCPA=100fF

PMOS 2000/0.35gm = 10 mA/Ven = 1.4 nV/√HzCPA = 5 pF1/f :


MOS input transistor sizing

Capacitive matching : strong inversiongm proportionnal to W/L √IDCGS proportionnal to W*LENC propotionnal to (Cdet+CGS)/ √gmOptimum W/L : CGS = 1/3 CdetLarge transistors are easily in moderate or weak inversion at smallcurrent

Optimum size in weak inversiongm proportionnal to ID (indep of W,L)ENC minimal for CGS minimal, provided the transistor remains in weak inversion

© P O’Connor BNL


Example of charge preamps

FLC_PHY3 for CALICE Si diodes

18 channels variable gain low noise preampOptimized for Cd=20-100 pFBi-gain shaper Linearity 0.1%Multiplexed output3 000 chips produced in 2003 in 0.8µm

FLC_PHY4Variable gain preamp, variable shaperPulsed powerIncludes 12bit ADC

AmpOPA

OPA

MUX out Gain=1

MUX out Gain=10

1 channel

© J. Fleury


FLC_TECH1 : noise performance

FLC_TECH1 : 0.35µmSeries : en = 1.4 nV/√Hz, CPA = 7 pF 1/f noise : 12 e-/pFParallel : in = 40 fA/√Hz

ENC vs Capacitance tp=100ns

ENC vs peaking time


IDeFIDeF--XX V1.1V1.1 ©O. Limousin

16 channels readout for CdTe detectorLow noise charge preampsOptimized for Cd = 2-5 pFVariable SallenKey shapersPeak detectiondiscriminatorMultiplexed output

1,6 mm

170µmENC=f(Tp) à 200µA

10

100

1000

0.1 1 10

Tp (en µs)

EN

C (e

n e-

)

Cin=47pFCin=0

See talk by O Gevin 22/6


Current preamplifiers :

Transimpedance configurationVout(ω)/iin(ω) = - Rf / (1+Zf/GZd)Gain = RfHigh counting rateTypically optical link receivers

Easily oscillatoryUnstable with capacitive detectorInductive input impedance

Leq = Rf / ωC

Resonance at : fres = 1/2π √LeqCdQuality factor : Q = R / √Leq/Cd

• Q > 1/2 -> ringingDamping with capacitance Cf

• Cf=2 √(Cd/Rf G0ω0)• Easier with fast amplifiers•

Step response of current sensitive preamp

Current sensitive preamp

High speed transimpedance amplifier


Fast transimpedance amplifiersRf= 25k Cf=10fFSiGe process15 GHz gain-bandwidth productSee talk on OPERA_ROC

40 Gb/s transimpedance for optical receiverSimple architecture (CE + CC)SiGe bipolar transistorsCC outside feedback loop« pole splitting »

Open loop frequency response of SiGe amplifier


ADCs : G.D.A.S.A.P. ©L. Dugoujon

The era of G.D.A.S.A.P. : « go digital as soon as possible »Spectacular evolution of ADCs : more bits, faster, less wattsPropelled by evolution of technologies and telecom

Has revolutionnized signal processing

[L. Dugoujon LEB 2002]

1E+4 1E+5 1E+6 1E+7 1E+8 1E+9

Sampling Frequency (Fs) (Hz)

5

10

15

20

25

30

Res

olut

ion

(n)

Sigma Delta Dual

Slope

Audio

SensorsInstrumentation

Successive Approximation Pipelined

Folded

High SpeedBasestation

InstrumentationIF sampling

Flash

Radars,RF

HEP

Resolution vs speed of ADCs in 2002

© L. DugoujonSTm

Integrating the ADCs :


Possible use of IPs (expensive)

Huge effort started in in2p3/CEASeveral designs in institutes10 bit pipeline ADC (LPCC) 10MHz 10 Bit C/2C SAR (LAL) 1 mW 1 MHz10 bit FADC (LAL) 100 MHz

12 bit Wilkinson (CEA,LAL,LPCC)

© J. LecoqPipeline ADC ©J. Lecoq

See poster by B. Genolini

See talk by R. Gaglione 22/6

100 MHz FADC ©V. Tocut


Analog memories

Switched Capacitor Arrays (SCAs)Store signal on capacitors (~pF) Fast write (~ GHz)Slower read (~10MHz)Dynamic range : 10-13 bitsdepth : 100-2000 capsUnsensitive to cap absolute value (voltage write, voltage read)Low powerPossible loss in signal integrity (droop, leakage current)

The base of 90% of digital oscilloscopes !

In

Write

Read Out

Principle of a « voltage-write, voltage-read » analog memory


Example : SAM for HESS2 ©E. Delagnes

Swift Analog Memory3 Gsample/s >10 bits

serial link for configuration set-up+

16 delays / colum

d

d

d

d

q

q

d

d

d

d

q

q

d

d

d

d

q

q

d

d

d

d

q

q

d

d

d

d

q

q

Phase comparator

+ Charge Pump

2 ns pulse in SAM0

chip layout in 0.35µ CMOS

See talk by E. Delagnes 20/6

In +In -

16 columnswck

Buffers

wck


Pipeline 12b 2GHz ©D. Breton

RAM 64k*16bits

ADCout BUS

RAM

MANAGER

4

Oscillator100MHz

DAC

thre

s

8 canaux

8 canaux

4 or 8 channels

Output : Busy or Sync_out channel 0

INTERFACE

data add

R/

Trigger Manager

Time base

Matrix Controller

I.1.c

) V

I.1.b

) G

Analog Inputs

Trigger

Trig_Out Ta

Ts

Stop

Fp

Start_BdTEn_Trig PostTrig

comp

Fast Control Slow Control

Output Enable<4 :1>

CK

AD

C

RAM

Wri

ting

RAM reading

I.1.a

) SP

x 4

Trig_ext

MATACQVMEVME board with

4-8 channels2 GHz – 12 bitsAuto-trigger modeSold by CAEN


Digital filtering © B. Cleland UPenn

Linear sums of sampled signalFinite Impulse Respopnse (FIR)made possible by fast ADCs (or analog memories)…

Signal : s(t)=Ag(t)+bA : amplitudeG(t) : normalised signal shapeB : noiseSampled signal : si=Agi+bi

Filter : weighted sum Σ ai si

ai = Σ R-1ij gi

R = autocorrelation fonctiongi = signal shape (0, 0.63, 1, 0.8, 0.47)S = Σn

i=1 aisi

Sampled signal shape

Autocorrelation function


Exemple : ATLAS “multiple sampling”

Slowing down the signalReduction of series noiseSimilar to a simple integration

Accelererating the signalReduction of pileup noiseSimilar to a differentiation

Measuring the timing

A = (0.17, 0.34, 0.4, 0.31, 0.28)

A = (-0.75, 0.47, 0.75, 0.07, -0.19)

Signal before and after digital filtering

[ATLAS-LArG-080]

©L. Serin


(R)evolution of analog electronics (1)

Acces to microelectronics

6 cm

FET

driverpreamp

Zf

Z0

100 µm

Q2

CfQ1

Q3

Cf

Charge preamp in 0.8µm BiCMOS

Charge preamp in SMC hybrid techno


(R)evolution of analog electronics (2)

ASICs : Application Specific Integrated CircuitsAccess to foundries through multiproject runs (MPW) Reduced development costs : 600-1000 €/mm2

compared to dedicated runs (50-200 k€)Full custom layout, at transistor levelmostly CMOS & BiCMOS

Very widespread in high Energy PhysicsHigh level of integration, limited essentially by powerdissipation and parasitic couplings (EMC)Better performance : reduction of parasiticsBetter reliability (less connections)But longer developpement time

Layout 32ch ASIC

300 mm wafer (IBM)


Processing of ASICs © Intel

From Sand to ICs…


Evolution of technologies

SiGe Bipolar in 0.35µm monolithic processFirst transistor (1949)(Brattain-Bardeen Nobel 56)

5 µm MOSFET (1985) 15 nm MOSFET (2005)First planar IC (1961)


Evolution of CMOS technologies © R. Hermel

Moore’s law : doubling every 2 years

Microprocesseur 4004 8086 i386 Pentium Pentium 4

Année 1971 1978 1985 1993 2000

Nb. Bits 4 16 32 64 64

Horloge (Hz) 108k 10M 33M 66M 1.5G

Mémoire adressable (bytes)

640 1M 16M 4G 64G

Technologie (µm) 10 3 1 0.8 0.18

Nb transistors 2300 29000 275000 3.1M 42M Tension alim (V) 12 5 5 5/3.3 1.3 interne

Pentium 4

4004


« CMOS scaling »

Reduction of dimensions Gate length : L Oxide thickness : tox

Reduction of power suppliesReduction of power dissipation

Improvement of speed in 1/L2

Transconductance : gm α W/LCapacitance : C α WLspeed : FT = gm/C α 1/L2

Reduction of costs (?)Increase of integration density

Radiation hardness in bonus !Less trapping in gaye oxide

Substrat P

Drain

Sour

ce

GateSi-poly

Gate Oxyde SiO2

N+N+

W

L

P

N+N+

VGS

VDS

VSB

Depletion regionChannel

Principle of Nchannel MOSFET


Evolution of CMOS technologies (2)

Differences between analog/mixed signall and digital technologies Very fast evolution of digital technologies (faster design migration)More « perene » analog technologies (SiGe, BiCMOS…) (driven by mobile telecom and automotive)A visible split occuring

More difficult analog design in low voltage« no more headroom for signals »


SiGe technology © R. Hermel

Faster bipolar transistors for RF telecomBetter mobility and FTBetter current gain (beta)Better Early voltageInteresting improvement at low TCompact CMOS (0.25 or 0.35µm) for mixed-signal design


Cost of ASICs ©K. Torki

MPW (multi-project wafers)CMOS 0.35µm (AMS) : 650 €/mm2BiCMOS SiGe 0.35 µm (AMS) : 900 €/mm2CMOS 0.13µ (STm) : 2500 €/mm2CMOS 90 nm (STm) : 5000 €/mm2Usually a few 10 to 100 pieces in a MPW run

Production runsMasks : 91 k€ (CMOS 0.35µm)8“ wafers : 4 k€, useful area : 25 000 mm2 = several thousands of chips

PackagingCeramic : 20-30€/chipPlastic : 2k€ + 1-2 €/chip

Example : chip 10mm2 16 channels100 chips (MPW) : 120€/chip, 7€/channel10 000 chips (4wafers) : 12€/chip < 1€/channel


(R)evolution of digital electronics (1)

From stacks of circuits to FPGAs : progammable gate arrays

2 FPGAs

Pentium processor board

Fastbus controller (1990) D0 LVL2 trigger board (2000)



Schematic -> High level languages(Verilog, VHDL)

Example 8 bit comparator74LS866

VHDL comparator :entity comparator_8 is

port ( raz : in std_logic;

val1,val2 : in std_logic_vector(7 downto 0)

result : out std_logic

);

end entity comparator_8;

architecure archi_& of comparator_8 is

begin

result <= ‘0’ when raz = ‘0’ else

‘1’ when val1 > val2 else

‘0’

end architecture archi_1;



Reduction of digital logic levels1980 : TTL : 0-5 V2000 : LVDS : Low Voltage ( ± 400 mV) Differential SwingBetter signal integrity (EMC)Reduction of power supplies 5V -> 3.3V -> 2.5V -> 1.2V

Components : the revolution of FPGAs : = Field Programmable Arrays (Altera©, Xilinx©)4-40 millions gates (55M in a Pentium4)RISC 32bits processors10 Mbits resident memory2000 pins 1300 I/O (inputs/outputs)300 MHz operation


FPGAs as blackhole of digital electronics ?

Memories& FIFOs

Clocks& PLLs

Bus interfaces

(GTL, LVDS…)

DSP blocks, arithmetics

©JP Cachemiche

IP standard interfaces

(Ethernet, USB,PCI..)

RISC processors

Matchingnetworks


Electromagnetic compatibility (EMC-EMI)

Coexistence analog-digitalCapacitive, inductive and common-impedance couplingsA full lecture !A good summary : there is no such thing as « ground », pay attention to current return


Effect of radiations on components

TID : total ionising dose effectsCharge trapping in gate oxideAlleviated in thin oxides (DeepSubMicron DSM)Radiation tolerant layout techniques designed by CERN RD49 in 0.25µm

NIEL : non ionising energy lossCristal damage with neutronsBeta drop in bipolar transistors

SEU : Single Event EffectEffect of large ionising impact : local charge deposition on criticalnodesSEU : single event Upset = bit flipSEL : single Event Latchup : thyristor setting -> destructive !

FEC

FEC

Z (m)

R (m)

Radiation levels in ATLAS (rads/an)

1 Mrad/an 1014 N/cm2

1 krad/an 1011 N/cm2


Radiation hardness : space vs LHC

Space missions LHC experimentsMission Time 10-15 years 10 yearsService Not Possible ImpracticalElectronics Reliability High HighTotal Dose Requirements 10 -100 krad 1 krad - 10 MradNon Ionizing Energy Loss (N) ~0 1013-1015 N/cm2Single Event Upsets IC’s SEU characterised

No Critical SEU Accepted

=> Similar requirements


Summary of radiation effects on components

IONISING(TID)

Gy, rad

NMOS: Vt ↑or ↓PMOS: Vt ↑gm ↓ I leak ↑

Bipolar: β↓

NON IONISING(NIEL)

Fluence or particles/cm2

Atomicdisplacement

CUMULATIVE

e- holepair creation

Bipolar: β↓

Optoelect.

©N. Seguin-Moreau

Single Event Effects(SEE)

Occurrence rateSEE permanent

SEL, SEGR, SEB

SEU (transient)

MOS

[N. Seguin-Moreau Cargèse 2004]


Examples : tracker circuits APV25

High level of intégration 128 preamps/shapers, 128*160 analog pipelinesMode peak & déconvolution, multiplexe’d output, internal calibration …

PerformanceDynamic range ±13 MIP, low dissipation (2µW/ch), Low noise : ~200e-

7.1mm

8.1 mm

Schematic diagram of APV25 readout chip


Example 2 : variable everything © F. Sevkov DESY

100n

10p

12kΩ 4kΩ 24p

12p

3p

in

8p 4p 2p 1p

40kΩ

8-bit

DAC

0-5V

ASIC

Rin=

10kΩ

50Ω

100MΩ2.4p1.2p

0.6p0.3p

0.1p 0.2p

0.4p0.8p

6p

+HV

SiPM

100kΩ 100

nF

SiPM readout chip for CALICE AHCAL0-5V 8 bit DAC for gain adjustmentVariable gain preampVariable gain shaper18 channels, multiplexed output


Example 3 :Towards SoCs… © E. Delagnes CEA

System on Chip (SoC) : multi-fonctionnalityEx : ARS chip for Antarès : pipelines 1GHz, TDC, ADCs…

Photon

VALUE

VALUE

VALUE

OR


Evolution 1 : integrating the detector (MAPS) © R. Turchetta RAL

• 0.5 µm CMOS technology

• Design 1st time right

• Noise < 50 electrons

• Power consumption: <300mW

• 3.3V Operation

• Readout control

• Readout speed: 10 Frames/Second

• Adjustable Gain Column Amplifiers

• 10 Bit ADC/Column

• Alternative analogue output

• Parallel digital output

• I2C control system

• Rad Tolerant Design, Triple d d i

Column

525 by 525 array of

25µm pixels

RAL Camera-on-a-chip


Evolution 1 : integrating the detector (TFA) © P. Jarron CERN


anode wire

pad plane

drift region88µs

L1: 5µs200 Hz

PASA ADC DigitalCircuit RAM

8 CHIPS x

16 CH / CHIP

8 CHIPSx

16 CH / CHIP

CUSTOM IC(CMOS 0.35µm) CUSTOM IC (CMOS 0.25µm )

DETECTOR FEC (Front End Card) - 128 CHANNELS(CLOSE TO THE READOUT PLANE)

FEC (Front End Card) - 128 CHANNELS(CLOSE TO THE READOUT PLANE)

570132PADS

1 MIP = 4.8 fCS/N = 30 : 1DYNAMIC = 30 MIP

CSA SEMI-GAUSS. SHAPER

GAIN = 12 mV / fCFWHM = 190 ns

10 BIT< 10 MHz

• BASELINE CORR.• TAIL CANCELL.• ZERO SUPPR.

MULTI-EVENTMEMORY

L2: < 100 µs200 Hz

DDL(4096 CH / DDL)

Powerconsumption:

< 40 mW / channel

Powerconsumption:

< 40 mW / channel

gatin

g gr

id

Evolution 2 : integrating the backend © L. Musa CERN

ALICE TPC readout: ALTRO chip (CERN) 8 ch/chipInternal ADC : 10bits 20MHzDigital tail cancelation and baseline correction


Integrating the backend (2) © L. Musa CERN

ALTRO chip (CERN)Detail du digital processing


Conclusion

A real move towards “smart sensors”

micro-electronics getting closer to detectorUnavoidable with increase of channels numberCost reduction

Backend more and more integratedIntegration of ADCSignal processingLoading of parameters

USB

Documents

tutorial electronics for photodetectorsndip.in2p3.fr/beaune05/cdrom/Sessions/delataille-tuto.pdf · 20 june 2005 C. de La Taille Tutorial Electronics for photodetectors Beaune 2005