1
Specifications subject to change without notice. www.taitien.com [email protected] 115 TT Type < for Stratum 3 > 7.0 x 5.0 mm SMD Voltage Controlled Temperature Compensated Crystal Oscillator FEATURE - Typical 7.0 x 5.0 x 1.9 mm ceramic SMD package. - Stratum 3 (Overall ±4.6ppm including 20 years aging.) - CMOS and Clipped Sine wave (without DC-cut capacitor) output optional. TYPICAL APPLICATION - Stratum 3 - Femtocell, Base Stations DIMENSION (mm) SOLDER PAD LAYOUT (mm) RoHS Compliant Actual Size Pin# Function Vcon:VC-TCXO GND/NC:TCXO 2 1 GND 3 OUTPUT 4 VDD [TOP VIEW] [SIDE VIEW] [BOTTOM VIEW] 5.08 1.90±0.20 0.7±0.12 5.08±0.15 7.00±0.20 5.00±0.20 #4 #4 #3 #3 #2 #1 #1 #2 1.40±0.15 4.00±0.15 0.80±0.15 1.50 1.20 4.20 0.1μF To ensure optimal oscillator performance, place a by-pass capacitor of 0.1μF as close to the part as possible between Vdd and GND pads. Parameter 2.5V 3.3V Min. Max. Min. Max. Unit Supply Voltage Variation (VDD) VDD-5% VDD+5% VDD-5% VDD+5% V Frequency Range 5 45 52 55 5 45 52 55 Standard Frequency MHz ±4.6 ±4.6 ppm _ ±0.14 (-20~+70°C) ±0.28 (-40~+85°C) ±0.14 (-20~+70°C) ±0.28 (-40~+85°C) _ _ _ ppm ppm ppm ±5.0 ±5.0 _ _ 3.5 2.5 6 3.5 2.5 6 _ _ _ ±0.32 ±0.32 _ _ mA _ _ Vp-p 10 KΩ // 10pF 10 KΩ // 10pF Output Level (Clipped Sine Wave) 0.8 90%VDD 90%VDD 10%VDD 10%VDD 0.5 0.8 0.5 100 100 -130 -145 -154 V V Load (CMOS) _ _ _ _ _ _ _ Load (Clipped Sine Wave) Phase Noise @ 10 MHz 100 Hz 1 kHz dBc/Hz 10 kHz Start time _ 2 _ 2 Storage Temp. Range -55 125 -55 125 °C °C 10, 12.8, 16.384, 19.2, 19.44, 20, 25, 26 Frequency Stability (Overall, 20 Years)* Supply Current (CMOS output) Supply Current (Clipped Sine Wave) Duty Control Voltage Range (VCTCXO) Pulling Range (VCTCXO) Vc Input Impedance (VCTCXO) Frequency Stability Vs Temp. Range (Ref. to (FMAX+Fmin)/2) Output Level (CMOS) Output High (Logic “1”) Output Low (Logic “0”) % 15pF 15pF Standard frequencies are frequencies which the crystal has been designed and does not imply a stock position. * Including calibration @ 25°C, supply voltage VDD±5% , load ±10%, reflow soldering, 20 years aging and frequency stability over temperature. + Including 24hours aging , supply voltage VDD±5% and frequency stability over temperature. mSec Operating Temp. Range -20 ~ 70 -40 ~ 85 Holdover Stability + Note: not all combination of options are available. Other specifications may be available upon request. ELECTRICAL SPECIFICATION

TT Type < for Stratum 3 > 7.0 x 5.0 mm SMD Voltage ...15pF 15pF Standard frequencies are frequencies which the crystal has been designed and does not imply a stock position

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Page 1: TT Type < for Stratum 3 > 7.0 x 5.0 mm SMD Voltage ...15pF 15pF Standard frequencies are frequencies which the crystal has been designed and does not imply a stock position

Specifications subject to change without notice.www.taitien.com

[email protected] 115

TT Type < for Stratum 3 >7.0 x 5.0 mm SMD Voltage Controlled Temperature Compensated Crystal OscillatorFEATURE- Typical 7.0 x 5.0 x 1.9 mm ceramic SMD package.- Stratum 3 (Overall ±4.6ppm including 20 years aging.)- CMOS and Clipped Sine wave (without DC-cut capacitor) output optional.

TYPICAL APPLICATION- Stratum 3- Femtocell, Base Stations

DIMENSION (mm) SOLDER PAD LAYOUT (mm)

RoHS Compliant

Actual Size

Pin# FunctionVcon:VC-TCXOGND/NC:TCXO

2

1

GND 3 OUTPUT 4 VDD

[TOP VIEW]

[SIDE VIEW]

[BOTTOM VIEW]

5.08

1.90

±0.2

0

0.7±

0.12

5.08±0.157.00±0.20

5.00

±0.2

0

#4#4 #3#3

#2 #1#1 #21.40±0.15

4.00

±0.1

5

0.80

±0.1

5

1.50

1.20

4.20

0.1µF

To ensure optimal oscillator performance, place a by-pass capacitor of 0.1μF as close to the part aspossible between Vdd and GND pads.

Parameter 2.5V 3.3VMin. Max. Min. Max. Unit

Supply Voltage Variation (VDD) VDD-5% VDD+5% VDD-5% VDD+5% VFrequency Range 5

45

52

55

5

45

52

55

Standard Frequency MHz

±4.6 ±4.6 ppm

_ ±0.14 (-20~+70°C)±0.28 (-40~+85°C)

±0.14 (-20~+70°C)±0.28 (-40~+85°C)

_

_ _

ppm

ppm

ppm

±5.0±5.0

__

3.5

2.5

63.5

2.5

6__

_ ±0.32 ±0.32_

_

mA

_

_

Vp-p

10 KΩ // 10pF 10 KΩ // 10pF

Output Level (Clipped Sine Wave)

0.8

90%VDD 90%VDD10%VDD 10%VDD

0.5

0.8

0.5

100100-130-145-154

V

V

Load (CMOS)

_

__

_

_

__

Load (Clipped Sine Wave)

kΩPhase Noise @ 10 MHz

100 Hz

1 kHz dBc/Hz10 kHz

Start time

_ 2 _ 2Storage Temp. Range -55 125 -55 125 °C

°C

10, 12.8, 16.384, 19.2, 19.44, 20, 25, 26

Frequency Stability (Overall, 20 Years)*

Supply Current (CMOS output) Supply Current (Clipped Sine Wave)

Duty

Control Voltage Range (VCTCXO) Pulling Range (VCTCXO) Vc Input Impedance (VCTCXO)

Frequency Stability Vs Temp. Range(Ref. to (FMAX+Fmin)/2)

Output Level (CMOS) Output High (Logic “1”) Output Low (Logic “0”)

%

15pF 15pF

Standard frequencies are frequencies which the crystal has been designed and does not imply a stock position.* Including calibration @ 25°C, supply voltage VDD±5% , load ±10%, reflow soldering, 20 years aging and frequency stability over temperature. + Including 24hours aging , supply voltage VDD±5% and frequency stability over temperature.

mSec

Operating Temp. Range -20 ~ 70-40 ~ 85

Holdover Stability +

Note: not all combination of options are available. Other specifications may be available upon request.

ELECTRICAL SPECIFICATION

B0711001
打字機
Rev(10) 06/2021