Implementation of an automatic gain control foraudio signals in an application for

environmental protectionErick Salas

Electronics Engineering SchoolTecnologico de Costa RicaE-Mail: ericksc@gmail.com

Pablo AlvaradoElectronics Engineering School

Tecnologico de Costa RicaE-Mail: palvarado@itcr.ac.cr

Abstract—The protection of forest areas is a complex taskdue to the limited financial support available, especially underconsideration of the forest extensions to be guarded. Hunting, il-legal logging and forest fires are activities that require immediatedetection in order to enable corrective actions, but the numberof forest rangers available are usually insufficient to provide therequired surveillance. Acoustic events produced by chainsawsand guns provide a promising mean to detect the occurrence ofthose illegal activities, if their detection is integrated in the nodesof a Wireless Sensor Network (WSN) spread over the area to beguarded.

The present work concentrates on the acoustic detectioncomponent in a node of a WSN, particularly on a digitalimplementation of the automatic gain control (AGC) system incharge of keeping a signal with a relatively constant output powerlevel in order to simplify the subsequent pattern recognitiontasks. A digital implementation of the AGC on a Spartan 3EFPGA is proposed, which consumes less than 5% of the availablehardware resources. Energy consumption and area are the factorsminimized in the design to comply with the conditions imposedby the forest protection application.

Index Terms—automatic gain control, wireless sensor network,pattern recognition, FPGA, forest protection

I. INTRODUCTION

The environmental costs associated with the destruction offorests —including, among other things, the destruction ofecosystems, the impact on air quality, increased susceptibilityto erosion, and the effects on the dioxide carbon cycle—are nowadays quantifiable. For instance, in Latin Americapayments for environmental services [1] and transferable car-bon trading certificates [2] have been implemented. Illegalactivities of hunting and logging on the one hand, and wildfirescaused by humans or by natural causes, on the other, destroyforests and their associated ecosystems, which has consider-able environmental, social and economical consequences.

One fundamental component in the mitigation of the abovementioned activities is the ability to detect an abnormalevent at the precise site and moment it occurs. Only underconsideration of this information decision makers are enabledto trigger counteracting actions.

In tropical forests the responsibility for surveillance ofthousands of hectares falls upon a few park rangers, with

highly limited resources, thus hindering an effective areaprotection.

Acoustic events produced by chainsaws and guns provide apromising mean to detect the occurrence of illegal logging andhunting, if the detection is integrated in the nodes of a WirelessSensor Network (WSN) spread on the area to be guarded.

A WSN is comprised by a set nodes with limited com-putational power, equipped with sensing and wireless ad-hocnetworking capabilities [3]. These sensor nodes are deployedover the region under study, where each node is responsiblefor capturing from its immediate surroundings data such ashumidity, temperature, air pressure, irradiation, etc. This datais locally processed in the node and send directly or in a multi-hop approach to a sink-node, from which end-users receive andmanipulate the captured data.

The acoustic detection of gunshots and chainsaw motors ona WSN node has to cope with the signal variability caused, onthe one hand, by the diversity of types and conditions of thesound sources (e. g. pistols, rifles, revolvers), and on the otherhand on the particular behavior of the forest as filter, whichalters the acoustic signal from the source in unpredictable wayson its path to the node.

In [4] an architecture for the acoustic pattern recognitionsubsystem has been proposed, which signalizes to the process-ing unit of a WSN node the occurrence of a particular event.The final goal is to implement this subsystem in a low-powerASIC. This allows to set the rest of the node into a low-consumption state until otherwise signalized by the acousticdetector.

A microphone is used to capture the sound on the acquisi-tion block. The signal average power is normalized by an auto-matic gain control module (AGC), before being subsequentlydecomposed into a set of spectral bands or channels by thefilter bank. The power level of each channel is estimated for afixed time interval. The output of all estimators is consideredas an eight-dimensional vector output, which is reduced indimensionality by a linear projection and transformed to asequence of discrete symbols. Then, the symbol sequencesare analyzed by three Hidden Markov Models (HMM) toestimate the probability for each sequence to correspond to

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AcquisitionFilterBank

SymbolGeneration

EnergyEstimation

HMMDecisionMaking

GainControl

Clasification

Acoustinc Pattern Recognition System

Preprocessing Feature Extraction

Figure 1. Block diagram of the acoustic pattern recognition system.

either a shotgun, a chainsaw or the natural forest state. Finally,the decision block reports which of the three states is themost probable. A detailed discussion of the FPGA-basedimplementation of this recognition system is presented in [5].

Power level variations of the acoustic signals arriving tothe node’s microphone are considerable during each day andduring the seasons of the year due to the changes on thepresence of rain, winds, animals and other factors. This levelneeds to be normalized by the AGC module to establish acommon reference for the pattern recognition stages.

Delay

Powerestimation

Errordetection Gain

Figure 2. Diagram of a theoretical feed-forward AGC [6].

Figure 2 shows a block diagram of a theoretical feed-forward AGC system. The power or amplitude of the inputsignal is first computed, and compared to a desired constantreference to produce an error measure, from which a new gainvalue is estimated to scale the delayed input signal [6]. Thepresent work simplifies this model to make it suitable for theWSN application, in its energy and area constraints.

Even though an analog implementation of the AGC isbest suited for the final ASIC implementation, in the currentprototype a digital version is required to be integrated inthe FPGA-based system. In any case, the digital version ofthe power estimation block is also required for the FeatureExtraction subsystem, where the energy levels of the outputsof a digital filter bank need to be computed.

This article is structured as follows. The next sectionreviews previous work. The elements of the proposed AGCstructure are introduced in section III, followed by FPGAimplementation details on section IV. Results obtained withthe system are outlined in section V. Section VI summarizesthe conclusions of this work.

II. PREVIOUS WORK

The broad application range for normalization of signallevels has result in an equally broad spectrum of publications,where a plethora of digital and analog AGC circuits have beenproposed to optimize speed, accuracy, power consumption,

efficiency, spectral shaping, etc. For instance, in [6] differ-ent structures of feed forward (FFAGC) and feed backward(FBAGC) AGC are introduced. FFAGC and FBAGC aresystems with a power estimation block, an error detector, adelay module and an amplifier, but differ in whether theycompute the gain adjustments from the input (as in our case)or from the adjusted output (building a feedback loop).

In [7] an AGC for an GNSS RF receiver is proposed, whichincludes a power detector, a special decoder, an ADC and aprogrammable gain amplifier which is digitally controlled inan AGC loop.

A mixed signal implementation with the digital componentsynthesized on an FPGA was introduced in [8]. That proposalincluded a peak-detector and a floating point data acquisitionsystem in an electro-chemical measurement application.

With the forest monitoring application at hand, it is ofinterest to considerably reduce area and power consumption,while the found systems all focused more or less on accuracy.

III. DIGITAL AGC ARCHITECTURE

The Automatic Gain Control (AGC) proposed on this workis given by

xnor[n] =x[n]

x[n] + knor

where xnor[n] is the normalized sample, x[n] is the input powerestimation for the n-th sample of the input x[n]. The positiveconstant knor avoids division by zero and controls the positionof the inflexion point in the normalization mapping. A blockdiagram for this system is depicted in figure 3; the similaritieswith the theoretical feed forward AGC of figure 2 are clear.

Powerestimation

x[n]

knornorm

Division

Saturationxnor[n]xnor[n]

Figure 3. Block diagram of automatic gain control (AGC) system.

On the AGC loop an approximation of the signal powerlevel is estimated in such a way that multipliers are avoided.

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For this task a non-linear signal envelope detector is used,given by

x[n] =

x[n− 1] + ∆a for |x[n]| < x[n− 1] + ∆a

x[n− 1]−∆d for |x[n]| > x[n− 1]−∆d

|x[n]| otherwise

where the constants ∆a and ∆d limit how fast the computedenvelope is allowed to ascend or descend, respectively. Theserestrictions on the speed of signal change is consistent witha low-pass behavior required in the signal normalization toenhance abrupt changes like the ones occurring in a gunshotevent, but also suppress slow-speed changes like produce buychanges in the biological and environmental changes duringthe day. The low-pass behavior also renders the use of a delaymodule unnecessary.

The use of an constant addition schema (linearcharge/discharge) over the common constant factors used inlinear systems (exponential charge/discharge) was chosen toeliminate the use of multipliers. Furthermore, the additionof constants can be optimally implemented in reconfigurablehardware.

The constant knor is added before entering the fixed pointdivision unit. The given norm controls how many bits will beused to represent the integer part of the results, and hence

xnor[n] = x[n](

2b−i

x[n] + knor

)(1)

for a b bit fixed point number representation with i bits onits integer part and b − i bits on the fractional part, and thusnorm= 2b−i. It has to be noted that since all three terms (norm,x[n] and knor) are positive, the term enclosed in parenthesis in(1) is also positive. However, the signal x[n] is signed and soit is the normalized signal xnor[n].

The hardware area and speed for the division module isimproved by using a look-up table (LUT) instead of thesequential circuitry necessary to perform a generic division.

The saturation module cuts off values out of range assigningthem to the corresponding maximal or minimal representablevalues. It follows the equation

xnor[n] =

2b−1 − 1 for xnor[n] > 2b−1 − 1−2b−1 for xnor[n] < −2b−1

xnor[n] otherwise

where the maximal and minimal values are limited by therange representable with two-complement integer numberswith b bits.

IV. FPGA IMPLEMENTATION

Table I presents the hardware resources utilized by theimplementation of the proposed AGC in an FPGA Spartan 3Efrom Xilinx.

The division module requires most slices within the AGC,for which a total of 4% of the available FPGA resouces arerequired. Sixteen flip-flops are needed to store the previousaverage sample computation, which is 16-bit long. In total 4%

Table IAGC RESOURCE UTILIZATION ON FPGA SPARTAN 3E

Module Slice Flip Flop LUT Mult.18×18

Average estimation 72 16 134 0Divider 124 0 218 0Standard Multiplier 0 0 0 1Saturation 15 0 26 0

AGC (Total) 212 19 283 1Total usage (%) 4 0.204 4 5

of the available slices are used in the AGC. The use of a ROM-based division explains the large number of LUT employed forthis module. The AGC requires 4% of all available LUT in theSpartan 3E. Only one standard multiplier is used to apply thecomputed gain factor to the signal, leaving other 19 multipliersfree for the rest of the acoustic detector.

The implemented AGC uses a sampling frequency of44.1 kHz with b = 16 bits word length.

V. RESULTS

The proposed implementation of the AGC module has beenempirically evaluated. For this task, the acquisition moduleof the whole recognition system (figure 1) is used, whichincludes an analog input for the acoustic signal and a ADC.An analog rectangular pulse is fed into the acquisition module,whose output depicted in figure 4a) is obtained after the usualanti-aliasing LP-filter followed by the ADC. The envelope

(a)

(b)Figure 4. (a) Pulse signal used as input to test the AGC module. (b) Outputof the power estimation module to the input in (a)

follower used as power estimator produces the signal shownin figure 4b), where a ∆a = 16 and a ∆d = 1. This valuesallow a rapid increment of the output and a 16 times slowerdecrement rate. Both signals in figure 4 were captured with

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an oscilloscope from the analog output of a DAC connectedto the digital outputs of the submodules of the AGC.

An additional example to show the operation of the envelopefollower is given in the figure 5. The differences in amplitude

(a)

(b)Figure 5. (a) Pulsating audio signal waveform. (b) Output of the powerestimation module to the input in (a).

are caused by the voltage reference used in the DAC.Figure 6a) shows the first 40 ms of a shotgun audio sample.

Previous to the gun shot (the first 8 ms in the figure) back-ground noise is present. Figure 6b) shows the output of the

(a)

(b)Figure 6. (a) Shotgun signal used for AGC testing. (b) Response of the AGCsystem to the signal in (a)

complete AGC system. On the first 8 ms it is clear that the

AGC has amplified the background noise to a reference level.When the gun shot occurs, the amplification factor cannotabruptly change, since the growth of the envelop is limitedby ∆a. The result is an over-amplified signal that is saturatedon the output from t ≈ 8.5 ms to t ≈ 10 ms. As the timegoes by, the envelope follows the signal growing fast at first,what produces smaller amplification factors, and then startto decrease as the gun shot attenuates, producing a growingamplification factor. Note that on the last 10 ms the signalvaries on the same range as the first samples corresponding tobackground noise.

VI. CONCLUSIONS

The proposed digital feed-forward AGC architecture re-duces the use of standard multipliers by employing an enve-lope follower as power estimation, and by using a LUT-baseddivision implementation. Around 5% of the available resourcesof the Spartan 3E FPGA were required to implement the com-plete AGC system, which leaves enough area to incorporate therest of the shotgun and chainsaw pattern recognition systeminto the same device.

Even though an analog AGC component is better suited forthe final ASIC implementation of the recognition system, theproposed digital version allows to integrate it into an FPGA-based prototype which is flexible enough to be integrated intofield tests.

ACKNOWLEDGEMENT

This work has been part of the 5402 1360 1701 fundedby ITCR and by CYTED’s D2ARS project, UNESCO code:120325;330417;120314;120305.

We want to extend our gratitude to M.Sc. Nestor Hernandezfor his collaboration in this project.

REFERENCES

[1] FAO and REDLACH, “Foro electronico latinoamericano de sistemasde pago por servicios ambientales en cuencas hidrograficas,” FAO andREDLACH, Santiago, Chile, Tech. Rep. Informe Final, 2004.

[2] N. Suarez, “Se arriendan bosques tropicales santander,” VanguardiaLiberal, Febrero 2002.

[3] J. Yick, B. Mukherjee, and D. Ghosal, “Wireless sensor network survey,”Computer Networks, vol. 52, pp. 2292–2330, 2008.

[4] P. Alvarado, N. Hernandez, and M. Hernandez, “D2ARS: Design anddevelopment of applications based on sensor networks,” Final Report ofResearch Project, ITCR, July 2010.

[5] E. Salas, “Real-time recognition of acoustic patterns chainsaw and shotby a FPGA implementation of hidden markov methods,” LicenciatureThesis, Electronics Engineering Deparment, ITCR, Cartago, Costa Rica,April 2010.

[6] Q. Du, M. Jiang, G. Lin, and N. Sun, “ALL-digital AGC in CDMAbase station receiver,” in Proceedings of the International Conference onCommunication Technology ICCT2003, vol. 2, April 2003, pp. 1037 –1041 vol.2.

[7] M. Zhou, C. Fan, D. Chen, and C. Mao, “A compact automatic gaincontrol loop for gnss rf receiver,” in Solid-State and Integrated CircuitTechnology (ICSICT), 2010 10th IEEE International Conference on,November 2010, pp. 284 –286.

[8] X. Chen and M. Du, “FPGA-based floating-point data acquisition systemwith automatic-gain-control and peak-detection for multi-channel electro-chemical measurement,” in 3rd International Conference on BiomedicalEngineering and Informatics (BMEI), vol. 4, October 2010, pp. 1489–1493.

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