Transient Load Tester for Time Domain PDN Analysiselectrical-integrity.com/Paper_download_files/EDICON2017...TLT Implementation and Test Results • TLT voltages measured at inverting

Transient Load Tester for Time Domain PDN Analysis

Ethan Koether (Oracle)

Istvan Novak (Oracle)

Speakers

Ethan KoetherHardware Engineer, [email protected]

He is currently focusing on system power-distribution network design, measurement, and analysis. He received his master's degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology.

Istvan NovakSenior Principal Engineer, [email protected]

Besides signal integrity design of high-speed serial and parallel buses, he is engaged in the design and characterization of power-distribution networks and packages for mid-range servers. He creates simulation models, and develops measurement techniques for power distribution. Istvan has twenty plus years of experience with high-speed digital, RF, and analog circuit and system design. He is a Fellow of IEEE for his contributions to signal-integrity and RF measurement and simulation methodologies.

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2SEPTEMBER 11-13, 2017

Outline

• Motivation for Time Domain PDN Validation

• Transient Load Tester Circuit Design

• The GaN FET

• Transient Load Tester Implementation and Performance

• Conclusion


Outline



• The GaN FET


• Conclusion


Target Impedance Methodology

• Estimates upper bound for rail’s impedance• Voltage fluctuation on rail: ∆𝑉• Maximum current step: ∆𝐼• Target Impedance: 𝑍𝑇𝑎𝑟𝑔𝑒𝑡 = ∆𝑉/∆𝐼

• Valid for linear and time-invariant PDN

• Approximation unless impedance strictly resistive

Impedance magnitude [ohm]

1.E-03

1.E-02

1.E-01

1.E+00

1.E+02 1.E+04 1.E+06 1.E+08

Frequency [Hz]


Time Domain PDN Validation

• Load device under test (DUT) with current who’s waveform follows input voltage waveform.

• For PDN design, can load DUT with worst case current in worst case time to analyze simulated behavior in live system.

𝑡0 𝑡0

Input Voltage Waveform Load Current


Outline



• The GaN FET


• Conclusion


Transient Load Tester (TLT) Circuit Design

𝐼𝐿𝑜𝑎𝑑

GaN FET


Only works in one I-V quadrant

Outline



• The GaN FET


• Conclusion


The Gallium Nitride FET (GaN FET)

Maximum Ratings

VDS

Drain-to-Source Voltage (Continuous) 40

VDrain-to-Source Voltage (up to 10,000 5ms pulses at 150○C)

48

ID

Continuous (TA = 25○C, RθJA = 6○C/W) 53A

Pulsed (25○C, TPULSE = 300 µs) 235

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJ Operating Temperature-40 to 150 ○

CTSTG Storage Temperature

-40 to 150

10SEPTEMBER 11-13, 2017

The Gallium Nitride FET (GaN FET)

• The enhancement mode GaN FET used compared to silicon MOSFETs with similar electrical characteristics: • Faster switching speeds and shorter delay time

• 𝐶𝐺𝐷 is exceptionally small in value• 𝐶𝐺𝑆 is relatively small in value• Lower threshold voltage• Lower package inductance

• Lower 𝑅𝐷𝑆 𝑂𝑁

11SEPTEMBER 11-13, 2017

Outline



• The GaN FET


• Conclusion

12SEPTEMBER 11-13, 2017

TLT Circuit Breadboard Implementation

13SEPTEMBER 11-13, 2017

DUT

Sense Resistors

High Speed Op Amp

TLT Circuit Breadboard Implementation

14SEPTEMBER 11-13, 2017

Buffer Circuit

GaN FET

TLT Implementation and Test Results

• TLT voltages measured at inverting and non-inverting inputs of op amp• For figure below: DUT voltage of 1V, rise/fall times of 100ns

15SEPTEMBER 11-13, 2017


• TLT voltages measured at inverting and non-inverting inputs of op amp• For figure below: DUT voltage of 1V, rise/fall times of 100ns

16SEPTEMBER 11-13, 2017


• Limitation of max operating current of individual circuit can be overcome by operating circuits in parallel

• The measurements below were captured from boards operating alone with 100ns rise/fall time on a DUT supplying 1V

0

5

10

15

20

25

30

35

40

45

50

-0.5 0 0.5 1 1.5 2 2.5

Cu

rren

t St

ep (

A)

Time (μs)

0

5

10

15

20

25

30

35

40

45

50

-0.5 0 0.5 1 1.5 2 2.5

Cu

rren

t St

ep (

A)

Time (μs)

TLT board #1 TLT board #2

17SEPTEMBER 11-13, 2017


• The measurements below were captured from TLT boards #1 and #2 operating in parallel with 100ns rise/fall time on a DUT supplying 1V

• Parallel operation does not affect operational behavior of TLT circuit

0

5

10

15

20

25

30

35

40

45

50

-0.5 0 0.5 1 1.5 2 2.5

Cu

rren

t St

ep (

A)

Time (µs)

18SEPTEMBER 11-13, 2017

TLT Full PCB Implementation

• Side and top views of 16 TLT circuits implemented in CPU BGA plug-in PCB for parallel operation

19SEPTEMBER 11-13, 2017

Loading GaN FETsControl Circuitry

TLT Usage for DC-DC Converter and its PDN’s Time Domain Performance Testing

• Verify PDN can supply necessary current to devices• DUT can be tested with complex waveforms using arbitrary waveform generator• TLT validation uses current pulse train with magnitude equal to max current step

PDN must support• Can vary frequency and duty cycle to explore exacerbations from resonances

20SEPTEMBER 11-13, 2017

TLT Usage for DC-DC Converter and its PDN’s Time Domain Performance Testing

• Verify PDN can supply necessary current to devices• DUT can be tested with complex waveforms using arbitrary waveform generator• TLT validation uses current pulse train with magnitude equal to max current step

PDN must support• Can vary frequency and duty cycle to explore exacerbations from resonances

10

18

260.007

0.008

0.009

0.01

0.011

1E+3 2E+3 3E+3 4E+3 5E+3 6E+3 7E+3 8E+3 9E+3 1E+4

DU

TY C

YCLE

(%

)

MA

X V

OLT

AG

E FL

UC

TUA

TIO

N (

V)

FREQUENCY (HZ)

21SEPTEMBER 11-13, 2017

Outline



• The GaN FET


• Conclusion

22SEPTEMBER 11-13, 2017

Conclusion

• Time domain validation of PDNs important for thorough PDN design and analysis

• The GaN FET offers faster turn on speeds and relatively low threshold voltage compared to silicon MOSFETs with similar electrical characteristics

• Implementation of GaN FET with TLT circuit topology along with parallel operation of TLT circuits delivers fast slew of current at 100ns rise/fall time with virtually unlimited current magnitude

• TLT allows for simulation of worst case loading conditions on a PDN in system within a lab setting for thorough PDN validation.

23SEPTEMBER 11-13, 2017

Acknowledgements

The authors wish to thank for their help Kavitha Narayandass, Alex Miranda, Guy Phillips, Dan Sullivan, Dave Michaud, Bill Tata, Khan Nguyen, Dan Rich, Randy Luckenbihl, Jerome Gentillet, Sandra Brescia, Raja Burney, Gustavo Blando, Laura Kocubinski, all of Oracle Corporation.

24SEPTEMBER 11-13, 2017

More Information

• [email protected]

• [email protected]

25SEPTEMBER 11-13, 2017

mailto:[email protected]

mailto:[email protected]

Thank You!---

QUESTSIONS?

26SEPTEMBER 11-13, 2017


• Inherent fight between 𝑉𝐺𝑆 and 𝑉𝐷𝑆, convergence of which determines operational behavior of TLT

• Figures below captured with DUT supplying 1V, show 𝑉𝐷𝑆, 𝑉𝐺𝑆, and resulting load current at steps of 20A and 40A with 100ns rise and fall times

0

5

10

15

20

25

30

35

40

45

-1 0 1 2 3

Cu

rren

t (A

)

Time (µs)

VGS(ID=20A) VGS(ID=40A)

0

0.5

1

1.5

2

2.5

3

3.5

4

-1 0 1 2 3

Vo

ltag

e (V

)

Time (µs)

VGS(ID=20A) VDS(ID=20A)

VGS(ID=40A) VDS(ID=40A)

27SEPTEMBER 11-13, 2017


• PCB implementation of TLT circuits operating in parallel demands loading FETs be in close proximity to one another

• Little thermal dependence of TLT operational behavior• Data below captured with TLT operating at 100ns rise/fall time connected to DUT

supplying 1V

0

5

10

15

20

25

0 0.1 0.2 0.3 0.4 0.5

Cu

rren

t Lo

ad S

tep

(A

)

Time (µs)

5 Degree C

10 Degree C

15 Degree C

20 Degree C

25 Degree C

30 Degree C

35 Degree C

40 Degree C

45 Degree C

28SEPTEMBER 11-13, 2017

Documents

Transient Load Tester for Time Domain PDN Analysiselectrical-integrity.com/Paper_download_files/EDICON2017...TLT Implementation and Test Results • TLT voltages measured at inverting