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1 Towards a General Framework for FPGA Based Image Processing using Hardware Skeletons K Benkrid, D Crookes and A Benkrid School of Computer Science, The Queen’s University of Belfast, Belfast BT7 1NN, UK (K.Benkrid, D.Crookes, A.Benkrid)@qub.ac .uk Abstract In this paper, we present our approach to developing a general framework for FPGA based Image Processing. This framework is based on a library of Hardware Skeletons. A hardware skeleton is a parameterised description of a task-specific architecture. A skeleton’s implementation will apply optimisations s pecific to the target hard ware. The library normally contains a range of alternative skeletons for the same task, perhaps tailored for different data represen tations. The library also conta ins high level skele tons for compound operations, whose implementa tion can apply appropriate optimisations. Given a complete algorithm description in terms of skeletons, an efficient hardware configuration is generated automatically. We have developed a library of hardware skeletons for common imag e processing tasks, with optimised implementations specifically for Xilinx XC4000 FPGAs. This paper presents and illustrates our hardware skeleton approach in the context of some common image processing tas ks. It demonstrates o ur approach to the broader problem of achieving optimised hardware configurations while retaining the convenience and rapid development cycle of an application-oriented, high level programming model. Keywords: FPGA, Coprocessor, Hardware Skeletons, Image Processing, High Level Programming. 1. Introduction Many modern image processing applications (such as processing video and very large images) are so computationally demanding that special purpose hardware s olutions need to be considered. Reconfigurable hardware in the form of FPGAs ca n offer the performance advantages of a custom hardware solution, while their reprogrammability makes them multi-

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