Toward Verification Closure

from industrial perspective

Yu-Chin HsuVice President, R&D, Logic Verification Group

Growing Trends

• Exploding Size• Growing Complexity• Unfamiliar IP• 30B Xtor’s theoretically possible in 20~30nm technology today

EmulatorsEmulators

DFD

SimulatorSimulatorssSimulatorSimulatorss

Prototypes

Signal DataSignal Data

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EDA Market Electronic Design Automation (EDA) Software Forecast

Revenue ($M) 2007 2008 2009 2010 2011 2012 2013 CAGR

EDA

4,866.6 4,318.4

4,398.0

4,835.0

5,420.0

6,045.0

6,510.0 8.6%

CAE

2,545.2 2,214.1

2,285.0

2,575.0

2,960.0

3,390.0

3,685.0 10.7%

IC CAD

1,789.9 1,581.2

1,589.0

1,705.0

1,875.0

2,045.0

2,190.0 6.7%

PCB 531.5 523.1 524.0 555.0 585.0 610.0 635.0 4.0%

* Courtesy Gary Smith EDA

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Architecturedesign & verification

Block design& verification Chip design,

Integration &Verification

Siliconfabrication&Test

SystemValidation

Time in Weeks

Systemspec

Firmware design & verification

Application software design & Verification

Implementation and Verification

SiliconSiliconRequirements

Requirements HDDHDD Early RTLEarly RTL Final

RTLFinal RTL

Concept Architecture Implementation Integration Fab Platform integration

TapeoutTapeout

System RTL/Gate prototypeDesign levels

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Drivers to Cope with ComplexityMethodology evolution Parallelism consideration – multi-core Multi-facet consideration – power, performance, visibility, etc.

Methodology revolution Platform design -- Domain specific customization ESL -- Raise the abstraction level to behavior level

Typical Design Process

New SoC Design & Verification Process

ProductionRelease

ProductionRelease

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8

Methodology Moved to Handle Complexity

FPGA

Standardization

customization

Platform

Makimoto’s Wave

Platforms – Most popular design methodology today!• Today most platforms are targeted at single customers and

applications• Software is an important part of the platform

• Abstract away the hardware• Enable the easy deployment of the platform

• Tools are important in platform deployment• Do not need to be as general purpose• More specialized tasks

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Platform-based Design

Central notions• A regular pre-verified collection of IP blocks• Usually customized for specific application domains• One stop shopping for IP

A way to sell silicon• Also means locking a customer in• Think TSMC and the design services around

Industry disaggregating• Think Nokia

• Nokia would rather not be a hardware company• Nokia is a software, design and marketing company• TI is the hardware designer for Nokia• Helps Nokia lower costs and focus efforts

• Nokia wants to know that their application runs on the platform – efficiently and effectively

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However…Something Doesn’t Happen As We Thought

Early ESL attempts failed because they did not target:• The right person• The right starting point• The right objectives

I still don’t think we have a clear picture today• Although it is emerging• Productivity is THE primary driver• Adoption constrained by lack of models

11HiSilicon Verification

Seminar

RTL Simulation Is Still in the Center

However, the execution time IS CONCERN!Technologies are added to improve the performance• Parallelism • Visibility enhancement with performance

cost reductionOther technologies usage increasing but not be able to replace or reduce simulation usage in short term• Hardware• Formal

Verification and Closure

DesignSpecification

Debug &

Desig

n co

mpre

hensio

n

Done

Verification Plan

Test Bench

Stimulus Assertion

CheckerCoverage

NoHDL design

Closure ?

No

Correctly ?

Verificationmanagement

Hardware

Simulation

Formal Yes

Engines

Improve Coverage

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Closure loop

Debug loop

Toward Verification Closure

Language Strategy• HDL/HVL trend

Debug loop -- Detect and fix bugs as early as possible• Fast turnaround time on simulation,

debug and design fix

Closure loop -- Detect and fix verification holes to sign off RTL verification• Measure and improve the coverage

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Language Strategy

Simulator – main methodology, commodityHDL/HVL has merged into one language• SystemC, • e language,• System Verilog – growing

Libraries and methodologies to support testbench development• VMM: initial leading, based on Vera• OVM: rapidly catching up, completely free,

and open (based on IEEE 1800-2005)

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Language Strategy (cont’d)

Assertion language• PSL: based on IBM sugar, focus on

procedure assertion• Used mainly by verification engineers

• SVA: part of System Verilog, provide both procedure and design assertion• Used by design engineers

Adoption of SVA is accelerating as its strong integration with dynamic verification

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Debug LoopSimulator is commodity. Technologies are developed to tackle complexity to improve productivity

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SimulationThe core of logic verification

Debug

Visibility

Enhancement

Diagnosis

StaticAnalysis

Formal Analysis

Formal Verification

VerificationIP

Hardware

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Formal Verification

• Survey in 2007: Does your project use formal "bug hunters"? (of all 818 engineers)

• Don't use : ######################## 74.5% • Mentor 0-In : ### 6.5% • Synopsys Magellan : #### 7.9% • Jasper : ## 4.6% • Real Intent Verix : 1.2%• Cadence ISV/IFV/BlackTie : ### 6.21% • IBM RuleBase : # 2.0% • Atrenta Periscope : 0.5% • OneSpin 360MV : 0.8%

• According to Gary Smith EDA, formal property checking is used by 65% of chip design companies in 2009

SpringSoft Confidential

Top 3 Use Cases Survey

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General Wish List on Formal

Typical complaints: Difficult to use, work for small block, false positive“Bigger, better, faster” technologyCommon constraints

• Constrained random test-benches vs. formalDebugging of assertions

• When an assertion fails, is this because I didn’t write it properly, or because something happened in the RTL?

Whether you have enough assertions• Make sure there are enough assertions to check

everything in your RTL

Closure Loop

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VIP coverageFunctional

coverage

Mutation

coverage

Code coverage

Assertion

coverage

DUV

Testbench

T1

T2

…

Tn

CoverageProducts

simulator

Formal Verification

FunctionalQualification

Emulation

Verification Plan

Closure?

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Coverage Data

Code Coverage• Block, Branch, Expression, FSM Coverage

Functional Coverage• Coverage of variable values, binning, specification of

sampling, and cross products

Mutation-based Coverage• How robust is your testbench environment

Assertion Coverage• Assertion formally covered• Assertion dynamically covered

UCIS High-Level Goals

• UCIS = Unified Coverage Interoperability Standard

• Start with standard terminology definition.

• API design spec draft is available for accessing unified coverage database (UCDB).

• Database is the repository of all coverage information.

• Interoperability standardization is on API, not DB implementation.

• API supports fast read, write and read-modify-write.

• Support merging data and reporting data usage model.

Simulation Static ChecksFormal

VerificationEmulation

Unified Coverage Database

Coverage

binning

UCIS API

UCIS API

Report generation RTL Annotation Test plan update

Coverage Producers

Coverage Consumers

Coverage query

response

•*From UCIS API design spec draft

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Hard Verification Closure Decision

What needs to be covered?

What has been covered?

How to improve the coverage?

How long before we are done?

Closure Loop

Relatively fewer successful commercial tools in the closure loop. Anything improve coverage is helpful.

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Verification-Plan Prepare TB Run Simulation Monitor Results

Global view of verification items• Itemize what needed to be tested ?• How to test them?• How critical are they?

Global view of verification status• What are missing?• How critical are they in the picture?• How to interpret these issues?

Coverage convergence

The Light and the Dark of Moore’s Law

Today’s Chips are Big and Rich!

Summary: Big and Rich

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