Toward system integrationkobaweb/warehouse/6-28-2nakagawa.pdfBV = 13.9 V R ON = 15.7mΩmm2 V G =1 V V G = 3 V 中川コンサルティング事務所 Electron current density Source

中川コンサルティング事務所

Toward system integration車載用BCD on SOI


Two SOI wafer structuresTwo SOI wafer structures

(1) SOI with n+ buried layer （デンソー）

(2) Simple SOI




Substrate bias influence on on-resistance


60V Lateral MOSFET

Accumulation layer

Vsub

1995 IEDM


Toward system integration

• Small warpage: Fine lithography.• CMOS process compatible.• Integration of 4bit MPU was demonstrated in 1995.


without buried layers with buried layers

npn pnp

48mm2 114mm2

Good Bip Tr. Without buried layers


高温動作


High Temperature OperationHigh Temperature OperationLeakage current vs. SOI thickness



LIGBT in thinner SOI exhibits faster switching speedLIGBT in thinner SOI exhibits faster switching speedand less temperature dependenceand less temperature dependence


SOI DiodeSOI Diode


SOI

BU

bulkeff tSS )(11 +

+=ττ

リーク電流少なく、スイッチングスピードは速いリーク電流少なく、スイッチングスピードは速い


Output voltage of bandgap reference circuit

200 200 ooCC operation of operation of bandgapbandgap reference circuitreference circuit

Block diagram


250V 0.5A inverter IC

p+ p+

n-well

n+ n+

p-well

n+p+ p+

n- n

p+ n+n+p

npn-Tr p-MOS n-MOS Lateral IGBT

pn-well

Buried silicon dioxide

Trench

5μm

2μm

200200ooCC OperationOperation of thin SOI power ICsof thin SOI power ICs


Block diagram of inverter IC

High Side Driver

Low Side Driver

LevelShifterControl

Logic

PWMGenerator

MultiProtection

Vcc

Vs

Output

VM

HoleSensorSignalInput U

VW

GND

IGBT FWD


0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 50 100 150 200 250 300

Bandgap reference circuit performance as a function of temperature

Temperature [oC]

Out

put V

olta

ge [V

]


Turn-off waveforms of lateral IGBTat 200oC

Drain Voltage : 50V/divDrain Current :200mA/div

Fall-time=0.5μsec

PWM frequency≧20kHz

Gate voltage : 5V/div


200oC Operation of 250V 0.5A inverter IC

Bootstrap capacitor voltage5V/div

U-phase output current

Hole sensor signal

U-phase low side IGBT voltage

PCIM’98 Japan


ＢＢiiＣＤ技術における微細化に向けた課題ＣＤ技術における微細化に向けた課題

中川明夫

セミコンダクター社

低耐圧ＢＣＤ技術低耐圧ＢＣＤ技術




DMOSDMOS・低いオン抵抗・低いオン抵抗

・破壊に強い！・破壊に強い！

・大電流素子が容易・大電流素子が容易

（ゲート配線：（ゲート配線：PolyPoly--Si Si ←←電流小さい）電流小さい）

なぜＢＣＤ技術か？なぜＢＣＤ技術か？

→→ Power IC Power IC の出力段の出力段DMOS vs. BipolarDMOS vs. Bipolar


Application AreaUp to 100V Supply voltage

Analog

LED DriversLED Drivers

AutomotiveAutomotiveMotor Control Motor Control Audio AmplifiersAudio Amplifiers

SensorSensor

Transistor ArrayTransistor Array

Power Power ManagementManagement

Laser DiodeLaser DiodeDriversDrivers


ＢＣＤの歴史

•DMOSFET Ron Improvement


Vertical DMOS CMOS Bip

Drain

•Smart Power Concept in early 1980’s

Smart Power 縦型ＤＭＯＳ + 制御回路


Smart Power： Vertical DMOShas lost advantage.

BCDBCD：： Lateral DMOSLateral DMOS ::reasonable costreasonable costlarge currentlarge currentmultimulti--outputoutput

Vertical DMOS CMOS Bip

Drain

p+ n+p

n+

n- n+

p

n+n-epi

pn

n-epi

n

n+p-well n-well

n

n+p-wellp-well

n+ n+p+ p+ p+

S GDG S D GS DC EB Cp-MOSn-MOSLateral DMOS npn

ppn n


ＢＣＤ技術横型ＤＭＯＳ + 制御回路

•Smart Power Concept•BCD Technology

0.6μm design rule


1

10

100

10 100

Breakdown Voltage (V)

RonA

(mΩ

mm

2)

Si Limit

: LDMOS: Vertical trench MOS: Bipolar

Lateral DMOS vs. Vertical Trench MOSFET


Up Drain vertical DMOS LDMOS

Lateral DMOS vs. Vertical DMOS

LDMOS: Rds（on） is simply reduced depending on design rule


従来のLDMOS 問題点----Low on-state breakdown voltage

Source

Gate

Drain

n+

p+ n+ p n+

p-epitaxial

p-well n-Resurf

15nm

elec

tric

ally

conn

ecte

d

Drain Voltage [V]

Dra

in C

urre

nt D

ensi

ty

[ ×10

4A

/cm

2]

VG = 0 VVBV = 30.2 V

0 10 20 300.0

2.0

1.0

VG = 5 VVBV = 13.9 VRON = 15.7mΩmm2

VG=1 V

VG = 3 V


Electron current density

Source Gate Drain

negative

S G D

Net charge distribution

Vg=5V


Net positive Resurf charge Net positive Resurf charge ρρnetnetunder a drain current of under a drain current of IIDD

ρnet = ρResurf dose − ΙD / qvs

ρResurf dose : original Resurf dose q : elementary electric charge vs : electron saturation velocity


Adaptive Adaptive ResurfResurf----- Improvement of on-state breakdown voltage

SourceGate

Drain

n+

p+ n+ p n+p-well Resurf

LOCOS

p-epi

Conventional

Improved LDMOS with Adaptive Resurf


Adaptive Resurf conceptNet space charge distribution

S G DVg=5V

negative

positive

negative

S G D

Conventional Adaptive Resurf


Adaptive Resurf concept

ConventionalResurf

Adaptive Resurf

Off-state (Vg = 0 V)

compensated

positive

On-state (Vg = 5 V)

positive

neutral


Effects of Adaptive Effects of Adaptive ResurfResurf

Conventional LDMOS Improved LDMOS


Experimental ResultsI-V characteristics of n-channel LDMOS

15V LDMOS

0

20

40

60

0 5 10 15

Drain voltage (V)

Dra

in c

urre

nt (m

A)

Vgs=5V

Vgs=4V

Vgs=3V

Vgs=2V

Vgs=1VD

rain

Cur

rent

（m

A)

Drain Voltage （V)

Vgs=1V

Vgs=2V

Vgs=3V

Vgs=4V

Vgs=5V

25V LDMOS


I-V characteristics of 25V p-channel LDMOS

Dra

in C

urr

ent

（m

A)

Drain Voltage （V)

Vgs=-2V

Vgs=-3V

Vgs=-4V

Vgs=-5V


Electrical Characteristics for Developed LDMOS

6000V2500VMIL

300V300VESD level EIAJ

28mΩmm2180mΩmm2Rds(on)

30V45VOn-state

Breakdown Voltage

30V70VBreakdown voltage

25V LDMOS60V LDMOS


-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

-5.00E-04 0.00E+00 5.00E-04 1.00E-03 1.50E-03 2.00E-03Time [sec]

Dra

in C

urre

nt [A

]

-1

0

1

2

3

4

5

Gat

e V

olta

ge

(V)

IdVg

Id

Vg

-10

-5

0

5

10

15

20

25

30

35

40

45

-1.00E-05 0.00E+00 1.00E-05 2.00E-05 3.00E-05 4.00E-05

Time [sec]

Vd[V

] Vg

[V]

-0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

Id[A

]Id

Vg

Vd

23µsec

負荷短絡＆ＵＩＳ


Top Metal thickness:1um

1

7

13

19

25

31

37

43

49

55

S_a

S_b

S_cS_d

S_eS_f

D_aD_b

D_cD_d

D_eD_f

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Norm

aliz

ed

Vds

Debi

as

0.8-0.9

0.7-0.8

0.6-0.7

0.5-0.6

0.4-0.5

0.3-0.4

SourceConnect

DrainConnect

Bonding PAD

２Ａｌ

432um

480um１Ａｌ

ＤＳ

大電流化：電極配線抵抗


2nd

Sour

ce M

etal

Lay

er

2nd

Dra

in M

etal

Lay

er

2nd

Sour

ce M

etal

Lay

er

2nd

Dra

in M

etal

Lay

er

Bonding PadW

1mm

1mm

拡大図

1st Metal


100

90

80

70

60

50

40

0 2 4 6 8 102nd aluminum layer thickness

On

resi

stan

ce o

f 1m

m x

1m

m L

DM

OS

(mΩ

mm

2 )

W=500μm

250μm

50μm

シリコン素子抵抗=40 mΩmm2


Cu electroplating - TI


BGA and Bump’sreduces parasitic R & L


Pch LDMOS

Nch LDMOS

Driver Circuits

Bump ball

The chip size ： 20.3mm2

Evaluation PCBChip

12V 10A chip


5V 20A 1chip DCDC Converter


１チップ電源に最適なパワー段が必要

5V系と20V系のパワー段を開発

5V Power CMOS 20V Lateral DMOS

N+P+ N+

LDD N- LDD N-

ch imp

P-Well

P-sub

DrainSource

Gate

N+P+ N+

LDD N- LDD N-

ch imp

P-Well

P-sub

DrainSource

Gate


20V MOSFET 構造

2-step n-implant LDMOS（Adaptive Resurf）

1-step n-implant LDMOS


N-ch LDMOS 特性

000.0E+0

10.0E-3

20.0E-3

30.0E-3

40.0E-3

50.0E-3

60.0E-3

70.0E-3

0 5 10 15 20 25Drain-Source Voltage (V)

Dra

in C

urre

nt I

ds (A

)(a)Nch LDMOS(1-step n-implant)

(b)Nch LDMOS(2-step n-implant)

000.0E+0

10.0E-3

20.0E-3

30.0E-3

40.0E-3

50.0E-3

60.0E-3

70.0E-3

0 5 10 15 20 25Drain-Source Voltage (V)

Dra

in C

urre

nt I

ds (A

)(a)Nch LDMOS(1-step n-implant)

(b)Nch LDMOS(2-step n-implant)

(@Vgs=5V, Channel width=157um)

Avalanche current


大電流素子の特性

Ron :9.7mRon :9.7mΩΩ(@Vgs=5V, Ids=5A)(@Vgs=5V, Ids=5A)

Ron :Ron :19.319.3mmΩΩ(@Vgs=5V, Ids=5A)(@Vgs=5V, Ids=5A)

(effective area =3.6mm2)

(effective area =3mm2)


5V NchMOSArea 3.61mm2

RonA 8.1mΩmm2

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

-70.0E-3 -60.0E-3 -50.0E-3 -40.0E-3 -30.0E-3 -20.0E-3 -10.0E-3 000.0E+0

Vds (V)

Ids

(A

)

Ron=12.4mΩ（Vin=-5V、Ids=-4A）

5V PchMOSArea 3mm2

RonA 30.5mΩmm2

Ron=12.4mΩ

0.0

2.0

4.0

6.0

8.0

10.0

12.0

000.0E+0 10.0E-3 20.0E-3 30.0E-3 40.0E-3 50.0E-3 60.0E-3

VG=3V

3.5V

4V5V

Ron=4.25mΩ

VD (V)

I D(A

)

VD (V)

I D(A

)


PCB

Thick Cu metal in PCB reduces interconnection resistance.

Assembled imageFlip chip

Interconnection resistance can be reduced Interconnection resistance can be reduced by by Bump Technology Bump Technology


Single driver circuit layout

Dra

in C

urre

ntConcentrated Driver Circuit

Gate Current

Parasitic metal layer resistance & capacitance

LDMOS

Parasitic Gate Resistance

LoadSignal Bus Line

Dra

in C

urre

ntD

rain

Cur

rentConcentrated

Driver Circuit

Gate Current


LDMOS


LoadSignal Bus Line

Concentrated Driver Circuit

Gate Current


LDMOS


LoadSignal Bus Line

Gate inter-connection

Single driver

Non-uniform switching


Distributed driver circuit layout

(@Switching frequency=780KHz, Input Voltage=12V, Load resistance=1.2Ω)

Distributed Driver Circuit

LDMOS

Gate Current

Signal Bus Line

Signal Current

Pre-driver circuit

Load

Dra

in C

urre

nt


LDMOS

Gate Current

Signal Bus Line

Signal Current

Pre-driver circuit

Load


LDMOS

Gate Current

Signal Bus Line

Signal Current

Pre-driver circuit

Load

Dra

in C

urre

ntD

rain

Cur

rent

Gate inter-connection

SegmentedLDMOS


Switching waveforms

V(switching node)


Measured efficiency vs. output current


Vin=5V Vout=1.083V fsw=980kHz

20A operation

60

65

70

75

80

85

90

95

100

0 5 10 15 20 2560

65

70

75

80

85

90

95

100

0 5 10 15 20 25

Output Current (A)

Eff

icie

ncy

(%)


Evaluation PCB Board


微細化するパワーＩＣプロセス

0.1um

1.0um

1990 1995 2000 2005 2010

0.6

0.350.3um

0.18

CMOS90nm90nm

0.13


CMOS Logic area reduction

5858％％

4040％％

2121％％

6060％％

0.8μm 0.6μm 0.35μm 0.18μm 0.13μm


5V LDMOSSpec

ific

On-

Res

ista

nce

(mΩ

/mm

2 )

なぜ微細化なのか？


nch-LDMOS On-Resistance

Data from ISPSD(2000 to 2007),VLSA-TSA(2008)


“Innovative lateral field plates by gate fingers on STI

regions in deep submicron CMOS” ISPSD’08A.Heringa, NXP-TSMC Research Center Leuven, Belgium

65nmCMOSプロセスを用いてマスク追加せずにLDMOSを作成する優れた手法。

ドレインのリサーフ条件を満たすためSTIを繰り返し入れることで平均の濃度を下げてリサーフ条

件を実現。今回は更にSTI上にフィールドプレートを設けることでSJと同じ原理でオン抵抗を下げ、

他社の0.18umBCDのLDMOS同等の特性を実現。今後、ファウンドリーを使うことが主流になる

中、優れた手法。

パワーＩＣも65nmの時代へ


ISPSD’09

Jan Sonský, NXP-TSMC Research Center; Gerben Doornbos, Anco Heringa, Michiel van Duuren, NXP Semiconductors;Jesús Pérez-González, NXP-TSMC Research Center

従来型のMOSFETと同等以上の特性可能


TSMCTSMC ファウンドリーの参入ファウンドリーの参入


ISPSD’2000, R. Williams, Advanced Analogic Technologies, Inc.

微細LSIの課題


3.3V

1.8V

1.8V

1.5V

1.2V

1.2V

12V

5V

3.3V


微細CMOSのＣＰＵ／ＳｏＣは消費電力大

ＳｏＣにＤＤコンを搭載して低速で良い回路ブロックの電源電圧を

ダイナミックに下げる。

ＳｏＣ、ＣＰＵの Power Crisis



ＣＰＵ、ＳｏＣのＰｏｗｅｒＣｒｉｓｉｓ


ＣＰＵの高周波化の破綻

ISPSD’08 Plenary “Environmental Trends and Opportunities for Computer Power Delivery”Edward Stanford, Intel



2003.9.1号


PowerWise™ AVS System

SoC

PROCESSORCORE

PLL+REFERENCE OSC

EMBEDDEDMEMORY

HOUSEKEEPINGFUNCTIONS, RTC,

WAKEUPCONTROL….

PWI MASTER

ADVANCED POWERCONTROLLER (APC)

OTHERINTEGRATEDFUNCTIONS

Other EMU

IntegratedFunctions

EMU

PWI SLAVE

SPWISPWI

SCLKSCLK

GNDGND GNDGND

PWROKPWROK

RESETNRESETN

ENABLEENABLE

VBATVBATHPM

Registers

StateControl

I/O Interface

I/O Voltage Regulator

Memory VoltageRegulator

Fixed VoltageRegulator

Core VoltageRegulator (AVS)

Other Voltage Regulators


Voltage Slewing

MPEG4 (with IEM)

10 ms

450 µs

350 mV

300 mV

70 µs


ISPSD’04 “A High Efficiency Ultra-Deep Sub-Micron DC-DC Converter

for Microprocessor Applications”Byron Reed, Jun Chen, Valerian Mayega, Kevin Ovens, and Sami Issa, Texas Instruments

• First pass design of the DC-DC converter was done in a baseline 90nm process.

• It is a discrete converter that uses a serial bus for communication of the voltage level to OMAPTM.

• For future 90nm and 65nm designs the SmartReflexTM DC-DC converter will be integrated with OMAPTM.

• No unique design techniques are used in the 90nm baseline process that will prevent it from being migrated to the 65nm baseline process.

Silicon

NwellNwell

Comp.Pwell

POLYPOLY

Pocket N+ Pocket N+

SILICIDE

SILICIDE

Low Voltage PMOS DE-PMOS

OXIDE

OXIDELDDLD

D P+ P+P+P+ N+N+ STI STISTISTI

NITRIDE


DC-DC Converter Output Stage

• MP1 is an HVG (1.8V) device.

• MN2 is a LV device.

• MDEP2 and MDEN1 are drain extended HVG devices.

• PBIAS is a bias voltage referenced from VBAT.

• Advantages of this cascode structure:

Allows high voltage operation.

Has less off mode leakage.

Has smaller gate capacitance that has to be switched than if a single DE device was used.

VBAT

MP1

MDEP2

MDEN1

MN2

PBIAS

VDD_LV

L

RloadC


Simulated Efficiency VS Load Current

• Vin = 3.6V

• Vout = 1.3V

• PWM mode from 100mA to 400mA

• PFM mode from 100uA to 50mA

• Includes parasitic resistances

50556065707580859095

100

0.0001 0.001 0.01 0.1 1

Load Current (A)

Effic

ienc

y (%

)









APEC 2010 APEC 2010 Special Session Special Session 11.4.2 .4.2 A 60MHz 50W FineA 60MHz 50W Fine--Grain Package Integrated VR Powering a CPU from 3.3V Grain Package Integrated VR Powering a CPU from 3.3V G. G. SchromSchrom, F. , F. FailletFaillet, J. Hahn, Intel, Santa Clara, CA , J. Hahn, Intel, Santa Clara, CA




結論

・エコ社会実現には既存インフラ・システムの

変革が必要であり高耐圧ICが重要な役割を

持つ。

・ＩＴ社会では多数の電源電圧があり、DCDC変換の効率向上が課題。

Documents

Toward system integrationkobaweb/warehouse/6-28-2nakagawa.pdfBV = 13.9 V R ON = 15.7mΩmm2 V G =1 V V G = 3 V 中川コンサルティング事務所 Electron current density Source