Tools for Discovery Digital Pulse Processing for Physics Applications Ganil 2 February 2011 Carlo Tintori

Tools for Discovery

Digital Pulse Processing for Physics Applications

Ganil 2 February 2011

Carlo Tintori

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited

Outline

• Description of the hardware of the waveform digitizers

• Overview on the CAEN Digitizer family

• Use of the digitizers for physics applications

• Comparison between the traditional analog acquisition chains and the new fully digital approach

• DPP algorithms:• Pulse triggering

• Zero suppression

• Pulse Height Analysis

• Charge Integration

• Gamma-Neutron discrimination

• Time measurement

• Multi Channel Scaler


• The principle of operation of a waveform digitizer is the same as the digital oscilloscope: when the trigger occurs, a certain number of samples is saved into one memory buffer (acquisition window)

• However, there are important differences:– no dead-time between triggers (Multi Event Memory)– multi-board synchronization for system scalability– high bandwidth data readout links– on-line data processing (FPGA or DSP)

PRE POST TRIGGER

ACQUISITION WINDOW

Sampling Clock

TRIGGER

Time

TIME STAMPS[0]

S[n-1]

S[1]S[2]S[3]

Memory Buffer

Digitizers vs Oscilloscopes


Highlights

• VME, NIM, PCI Express and Desktop• VME64X, Optical Link (CONET), USB 2.0,

PCI Express Interfaces available• Memory buffer: up to 10MB/ch (max. 1024

events)

• Multi-board synchronization and trigger distribution

• Programmable PLL for clock synthesis• Programmable digital I/Os• Analog output with majority or linear sum• FPGA firmware for Digital Pulse Processing• Software for Windows and Linux


Digitizers Table

MO

DE

L

For

m F

acto

r

Num

ber

of

chan

nels

Max

. S

ampl

ing

Fre

quen

cy (

MS

/s)

N.

Bit

Inpu

t D

ynam

ic

Ran

ge (

Vpp

)

Sin

gle

End

ed /

D

iffer

entia

l Inp

ut

Ban

dwid

th (

MH

z)

Mem

ory

(Msa

mpl

e/ch

)

DP

P f

irmw

are

VME 8 SE, D

Desktop/NIM 4 SE

PCIe 2 SE

VME 8 SE, D

Desktop/NIM 4 SEPCIe 2 SE

x721 VME 8 500 8 2 SE, D 250 2 no

VME 8/4 SE, D

Desktop/NIM 4/2 SE 2/4

PCIe 2 SE

VME 8/4 SE, D

Desktop/NIM 4/2 SE

VME 2 SE, D

Desktop/NIM 1 SE

VME 64

Desktop/NIM 32

VME 32+2

Desktop/NIM 16+1

x724 40 TF, SG

CI, NGx720 250 12 2

0.5; 4

1.25; 10125

1

100 14 0,5; 2.25; 10

250/500 no

nox761 4000

x751

x731 500/1000 8 2

30

x742 5000

x740 65 12 2 SE

600

10

no

no500

0.19; 1.5

7.2; 57.6

1.8; 14.4 / 3.6; 28.8

0.128 (2)

tbd

1101000/2000

no

12 1 SE

ADC

FIXED GAINAMPLIFIER

+

DAC

FPGA(AMC)

SRAMMEMORY

DAUGTHER BOARDS

FPGA(VME)

LOCAL BUS

PLL

CONET

CLK-IN

INT. OSCILL.

MOTHER BOARD

TRG-IN

SYNC-IN

TRG-OUT

GLOBAL TRG

SYNC

SELF TRG

I/Os

CLK-OUT

SAMPLING CLOCK

DAC MONITOR

ANALOGINPUTs

VME/USB

n CHANNELS

Architecture



• Traditionally, the acquisition chains for radiation detectors are made out of mainly analog circuits; the A to D conversion is performed at the very end of the chain

• Nowadays, the availability of very fast and high precision flash ADCs permits to design acquisition systems in which the A to D conversion occurs as close as possible to the detector

• The data throughput is extremely high: it is no possible to transfer row data to the computers and make the analysis off-line!

• On-line digital data processing in needed to extract only the information of interest (Zero Suppression & Digital Pulse Processing)

• The aim of the DPP for Physics Applications is to provide FPGA algorithms able to make in digital the same functions of analog modules such as Shaping Amplifiers, Discriminators, Charge ADCs, Peak Sensing ADCs, TDCs, Scalers, Coincidence Units, etc.

Digitizers for Physics Applications


Traditional chain: example 1charge sensitive preamplifiers

DECAY TIMERISE TIME

TIME Q = ENERGY

PEAK AMPLITUDE = ENERGY

ZERO CROSSING

This delay doesn’t depend on the pulse amplitude

DETECTOR

PREAMPLIFIER

SHAPING AMPLIFIER

TIMING AMPLIFIER

CFD

CFD OUTPUT

DETECTOR

Charge SensitivePreamplifier

SHAPINGAMPLIFIER

ENERGY

POSITION,IDENTIF.

TIMING

COUNTINGSHAPING TIME,GAIN THRESHOLDS

PEAK SENSING ADC

DISCRIMINATOR

TDC

SCALER

LOGICUNIT

Trigger, Coincidence

Fast Out


TIME Q = ENERGY

ZERO CROSSING

DETECTOR

CFD

GATE

DELAYED SIGNALCHARGE

INTEGRATION

• The QDC is not self-triggering; need a gate generator

• need delay lines to compensate the delay of the gate logic

TransimpedancePreamplifier

(optional)

SPLITTER

DETECTOR

ENERGY

POSITION,IDENTIF.

TIMING

COUNTINGTHRESHOLDS

DISCRIMINATOR

TDC

SCALER

LOGICUNIT

Gate

QDCDelayLine

Traditional chain: example 2trans-impedance (current sensitive)

preamplifier


• One single board can do the job of several analog modules

• Full information preserved

• Reduction in size, cabling, power consumption and cost per channel

• High reliability and reproducibility

• Flexibility (different digital algorithms can be designed and loaded at any time into the same hardware)

DETECTORENERGY

SHAPE

TIMING

COUNTINGDPPIN

SAMPLESA/D INTERF

DIGITIZER COMPUTER

VERY HIGH DATA THROUGHPUT

Benefits of the digital approach


Standard Firmware:• common trigger on all channels simultaneously• programmable record length and pre/post trigger• channels self trigger: digital discriminator with programmable

threshold• multi board synchronization (clock, sync and trigger distribution)• trigger time stamps• multi event memory buffers (up to 1024 events)• waveform mode only (raw data)

DPP Firmware• trigger and timing filters for pulse identification and triggering• channels can trigger independently• energy filters for the pulse height analysis (trapezoidal filters)• energy filters for the digital charge integration (digital QDC)• configurable event data format (time and/or energy and/or waveform)• individual trigger propagation on channel basis, also from board to

board• pulse shape analysis (e.g. gamma neutron discrimination)• event data packing for high counting rate

Standard vs DPP firmware


Raw waveform mode vs DPP events

INPUT

TIMINGFILTER

MEAN

ZCROSS

SUM

Trigger

TIME STAMP

CHARGE

BASELINE

S1

S2

S3

S4

TIME STAMP

BASELINE

CHARGE

EVENT DATA

Threshold

Leading Edge

INPUT

S1

S2

S3

S4

S5

S6

S7

Sn

Threshold

Trigger

Acquisition Window

EVENT DATA


Individual vs Common trigger

0

50

100

150

200

250

300

350

0 2000 4000 6000 8000 10000 12000 14000 16000 18000

1 B

IN

=

1.376 K

eV

Time (1 sample = 10ns)

Emulation Mode

InputTrigger

0

50

100

150

200

250

300

350

0 2000 4000 6000 8000 10000 12000 14000 16000 18000

1 B

IN

=

1.376 K

eV


Emulation Mode

InputTrigger

Common Individual

400 ns =

100+100 samples =

300 bytes/event (2ch)

80 ns =

20 samples =

30 bytes/event

empty event


Trigger and timing filter (I)

• Pulse triggering is the basis for all DPP and Zero Suppression algorithms

• Fast Shaping filter: RC-CRN (N=1, 2)

• Immune to baseline fluctuation and low frequency noise (ground loop)

• Pulse identification also with the presence of pile-up

• High frequency noise rejection (RC like mean filter)

• Can operate as a digital CFD

• Zero crossing for precise timing information

• Off-line interpolation to overcome the sampling period granularity

• Zero crossing of CFD can also be used for rise time discrimination


Trigger and timing filter (II)

-5000

0

5000

10000

6000 7000 8000 9000 10000 11000

1 B

IN =

1.3

76 K

eV


Emulation Mode

CFDInput


Zero Suppression

• Data reduction algorithms can be developed to reduce the data throughput:– Full event suppression: one event (acquisition window) is discarded if no pulse is detected inside the window– Zero Length Encoding: only the parts exceeding the threshold (plus a certain number of samples before and after) are saved.

suppressed suppressed suppressed

ZLE threshold

Look BackWindow

Look AheadWindow

Region ofInterest

SAMPLEST T TSAMPLES SAMPLES


DPP for the Pulse Height Analysis (DPP-TF)

• Digital implementation of the shaping amplifier + peak sensing ADC (Multi-Channel Analyzer)

• Charge sensitive preamplifier directly connected to the digitizer

• Implemented in the 14 bit, 100MSps digitizers (mod. 724)

• Use of trapezoidal filters to shape the long tail exponential pulses

• Pile-up rejection, Baseline restoration, ballistic deficit correction

• High counting rate, very low dead time

• Energy and timing information can be combined

• Best suited for high resolution spectroscopy (HPGe and Si detectors)


DPP-TF Block Diagram

DECIMATOR

RC-(CR)N

N = 1,2

COMP

TRAPEZOIDALFILTER

TRG & TIMING FILTER

COMP

ARMED

ZERO

TRIGGER

BASELINEMEAN

a b N

k m M

D

D = 1,2,4,8

Nsbl

Thr

SUB

INPUT

TIME STAMP

ENERGY

ftd Nspk

CLK

PEAKMEAN

COUNTER

b = RiseTime

Nsbl = Baseline Mean

Nspk = Peak meanftd = Flat Top Delay (ballistic deficit)

m = Flat Top

Thr = TRG Threshold

a = Low Pass mean

zero crossing

M = Time Constant (PZ cancellation)K = Shaping Time

TRAPEZOIDTIMINGFILTER

-15000

-10000

-5000

0

5000

10000

8000 10000 12000 14000 16000 18000

1 B

IN =

1.3

76 K

eV


Emulation Mode

TrapezoidInput


Example of trapezoidal filter output

Pile-upTrapezoid Height = Energy


DPP-TF / Analog Chain set-ups

N1470High

VoltageN968

ShapingAmplifier

N957Peak

Sensing ADC

DT572414bit @ 100MSpsDigitizer + DPP-TF

Energy

Energy

Time

Ge / SiC.S. PRE


High Rate spectroscopy (DPP-TF)

• Rise Time Discriminator (RTD)

Detection of pulses piling-up on the rising edge

Cancellation of the sum peaks

Pulse count rate correction (true rate)

• Baseline Restorer

Programmable number of points for the BL calculation

Programmable hold-off for a better BL recovery

Constraints on the pulse separation


DPP-TF: Test Results with CdTe

0

200000

400000

600000

800000

1e+006

0 200 400 600 800 1000

70KHz

0

5000

10000

15000

20000

0 200 400 600 800 1000

200KHz (RTD)200KHz

0

50

100

150

200

250

300

350

0 200 400 600 800 1000

800KHz

70 KHz 200 KHz

Sum Peakswith and

withou RTD

800 KHz


Dead Time (DPP-TF)

• Dead-timeless acquisition (no conversion time)

• Double pulse resolution Rise Time (two pulses separated by at least the rise time can be distinguished)

• The rise time discriminator allows double pulses piling up on the rising edge to be detected and counted twice

• Although pile-up causes the loss of some energies, the DPP-TF is able to get the timestamps of nearly all pulses: true rate can be calculated

• Residual multiple pulses that cannot be distinguished (despite the RTD) can be taken into account on a statistical basis

• Histogram (spectrum) calculated off-line: easy implementation of techniques for the ‘dead-time’ correction (loss of energy counts)

• The number and the position of lost counts is known: they can be dynamically re-distributed on the histogram. This is very important in the cases where the activity is not constant in time.


Individual inter-channel triggering (DPP-TF)• Mainly needed in segmented (cloves) detectors

• One channel triggers itself and also neighbour channels

• Individual TRG-IN and TRG-OUT lines from each channel to the Front Panel GPIO connector (8 inputs + 8 outputs)

• External trigger unit (V1495) for the coincidence matrix implementation

• Can work also between cards

• Available in the new DPP-TF (724 series)

• Can be implemented in the 720 and 751 series as well


Pulse Shape Analysis (DPP-TF)

• Some applications need to perform pulse shape analysis to validate or correct the energy/timestamp information

• Usually a small set of samples (short waveform) is required; for the DPP-TF, this is typically the rising edge

• Unlike the ‘oscilloscope like’ acquisition mode, the recording of this waveform chunk has a little overhead in the readout rate

• Also used to improve the timestamp resolution: just two samples around the CFD zero crossing linearly interpolated off-line permit to make the resolution up to 100 times better than sampling period


DPP-TF: Test Results

FWHM @ 1.33 MeV: 1.98 KeV

• Germanium Detectors at LNL (Legnaro - Italy) in Nov-08 and Feb-09, at GSI (Germany) on May-09, at INFN-MI on Jan-10, in Japan on Feb-10, at Duke University (USA) on Jul-10; Palermo on Jan 2011; resolution = 1.98 KeV @ 1.33 MeV (60Co)

• Silicon Strip (SSSSD and DSSSD) and CsI detectors in Sweden at Lund and Uppsala (ion beam test)

• CdTe at high rate (up to 800KHz) for spectroscopy imaging

• NaI detectors in CAEN (see demo)

• PET in U.S.A.

• Homeland security application using CsI

• BGO detector at ENEA ‘Centro Ricerche Casaccia’ (Rome)

228Th with DSSSD

60Co with Ge


DPP for the Charge Integration(DPP_CI)

• Digital implementation of the QDC + discriminator and gate generator

• Implemented in the 12 bit, high speed digitizers ( Mod. 720(*) )

• Self-gating integration; no delay line to fit the pulse within the gate

• Baseline restoration (pedestal cancellation)

• Extremely high dynamic range


• Energy and timing information can be combined

• Coincidences can be easily applied off-line

• Typically used for PMT or SiPM/MPPC readout(*) Implementation in the Mod751 is a work in progress


DPP-CI Block Diagram

INPUT

a = Low Pass mean

b = RiseTimeThr = TRG Threshold

W = Gate width

Nsbl = Baseline mean

TIMING FILTER

GATE

DELAYED INPUT

D = Delay (Pre-Gate) COMP

DELAY

TRG & TIMING FILTER

TRIGGER

BASELINEMEAN

a b

Nsbl

Thr

SUB

INPUT

TIME STAMP

CHARGE

W

CLK COUNTER

ACCUMULATOR(INTEGRATOR)

DMONOSTABLE

GATE

QLSB = TS * VLSB / 50 = 40 fC (Mod 720)


DPP-CI / Analog Chain set-ups

N1470High

Voltage

DT572012bit @ 250MSpsDigitizer + DPP-CI

Charge

Charge

Time

NaI(Tl)

PMT

Dual TimerN93B

DelayN108A

QDCV792N

CFDN842

TDC V1190 Time

SplitterA315


DPP-CI: Test Results

DPP-CI Analog QDC

Energy (MeV) Res (%) Res (%)

0.481 (137Cs Compton edge)

9.41 1.18 12.80 0.70

0.662 (137Cs Photopeak) 7.01 0.04 8.17 0.04

1.33 (60Co Photopeak) 5.67 0.03 6.66 0.18

1.17 (60Co Photopeak) 5.46 0.02 5.89 0.13

2.51 (60Co Sum peak) 3.82 0.11 4.10 0.24Resolution = FWHM * 100 / Mean

NaI detector and PMT directly connected to the QDC or digitizer


DPP-CI: Other Tests

• Tested with SiPM/MPPC detectors at Univerità dell’Insubria (Como – Italy) and in CAEN (2009/2010):– Dark Counting Rate– LED pulser– Readout of a 3x3mm Lyso Crystal + Gamma source– Readout of a scintillator tile for beta particles

•0.5 ph

•1.5 ph

•2.5 ph

•Th

resho

ld scan


DPP for -n Discrimination

• Digital implementation of the E/E or Rise Time discriminator (both are Pulse Shape Analysis)

• Digital E/E: double gate charge integration (same as DPP-CI but with two gates); applied to fast detectors (typ. organic liquid scintillators)

• Digital Rise Time discrimination: T in the Zero Crossing of two CFDs at 25% and 75%; applied to integrated output (either from C.S. preamp or digital integrator)

• PSA used to discard unwanted events (typ. gammas); good events saved including waveform, energy and time stamp


• Algorithms tested at Duke University on July 2010 (off-line). FPGA implementation just finished. Will be tested next week.


DPP-NG vs DPP-CI

• Dual Gate

• Gate position and length settings with 4 ns granularity (DPP-CI has 8 ns)

• Gate position can be referred to either the threshold crossing or the pulse peak

• PSD parameter QSHORT / (QLONG-QSHORT) can be used to decide whether an event has to be saved or discarded

• Better baseline restoration

• Improved readout (event packing)

• Two Channel coincidence discontinued

• Need big FPGA option!


-n Discrimination Block Diagram (I)

SHORT GATE

LONG GATE

Algorithms tested off-line

Firmware under test

DELAY

BASELINE

BLns

TRGthr

SUBINPUT

TIME STAMP

Q-FAST

CLKTIME

COUNTER

GATE1

ACCUMULATOR(INTEGRATOR)

COMPTRIGGER

BLthr GateWidth1

WAVEFORM

PULSE SHAPEDISCRIMINATOR

GATE2

EV

EN

T B

UIL

DE

R

PSDthr

Q-SLOW

PreTrigger

GateWidth2

OUTDATA


-n Discrimination Block Diagram (II)

T

Algorithms tested off-line

Firmware not planned

DELAY

BASELINE

BLns

TRGthr

SUBINPUT

TIME STAMPCLK

TIME COUNTER

COMP

T1

BLthr

WAVEFORM

PULSE SHAPEDISCRIMINATOR

PreTrigger

CFD DELAY

25% ATTEN

75% ATTEN

SUB

SUB

ZC

ZC

EV

EN

T B

UIL

DE

R

T2

OUTDATA

PSDthr


-n Discrimination: preliminary results (I)


-n Discrimination: preliminary results (II)


-n Discrimination: preliminary results (III)


-n Discrimination: preliminary results (IV)


DPP for Time Measurements

• Digital implementation of the TDC + CFD

• DPP-TF and DPP-CI give time stamps with the resolution of the sampling period (10 ns and 4 ns, = Ts/12); interpolation can improve timing resolution

• Extremely high dynamic range

• Dead-timeless acquisition (no conversion time); can manage long bursts of pulses (theoretical unlimited double pulse resolution)

• Big dependence of the resolution from the rise-time and amplitude of the pulses (V/ T)

S1

S2

S3

S4S4 = ZC time stampResolution = Ts / 12

High Resolution ZC aftermath. Interpolation

Time

INPUT

Timing Filter


ZC timing errors• The timing resolution is affected by three main

sources of noise:– Electronic noise in the analog signal (not

considered here)– Quantization error Eq– Interpolation error Ei

• Both simulations and experimental test demonstrate that there are two different regions:

• When Rise Time > 5*Ts the pulse edge can be well approximated to a straight line, hence Ei is negligible. The resolution is proportional to the rise time and to the number of bits of the ADC.

• When Rise Time < 5*Ts the approximation to a straight line is too rough and Ei is the dominant source of error. The resolution is still proportional to the number of bit but becomes inversely proportional to the rise time. Resolution improvement expected for cubic interpolation.

• The best resolution is for Rise Time = 5*Ts, regardless the type of digitizer

• The resolution is always proportional to the pulse amplitude (more precisely to the slope V/T)

SN

SN+1

TSAMPL

LSBADC

zero

Eq

Ei

ANALOG SIGNAL

LINEAR INTERPOLATION


Preliminary results: Mod724

DELAYAB = (N+0.5) * Ts (worst case)

50 mV

100 mV

200 mV

500 mV

(14 bit, 100 MS/s)

RiseTime (ns)

Std

Dev

(n

s)



50mV

100mV

200mV

500mV

(12 bit, 250 MS/s)


RiseTime (ns)

Std

Dev

(n

s)



50mV

100mV

200mV

500mV

(10 bit, 1 GS/s)


NOTE: the region with Rise Time < 5*Ts (5 ns) is missing in this plot

RiseTime (ns)

Std

Dev

(n

s)


Mod724 vs Mod720 vs Mod751

10 bit, 1 GS/s

12 bit, 250 MS/s

14 bit, 100 MS/s

RiseTime (ns)

Std

Dev

(n

s)

Amplitude = 100 mV


Mod751 @ 2 GS/sS

tdD

ev (

ns)

Amplitude (mV)

2 ps !

RT = 1 ns - worst case

RT = 1 ns - best case

RT = 5 ns

The cubic interpolation can reduce the gap between best and worst case as well as increase the resolution for small signals!


DPP for Pulse Counting (SCA)

• Digital implementation of the discriminator + scaler (Single-Channel Analyzer)

• Can be implemented in the high density digitizers (mod. 740)

• Pulse Triggering: baseline restoration, noise rejection, etc…

• Single or Multi-Channel Energy Windowing

COMPCR-RC

ThrL

INPUT

ACTIVITYCOUNTER

COMP

ThrH

ThrH

ThrL

Documents

Tools for Discovery Digital Pulse Processing for Physics Applications Ganil 2 February 2011 Carlo Tintori