Tools for analysis and evaluation of CPU Performance

Analysis tools for Evaluation and

Performance

Mourad BouachePhD, Computer Architecture

[email protected]

Oracle - Nov, 14-2011

Introduction

Processors are increasingly complex

• More difficult microarchitecturedesign.

Simulator : very important tool

• Understand the instructionbehavior during its execution inprocessor.

Complex Simulator :

• Time for preparation andmodification.

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Introduction

Simulation

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Simulator

Tool

• Simulator : very important tool

• test new concepts

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Simulator

Tool

• Simulator : very important tool

• test new concepts

Three characteristics

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Complexity of microarchitectures

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Modular Simulation

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Speed decreases as complexity increases

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Contribution : vectorization methodology

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Monolithic Simulation

Simplescalar, is the most used (in 70% of articles).This simulator and most other simulators have a seriousdrawback : monolithic

Advantage

• simulation speed

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Monolithic Simulation

Simplescalar, is the most used (in 70% of articles).This simulator and most other simulators have a seriousdrawback : monolithic

Advantage

• simulation speed

Disadvantages

• Difficult to update.

• Difficult to extract and compare the simulator components.

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Monolithic vs Modular

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Modular simulation

Advantages

• Reuse/ exchange and compare simulator modules,

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Modular simulation

Advantages


• Better confidence in simulation (closer to HW),

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Modular simulation

Advantages



• Easier to read.

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Modular simulation

Advantages



• Easier to read.

Main drawback :

• Simulation speed slowdown

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Outline

1 Modular simulation environment

2 Acceleration techniques

3 Vectorization of Simulator Modules

4 Experimental framework

5 Results

6 Scheduling process in SystemC

7 Conclusion & future works.

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Modular simulation environments

• A modular simulation environment describe hierarchically andstructurally the system to simulate.To simulate the entire system, the environment includes ascheduler controlling the performance of different components.

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• A modular simulation environment describe hierarchically andstructurally the system to simulate.To simulate the entire system, the environment includes ascheduler controlling the performance of different components.

• Key benefits :

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Reuse ...

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Compare ...

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Share ...

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Simulation models

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acceleration techniques

Acceleration techniques

• reduction of inputs and simulation programs : MinneSPEC,

• simulation engine optimization : FastSysC 1(speedX 2),

• distribution of simulation : DisT,

• sampling techniques : representative, periodic and

random sampling,

• transition to modeling TTLM :Timed Transaction LevelModeling.

1. Daniel Gracia Perez et al. FastSysC : a fast SystemC engine18/1



• Compromise between accuracy and simulation speed,

2. David Parello, Mourad Bouache, and Bernard Goossens. Improving cycle-level modular simulation by vec-torization. In Rapid Simulation and Performance Evaluation : Methods and Tools (RAPIDO’09)

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• Compromise between accuracy and simulation speed,

• Vectorization 2 is a methodology that can be used withone of these acceleration techniques.

2. David Parello, Mourad Bouache, and Bernard Goossens. Improving cycle-level modular simulation by vec-torization. In Rapid Simulation and Performance Evaluation : Methods and Tools (RAPIDO’09)

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Modular simulation environment

UNISIM 3 : A modular simulation framework

• UNISIM is a modular framework for simulation, each simulatoris divided into several modules, each module corresponding toa hardware block.

3. http ://www.unisim.org/20/1


UNISIM 3 : A modular simulation framework

• UNISIM is a modular framework for simulation, each simulatoris divided into several modules, each module corresponding toa hardware block.

• A module is composed of two parts : state and processes.

3. http ://www.unisim.org/20/1


UNISIM : A modular simulation framework

• A process is defined in a .sim file as a C++ class

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UNISIM : Communication protocol

Communication protocol

• Ports : inports and outports

• Signals

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• Ports : inports and outports

• Signals

3 signals :

• Processes can be sensitive tothe data, the accept andthe enable signals.

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UNISIM : signals

• The simulation engine (SystemC) wakes up the modulesprocess.

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Communication between modules

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Communication between modulesScalability is difficult with a modular simulation, for two factors :

• Communication costs between the simulator modules.

• Awakening process for each communicating module.

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Communication costs

Monolithic Simulator

• Write/read a variable.

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Communication costs

Monolithic Simulator

• Write/read a variable.

Modular Simulator

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A New Communication Protocol

Signals Array

• Reduce the number of signals,

• Several values of data, accept, enable temporarily stored insignals array.

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A New Communication Protocol

Signals Array

• An extension of the communication protocol between modulesis a solution to accelerate a simulation speed.

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Module Vectorization

A simple and systematic procedure

1 vectorize module state and ports,

2 add a loop around the process,

3 add method calls to send() following the addition of forloops.

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Example : Functional Unit

1 class FunctionalUnit : public module2 { public:3 inclock clock;4 inport <instr > in;5 outport <instr > out;6 FunctionalUnit (const char*name): module(name)7 { sensitive_pos_method (start_of_cycle ) << clock;8 sensitive_neg_method (end_of_cycle ) << clock;9 sensitive_method ( on_data_accept ) << in.data << out.accept;

10 }11 void start_of_cycle ()12 { if (pipeline.is_ready ())13 out.data = pipeline.get ();14 else out.data.nothing ();15 }16 void on_data_accept ()17 { if (in.data.know() && out.accept.know())18 { if (! pipeline.is_full() || out .accept)19 in.accept = true;20 else in.accept = false;21 out.enable = out.accept;22 }23 }24 void end_of_cycle ()25 { if (out.accept) pipeline.pop ();26 if (in.enable) pipeline.push(in.data);27 pipeline.run ();28 }29 private:30 Fifo <instr > pipeline;31 };

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Vectorization Procedure1. vectorize module state and ports.

1 class FunctionalUnit : public module2 { public:3 inclock clock;4 inport <instr > in;5 outport <instr > out;6 ...7 private:8 Fifo <instr > pipeline;

1 class FunctionalUnit : public module2 { public:3 inclock clock;4 inport <instr , NBCFG > in;5 outport <instr , NBCFG > out;6 ...7 private:8 Fifo <instr > pipeline[NBCFG];

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Vectorization procedure

2. add a loop around the process.

1 ...2 void start_of_cycle ()3 { if (pipeline.is_ready ())4 out.data = pipeline.get ();5 else out.data.nothing ();6 }7 void on_data_accept ()8 { if (in.data.know() && out.accept.know())9 { if (! pipeline.is_full() || out .accept)

10 in.accept = true;11 else in.accept = false;12 out.enable = out.accept;13 }14 }15 ...

1 ...2 void start_of_cycle ()3 { for (int cfg =0; cfg <NBCFG; cfg ++)4 {5 if (pipeline[cfg ]. is_ready ())6 out.data[cfg] = pipeline[cfg ].get ();7 else out .data[cfg ].nothing ();8 ...9 }

10 }11 void on_data_accept ()12 { if (in.data.know() && out.accept.know())13 { for (int cfg =0; cfg <NBCFG; cfg ++)14 { if (! pipeline[cfg ]. is_full()15 || out.accept[cfg ])16 in.accept[cfg] = true;17 else in.accept[cfg] = false;18 out .enable[cfg ] = out.accept[cfg ];19 ...20 }21 }22 }23 ...

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Vectorization procedure

3. add method calls to send() following the addition of for loops.

1 ...2 void start_of_cycle ()3 { if (pipeline.is_ready ())4 out.data = pipeline.get ();5 else out.data.nothing ();6 }7 void on_data_accept ()8 { if (in.data.know() && out.accept.know())9 { if (! pipeline.is_full() || out .accept)

10 in.accept = true;11 else in.accept = false;12 out.enable = out.accept;13 }14 }15 ...

1 ...2 void start_of_cycle ()3 { for (int cfg =0; cfg <NBCFG; cfg ++)4 {5 if (pipeline[cfg ]. is_ready ())6 out.data[cfg] = pipeline[cfg ].get ();7 else out .data[cfg ].nothing ();8 }9 out.data.send();

10 }11 void on_data_accept ()12 { if (in.data.know() && out.accept.know())13 { for (int cfg =0; cfg <NBCFG; cfg ++)14 { if (! pipeline[cfg ]. is_full()15 || out.accept[cfg ])16 in.accept[cfg] = true;17 else in.accept[cfg] = false;18 out .enable[cfg ] = out.accept[cfg ];19 }20 in.accept.send();21 out .enable.send();22 }23 }24 ...

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Example : Vectorized Functional Unit

1 class FunctionalUnit : public module2 { public:3 inclock clock;4 inport <instr , NBCFG > in;5 outport <instr , NBCFG > out;6 FunctionalUnit (const char*name): module(name)7 { // sensitive list8 sensitive_pos_method (start_of_cycle ) << clock;9 sensitive_neg_method (end_of_cycle ) << clock;

10 sensitive_method ( on_data_accept ) << in.data << out.accept;11 }12 void start_of_cycle ()13 { for (int cfg =0; cfg< NBCFG; cfg ++)14 {15 if (pipeline[cfg ]. is_ready ())16 out.data[cfg] = pipeline[cfg ]. get ();17 else out.data[cfg ]. nothing ();18 }19 out .data.send();20 }21 void on_data_accept ()22 { if (in.data.know() && out.accept.know())23 { for (int cfg =0; cfg< NBCFG; cfg ++)24 { if (! pipeline[cfg ]. is_full() || out.accept[cfg ])25 in.accept[cfg ] = true;26 else in.accept[cfg] = false;27 out .enable[cfg] = out.accept[cfg ];28 }29 in.accept. send();30 out .enable.send();31 }32 }33 void end_of_cycle ()34 { for (int cfg =0; cfg< NBCFG; cfg ++)35 { if (out.accept[cfg ]) pipeline[cfg ]. pop ();36 if (in.enable[cfg ]) pipeline[cfg ].push(in.data);37 pipeline[cfg ].run ();38 }39 }40 private:41 Fifo <instr > pipeline[NBCFG];42 };

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Simulator Vectorization

Multi-cores Simulation

• In our study, we performed simulations of multi-cores : 2, 4, 8,16, 32 and 64.

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OoOSim : Out of Order Simulator

OoOSim 4 modelises a generic superscalar out-of-order processor.The baseline simulator includes a 4-way superscalar core with an L1instruction cache, an L1 write-back data cache, a bus and a dram.

4. Mourad Bouache, David Parello, Bernard Goossens. Acceleration of Modular simulation. In InternationalSupercomputing Conference (ISC09) Hamburg, Germany, June 2009.

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OoOSim : 12 modules

1 Fetcher,

2 AllocatorRenamer,

3 Dispatcher,

4 Scheduler,

5 RegisterFile,

6 Ret-Broadcast and CDBA:Common Data Bus Arbiter,

7 IntegerUnit, FloatingPointUnit and AddressGenerationUnit,

8 LoadStoreQueue,

9 Data caches L1 and L2,

10 Instruction cache L1,

11 Memory DRAM,

12 Reorder Buffer.

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more than 15.000 code lines, 12 connected modules through 187 signals.46/1

Benchmarks

Benchmarks : MiBench

• Simulations were carried out by MiBench, divided into sixsuites targeted areas specific market for embeddedapplications :Automotive, Network, Security, Consumer Devices,

Office Automation, and Telecommunications.

Auto./Industrial Consummer Office Network Security Telecomm.

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Performance evaluation

Simulation machine

• Performance evaluation has been carried out on a cluster of30 Intel Xeon 5148 dual-core processors clocked at2.33GHz with a 4MBytes L2 cache.

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Results : simulation speed (without vectorization)

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simulation speed (with vectorization)

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Results : speedup

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Why ... ?

Instrumentation of the FastSysC code(program)

• Cycle Counters (RDTSC:Read Time Stamp Counter) :

1 The scheduler FastSysC transit time.2 The process time.

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FastSysC transit time(without/with vectorization)

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Conclusion

Results

• To address the need to improve the simulation speed, weproposed a developing modules methodology in a modularsimulator.

• This methodology is based on a new communication signalsprotocol .

The vectorial simulation improves scalability.

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Results Discussion

Vectorization ...

• improves the speedup of the simulation time.

• it allows duplicate resources by limiting the overhead ofscheduler simulation time.

• can be used in conjunction with other techniques toimprove the speed as sampling techniques or reductionof test programs.

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Results Discussion

Vectorization ...

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Conclusion

ConclusionOur contribution aims to improve the simulation speed inmodular simulators, offering a simple and systematicdevelopment based on the vectorization of the simulatormodules.

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Conclusion

Simplescalar is not a multi-core simulator

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Conclusion

Simplescalar is not a multi-core simulator

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In focus

Other idea ...

• VectorizationWe wish to compare the results of this methodology usingTTLM modeling (Timed Transaction Level Modeling).

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Merci, Thank you, Tack

QUESTIONS ?

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Back-up slides

Post-doc research work

• Instruction Level Parallelism : ILPGoal : understand the general structure of an execution andparallelism it offers.

• PerPi : A Tool to Measure Instruction Level Parallelism• http://kenny.univ-perp.fr/PerPi/• A Pin tool, an Intel free programmable tool,• computes the instructions dependency graph,• computes, for each instruction in the run, its instruction cycle in the ideal

machine,• Analysis of the structure of instruction-level parallelism,• Parallelism on loops,• Local and global parallelism,• Parallelism on function ”CALL”.

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Back-up slides

Pin Tool

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Back-up slides

TTLM

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Back-up slides

SystemC and FastSysC

SystemC, Contains a scheduler which manages signals and directsthe process to start. It contains a sequential processes (sensitive tothe clock) and combinatorial process (sensitive to input ports).FastSysC, a mixture of static and dynamic scheduling to avoidunnecessary awakening processes : thus optimize the simulationengine.

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Back-up slides

Monolithic

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Back-up slides

Modular

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Parallel Simulation

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Back-up slides

Sampling I

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Back-up slides

Sampling II

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MiBench

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Use of OoOSim

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Stringsearch

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flight-trace simulation

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execution-driven simulation

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trace-driven simulation

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Unisim Example

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UNISIM History

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Documents

Tools for analysis and evaluation of CPU Performance