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Frontiers 2008 Panel
Georgia Tec, 05-13-08
“T
oo
l V
en
do
r P
ers
pecti
ves –
SysM
LT
hu
s F
ar”
Han
s-P
ete
r H
off
man
n, P
h.D
Ch
ief
Syste
ms M
eth
od
olo
gis
t
Tele
log
ic,
Syste
ms &
So
ftw
are
Mo
delin
g B
usin
ess U
nit
Pe
ter.
Ho
ffm
an
n@
tele
log
ic.c
om
a2
©Telelogic AB
To
ol
Ve
nd
or
Pe
rsp
ec
tiv
es
–S
ys
ML
Th
us
Fa
r
�SysMLdefines the standardized “vocabulary”of the language for model-based
systems engineering. As a standard, this vocabulary needs to cover all possible
applications.
�SysMLdoes not specify, how to apply these “words”.
�Systems engineering is strongly communication-driven.
Systems engineers have to communicate with stakeholders from different
domains, e.g.
-mechanical engineers
-electrical engineers
-software engineers,
-test engineers, and not to forget
-customers, who not necessarily have an engineering background.
�In such an environment it is paramount to keep the language domain
independent and easy understandable.
�Compliance to a standard does not mean that all elements of this standard
have to be applied.
�It is recommended to standardizethe usage of the SysMLwithin the organization,
if a company wants to deploy SysML-based systems engineering.
a3
©Telelogic AB
To
ol
Ve
nd
or
Pe
rsp
ec
tiv
es
–S
ys
ML
Th
us
Fa
r
�In m
any cases, customers -even if they are quite familiar with the SysML-struggle
with the usage of the appropriate SysMLdiagrams because there is an overlap
between the different diagrams.
�Key for a successful usage of the SysMLis a systems engineering process
that is an integral part of the m
odel-driven development (M
DD) process.
�The systems engineering process should define the essential SysMLartifacts
that are needed to enable a seamless transition to the subsequent HW/SW
development, e.g.
Telelogic Integrated System/Embedded Software Development Process Harmony.
�Our recommendation is, that the O
MG, INCOSE, and associated groups should
address this issue in respective forums.
a4
©Telelogic AB
To
ol
Ve
nd
or
Pe
rsp
ec
tiv
es
–S
ys
ML
Th
us
Fa
r
�Key requirement for model-based systems engineering is model execution.
-In the functional analysis phase, model execution assures thatthe requirements
are correct, complete, and unambiguous.
-In the design synthesis phase, model execution verifies and validates the
system architectural design incl. associated interfaces.
�The O
MG is working on this topic. The Telelogic tool Rhapsodyalready
supports m
odel execution. Important is, that model execution does not
require that the user has to write code.
�With regard to m
odel execution, SysMLparametric diagramsalso need to
be executable.
�Currently, engineers put a lot of effort in to produce a decent parametric diagram,
but it does nothing as a result of all this work.
What is gained is an understanding of the m
athematical principles which govern
a particular problem, but it cannot be taken any further.
a5
©Telelogic AB
Bac
ku
p S
lid
es
Rh
ap
so
dy 7
.2
Ad
van
ces in
Syste
ms E
ng
ineeri
ng
a7
©Telelogic AB
Ad
va
nc
es
in
Sys
tem
s E
ng
ine
eri
ng
•OMG SysML™
1.0 enhancements to better organize and
communicate inform
ation effectively
–Requirements Tables, Allocation Tables, N-2 M
atrix
–Value Types, Dim
ensions, Units help in trade study analysis
–XMI 2.1 for SysML
•Independently certified by NIST (National Institute of Standardsand
Technology)
•Im
proved design consistency
–Im
proved user interface to pinpoint design errors in m
odel
–Create customizable checks to ensure compliance to
company/project standards
•Integrated graphical panels validate design correctness
a8
©Telelogic AB
Ta
ble
s a
nd
Ma
trix
Vie
ws
•Organize large amounts of inform
ation concisely
•Requirements tables summarize requirements inform
ation
•Allocation tables show key inform
ation —
how blocks are
allocated
•N-2 m
atrices show how m
odel elements are connected
•Define tables and m
atrices to organize any desired inform
ation
a9
©Telelogic AB
Va
lue
Typ
es
, U
nit
s,
Dim
en
sio
ns
•Model physical dim
ensions and m
easurement units
•Enable trade study analysis of different designs by comparing
units
•Ensure proper units are being used for system integration
and parametrics
•Standard SI
library includes
standard units
a10
©Telelogic ABIm
pro
ve
d M
od
el
Co
ns
iste
nc
y C
he
ck
s
•Check for completeness, model integrity and correctness of the
design
•Design quality into the m
odel
•Configure the check m
odel dialog easily
•Navigate directly to m
odel errors
•Include your own check
scripts to ensure the
design m
eets your
company standards
a11
©Telelogic AB
Gra
ph
ica
l P
an
els
•Create m
ock ups of interface to effectively communicate
intended design behavior to customers
•Easily m
odify, monitor and analyze data values during
sim
ulation to ensure the design is correct early in the process
Harm
on
y/S
E
Mo
del-
Based
Syste
ms E
ng
ineeri
ng
a13
©Telelogic AB
Inte
gra
ted
Syste
m / E
mb
ed
ded
So
ftw
are
Develo
pm
en
t P
rocess Harmony
Model-Driven Development of Embedded Systems
Scen
ari
os
(Su
b-)
Sys
tem
Inte
gra
tio
n &
Tes
t
Sys
tem
Ac
ce
pta
nc
e
Sys
tem
An
aly
sis
& D
es
ign S
W
An
aly
sis
& D
es
ign
SW
Im
ple
me
nta
tio
n
& U
nit
Te
st
Re
qu
ire
me
nts
An
aly
sis
Model / Requirements Repository *
Systems
Engineering
Harmony/SE
Req
uir
em
en
ts
An
aly
sis
Syste
ms
An
aly
sis
& D
esig
n
SW
Im
ple
men
tati
on
& U
nit
Test
Software
Engineering
Harmony/ESW
Mo
du
le
Inte
gra
tio
n &
Test
(Su
b-)
Syste
m
Inte
gra
tio
n &
Test
Syste
m
Ac
cep
tan
ce
System Changes
SW
An
aly
sis
& D
esig
n
Stakeholder
Requirements
•Executable Use Case Models
•Architectural Analysis Model(s)
•Executable System Architecture Model
Software Implementation Model
Software Implementation Model
System Architecture Baseline
•Requirements Models
•Use Case Model
* Configuration Controlled Knowledge
of the System Under Development:
•R
eq
uir
em
en
ts D
ocu
men
tati
on
•R
eq
uir
em
en
ts T
raceab
ilit
y
•D
esig
n D
ocu
men
tati
on
•T
est
Defi
nit
ion
s
a14
©Telelogic AB
Essen
tial S
ysM
L A
rtif
acts
fo
r
Mo
del-
Based
Syste
ms E
ng
ineeri
ng
Para
metr
ic D
iag
ram
Req
uir
em
en
ts D
iag
ram
Blo
ck D
efi
nit
ion
Dia
gra
m
Inte
rnal B
lock D
iag
ram
Use C
ase D
iag
ram
Seq
uen
ce D
iag
ram
Ac
tiv
ity D
iag
ram
Sta
tech
art
Dia
gra
m
SysM
L D
iag
ram
Str
uctu
ral D
iag
ram
sB
eh
av
iora
l D
iag
ram
s
UM
L 2
.1S
ysM
L 1
.0
UML4SysML
a15
©Telelogic AB
Mo
del-
Based
Syste
ms E
ng
ineeri
ng
(Harmony/SE )
Artifact Relationships at the R
equirements Analysis / FunctionalAnalysis Level
1 2..*
Use C
ase D
iag
ram
Use C
ase
1 1..*
Blo
ck 1 1
Seq
uen
ce D
iag
ram
15 ..*
Ac
tiv
ity D
iag
ram
1 1
Str
uctu
re D
iag
ram
Block Definition Diagram
Internal Block Diagram
11
Req
uir
em
en
ts D
iag
ram
1*
Sta
tech
art
Dia
gra
m
Req
uir
em
en
ts A
naly
sis
Fu
ncti
on
al
An
aly
sis
a16
©Telelogic AB
Ke
y O
bje
cti
ves o
f th
e
Mo
del-
Based
Syste
ms E
ng
ineeri
ng
Pro
cess Harmony/SE
�Id
en
tify
/ d
eri
ve r
eq
uir
ed
syste
m f
un
cti
on
ality
�Id
en
tify
asso
cia
ted
syste
m m
od
es a
nd
sta
tes
�A
llo
cate
syste
m f
un
cti
on
ality
/ m
od
es t
o a
ph
ysic
al arc
hit
ectu
re
Scen
ari
os
Sys
tem
An
aly
sis
& D
es
ign
Re
qu
ire
me
nts
An
aly
sis
Systems
Engineering
Harmony/SE
Req
uir
em
en
ts
An
aly
sis
Syste
ms
An
aly
sis
& D
esig
n
Stakeholder
Requirements
a17
©Telelogic AB
Mo
del-
Based
Syste
ms E
ng
ineeri
ng
(Harmony/SE )
Requirements Analysis
Model / Requirements Repository
Sta
keh
old
er
Req
uir
em
en
ts
Syste
m U
se C
ases
Sta
keh
old
er
Req
uir
em
en
ts
Syste
m R
eq
uir
em
en
ts
Links providing traceability
to original requirements
Req
uir
em
en
ts A
naly
sis
Model / Requirements Repository
Sta
keh
old
er
Req
uir
em
en
ts
Syste
m U
se C
ases
Sta
keh
old
er
Req
uir
em
en
ts
Syste
m R
eq
uir
em
en
ts
Syste
m R
eq
uir
em
en
ts
Links providing traceability
to original requirements
Req
uir
em
en
ts A
naly
sis
In t
he R
eq
uir
em
en
ts A
naly
sis
ph
ase, th
e f
ocu
s
is o
n t
he a
naly
sis
of
the p
rocess in
pu
ts.
Cu
sto
mer
req
uir
em
en
ts a
re t
ran
sla
ted
in
to a
set
of
req
uir
em
en
ts t
hat
defi
ne
-w
hat
the s
yste
m m
ust
do
(functional requirements
) an
d
-h
ow
well it
mu
st
perf
orm
(quality of service requirements).
On
ce t
he r
eq
uir
em
en
ts a
re s
uff
icie
ntl
y
un
ders
too
d t
he
y a
re g
rou
ped
in
to Use Cases.
Stakeholder
Requirements
Specification
An
aly
ze
/Re
fin
e
Sta
keh
old
er
Req
’s System
Requirements
Specification (Draft)
System
Requirements
Specification (Draft)
De
fin
e
Syste
m –
Le
ve
l U
se
Ca
ses
De
fin
e
Syste
m –
Le
ve
l U
se
Ca
ses
L
ink
Re
q’s
to U
se
Ca
ses
Lin
k
Re
q’s
to U
se
Ca
ses
Ge
nera
te
Syste
m R
eq
’s
Cre
ate
Tra
cea
bilit
y b
etw
een
Sta
ke
ho
lde
r a
nd
Syste
m R
eq
’s
Ge
nera
te
Syste
m R
eq
’s
Cre
ate
Tra
cea
bilit
y b
etw
een
Sta
ke
ho
lde
r a
nd
Syste
m R
eq
’s
Cre
ate
Tra
cea
bilit
y b
etw
een
Sta
ke
ho
lde
r a
nd
Syste
m R
eq
’s
a18
©Telelogic AB
Mo
del-
Based
Syste
ms E
ng
ineeri
ng
(Harmony/SE )
System Functional Analysis
Links providing traceability
to original requirements
Model / Requirements Repository
Us
e C
ase S
cen
ari
os (
Bla
ck-B
ox)
Syste
m-L
ev
el O
pe
rati
on
s
Syste
m U
se C
ases
Sta
keh
old
er
Req
uir
em
en
ts
Syste
m R
eq
uir
em
en
ts
Sys
tem
Fu
ncti
on
al
An
aly
sis
(Us
e C
ase-B
ase
d)
Re
qu
irem
en
ts A
naly
sis
Syste
m U
se C
as
e M
od
el(
s)
Us
e C
ase S
cen
ari
os (
Bla
ck-B
ox)
Syste
m-L
ev
el O
pe
rati
on
s
Syste
m U
se C
ases
Sta
keh
old
er
Req
uir
em
en
ts
Syste
m R
eq
uir
em
en
ts
Syste
m R
eq
uir
em
en
ts
Sys
tem
Fu
ncti
on
al
An
aly
sis
(Us
e C
ase-B
ase
d)
Re
qu
irem
en
ts A
naly
sis
Syste
m U
se C
as
e M
od
el(
s)
In t
he S
yste
m F
un
cti
on
al
An
aly
sis
ph
ase,
the f
ocu
s is o
n t
he t
ran
sla
tio
n o
f th
e
fun
cti
on
al re
qu
irem
en
ts in
to a
co
here
nt
descri
pti
on
of
sys
tem
fu
ncti
on
s (Operations )
.
Each
use c
ase is t
ran
sla
ted
in
to a
mo
del
an
d t
he u
nd
erl
yin
g r
eq
uir
em
en
ts v
eri
fied
an
d v
alid
ate
d t
hro
ug
h model execution.
Merg
e U
se C
as
e B
locks
in S
uD
Blo
ck
System
Requirements
Specification (Baselined)
[Next
Use C
ase]
[els
e]
UC Internal Block Diagram
UC Internal Block Diagram
Veri
fy /
Vali
date
UC
Mo
del
tro
ug
h M
od
el E
xecu
tio
n
Defi
ne
Po
rts a
nd
In
terf
ace
s
Lin
k
UC
Blo
ck P
rop
ert
ies t
o R
eq
’s
Deri
ve U
C S
cen
ari
os
fro
m U
C F
un
cti
on
al
Flo
w
System
Requirements
Specification (Baselined)
System
Requirements
Specification (Baselined)
[Next
Use C
ase]
[els
e]
UC Internal Block Diagram
UC Black-Box Activity Diagram
UC Black-Box Sequence Diagram
UC Internal Block Diagram
UC StatechartDiagram
Defi
ne
Use C
ase M
od
el
Co
nte
xt
Defi
ne
UC
Fu
ncti
on
al F
low
Deri
ve U
C S
tate
-Ba
sed
Beh
avio
r
fro
m U
C B
B-A
D a
nd
BB
-SD
s
Merg
e U
se C
as
e B
locks
in S
uD
Blo
ck
System
Requirements
Specification (Baselined)
System
Requirements
Specification (Baselined)
[Next
Use C
ase]
[els
e]
UC Internal Block Diagram
UC Internal Block Diagram
Veri
fy /
Vali
date
UC
Mo
del
tro
ug
h M
od
el E
xecu
tio
n
Veri
fy /
Vali
date
UC
Mo
del
tro
ug
h M
od
el E
xecu
tio
n
Defi
ne
Po
rts a
nd
In
terf
ace
s
Lin
k
UC
Blo
ck P
rop
ert
ies t
o R
eq
’s
Lin
k
UC
Blo
ck P
rop
ert
ies t
o R
eq
’s
Deri
ve U
C S
cen
ari
os
fro
m U
C F
un
cti
on
al
Flo
w
System
Requirements
Specification (Baselined)
System
Requirements
Specification (Baselined)
[Next
Use C
ase]
[els
e]
UC Internal Block Diagram
UC Black-Box Activity Diagram
UC Black-Box Sequence Diagram
UC Internal Block Diagram
UC StatechartDiagram
Defi
ne
Use C
ase M
od
el
Co
nte
xt
Defi
ne
UC
Fu
ncti
on
al F
low
Deri
ve U
C S
tate
-Ba
sed
Beh
avio
r
fro
m U
C B
B-A
D a
nd
BB
-SD
s
a19
©Telelogic AB
Mo
del-
Based
Syste
ms E
ng
ineeri
ng
(Harmony/SE )
Design Synthesis
In t
he D
esig
n S
yn
thesis
ph
ase, th
e f
ocu
s is o
n t
he a
llo
cati
on
of
syste
m-l
evel o
pera
tio
ns t
o
a s
yste
m a
rch
itectu
re -
op
tio
nall
y e
lab
ora
ted
th
rou
gh
tra
de s
tud
ies -
an
d o
n t
he d
efi
nit
ion
of
po
rts / i
nte
rfaces a
nd
sta
te-b
ased
beh
avio
r at
the l
ow
est
level o
f th
e s
tru
ctu
ral
deco
mp
osit
ion
.
HW
/SW
Dev
elo
pm
en
t
Model / Requirements Repository
Use
Ca
se
Sce
na
rio
s (
Bla
ck
-Bo
x)
Sc
en
ari
os
(W
hit
e-B
ox
)
Syste
m A
rch
ite
ctu
re M
od
el
Sys
tem
-Le
ve
l O
pera
tio
ns
Links providing traceability
to original requirements
Sys
tem
Fu
nc
tio
na
l A
na
lys
is
(Us
e C
ase
-Base
d)
Des
ign
Syn
the
sis
Deta
ile
d
Arc
hit
ectu
ral
De
sig
n
Arc
hit
ectu
ral
An
aly
sis
(Tra
de
Stu
dy)
Arc
hit
ectu
ral
De
sig
n
Arc
hit
ec
tura
l C
on
ce
pt
All
oc
ate
d
Syste
m-L
ev
el O
pera
tio
ns
Repeated for each Level of
System Architecture Decomposition
Sys
tem
Use
Ca
se
Mo
de
l(s)
Arc
hit
ectu
ral
An
aly
sis
Mo
de
l(s
)
UC
Ac
tiv
ity D
iag
ram
(s)
(Bla
ck
-Bo
x)
Use
Ca
se
Sce
na
rio
s (
Bla
ck
-Bo
x)
HW
/SW
Req
Sp
ec
s (
Bas
eli
ne
)
inc
l. T
est
Sce
na
rio
s
Lo
gic
al
ICD
s
HW
/SW
Dev
elo
pm
en
t
Model / Requirements Repository
Use
Ca
se
Sce
na
rio
s (
Bla
ck
-Bo
x)
Sc
en
ari
os
(W
hit
e-B
ox
)
Syste
m A
rch
ite
ctu
re M
od
el
Sys
tem
-Le
ve
l O
pera
tio
ns
Links providing traceability
to original requirements
Sys
tem
Fu
nc
tio
na
l A
na
lys
is
(Us
e C
ase
-Base
d)
Des
ign
Syn
the
sis
Deta
ile
d
Arc
hit
ectu
ral
De
sig
n
Arc
hit
ectu
ral
An
aly
sis
(Tra
de
Stu
dy)
Arc
hit
ectu
ral
De
sig
n
Arc
hit
ec
tura
l C
on
ce
pt
All
oc
ate
d
Syste
m-L
ev
el O
pera
tio
ns
Repeated for each Level of
System Architecture Decomposition
Sys
tem
Use
Ca
se
Mo
de
l(s)
Arc
hit
ectu
ral
An
aly
sis
Mo
de
l(s
)
UC
Ac
tiv
ity D
iag
ram
(s)
(Bla
ck
-Bo
x)
Use
Ca
se
Sce
na
rio
s (
Bla
ck
-Bo
x)
HW
/SW
Req
Sp
ec
s (
Bas
eli
ne
)
inc
l. T
est
Sce
na
rio
s
Lo
gic
al
ICD
s
System
White-Box Sequence Diagrams
[Next
Level o
f
Deco
mp
osit
ion
]
Leaf Blocks
StatechartDiagram
Defi
ne
Po
rts a
nd
In
terf
aces
[Next
Use C
ase]
System Architecture
Structure Diagram (IBD)
Deco
mp
ose
UC
Bla
ck-B
ox S
eq
uen
ce D
iag
ram
s
Veri
fy
Syste
m A
rch
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Leaf Blocks
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Defi
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System Architecture
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Deco
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System Architecture
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Use Case
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Allo
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Defi
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Parametric Diagram(s)
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Sce
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Lo
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ICD
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