TMP102 低消費電力デジタル温度センサ、SMBusおよび2線 …Diode Temp. Sensor DS A/D Converter OSC Control Logic Serial Interface Config. and Temp. Register Temperature

Diode

Temp.

Sensor

DS

A/D

Converter

OSC

Control

Logic

Serial

Interface

Config.

and Temp.

Register

Temperature

SCL1

3

6

4ALERT

SDA

GND2 5

V+

ADD0

SCL

GND

ALERT

2

4

1

ADD0

V+

6

3

5

0.01 µF

Two-WireHost Controller

TMP102

1.4 V to 3.6 V

SDA

Pullup Resistors

Supply Bypass Capacitor

Supply Voltage

5 k�

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &Community

ReferenceDesign

英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SBOS397

TMP102JAJS306H –AUGUST 2007–REVISED DECEMBER 2018

参参考考資資料料

TMP102 低低消消費費電電力力デデジジタタルル温温度度セセンンササ、、SMBusおおよよびび2線線式式シシリリアアルル・・イインンタターーフフェェイイスス内内蔵蔵、、SOT563パパッッケケーージジ採採用用

1

1 特特長長1• SOT563パッケージ(1.6mm × 1.6mm)はSOT-23

よりもフットプリントで68%小型• 較正なしでの精度

– -25°C～85°Cで2.0°C（最大値）– -40°C～125°Cで3.0°C（最大値）

• 低い静止電流– アクティブ時：10μA（最大値）– シャットダウン時：1μA（最大値）

• 電源電圧範囲：1.4～3.6V• 分解能：12ビット• デジタル出力：SMBus、2線式、I2Cインターフェ

イスと互換• NISTトレース可能

2 アアププリリケケーーシショョンン• 携帯用およびバッテリ駆動のアプリケーション• 電源温度のモニタリング• コンピュータ・ペリフェラルの熱保護• ノートPC• バッテリ管理• オフィス機器• サーモスタット制御• 電気機械的なデバイスの温度• 一般的な温度測定

– 産業用制御– 試験用機器– 医療機器

概概略略回回路路図図

3 概概要要TMP102デバイスは、高精度が必要な場合にNTC/PTCサーミスタの代替品として理想的なデジタル温度センサで

す。このデバイスは、較正や外部部品による信号コンディ

ショニングを必要とせず、±0.5°Cの精度を実現します。デバイス温度センサは線形性が高く、複雑な計算やルック

アップ・テーブルなしに温度を導き出すことができます。オ

ンチップの12ビットADCは、最小で0.0625°Cの分解能があります。

1.6mm × 1.6mmのSOT563パッケージは、SOT-23パッケージよりもフットプリントが68%小さくなります。TMP102デバイスには SMBus™、2線式、I2Cインターフェイスとの互換性があり、最大4つのデバイスを1つのバスに接続できます。このデバイスには、SMBusのアラート機能も搭載されています。デバイスは1.4～3.6Vの電源電圧で動作が規定されており、動作範囲の全体にわたって、最大静止

電流は10µAです。

TMP102デバイスは、通信、コンピュータ、コンシューマ、環境、工業、計測など、さまざまなアプリケーションの広範

囲の温度測定に理想的です。このデバイスは、－40°C～125°Cの温度範囲での動作が規定されています。

TMP102の量産品は、NISTトレース可能なセンサに対して100%テストされ、ISO/IEC 17025基準に合格した較正によりNISTトレース可能な機器によって検証されています。

製製品品情情報報(1)型型番番パパッッケケーージジ本本体体ササイイズズ（（公公称称））

TMP102 SOT563 (6) 1.60mm×1.20mm

(1) 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。

ブブロロッックク図図

http://www-s.ti.com/sc/techlit/SBOS397.pdfhttp://www.tij.co.jp/product/jp/tmp102?qgpn=tmp102http://www.tij.co.jp/product/jp/TMP102?dcmp=dsproject&hqs=pfhttp://www.tij.co.jp/product/jp/TMP102?dcmp=dsproject&hqs=sandbuysamplebuyhttp://www.tij.co.jp/product/jp/TMP102?dcmp=dsproject&hqs=tddoctype2http://www.tij.co.jp/product/jp/TMP102?dcmp=dsproject&hqs=swdesKithttp://www.tij.co.jp/product/jp/TMP102?dcmp=dsproject&hqs=supportcommunityhttp://www.tji.co.jp/tool/jp/TIDA-00156?dcmp=dsproject&hqs=rd

2

TMP102JAJS306H –AUGUST 2007–REVISED DECEMBER 2018 www.tij.co.jp

Copyright © 2007–2018, Texas Instruments Incorporated

目目次次1 特特長長.......................................................................... 12 アアププリリケケーーシショョンン ......................................................... 13 概概要要.......................................................................... 14 改改訂訂履履歴歴................................................................... 25 Pin Configuration and Functions ......................... 46 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 46.2 Handling Ratings....................................................... 46.3 Recommended Operating Conditions....................... 56.4 Thermal Information .................................................. 56.5 Electrical Characteristics........................................... 56.6 Timing Requirements ............................................... 66.7 Typical Characteristics .............................................. 7

7 Detailed Description .............................................. 87.1 Overview ................................................................... 87.2 Functional Block Diagram ......................................... 87.3 Feature Description................................................... 8

7.4 Device Functional Modes........................................ 147.5 Programming........................................................... 15

8 Application and Implementation ........................ 218.1 Application Information............................................ 218.2 Typical Application .................................................. 21

9 Power Supply Recommendations ...................... 2310 Layout................................................................... 23

10.1 Layout Guidelines ................................................. 2310.2 Layout Example .................................................... 23

11 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト ....................... 2411.1 ドキュメントのサポート ............................................. 2411.2 ドキュメントの更新通知を受け取る方法..................... 2411.3 コミュニティ・リソース ................................................ 2411.4 商標 ....................................................................... 2411.5 静電気放電に関する注意事項 ................................ 2411.6 Glossary ................................................................ 24

12 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報 ................. 24

4 改改訂訂履履歴歴資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。

Revision G (September 2018) かからら Revision H にに変変更更 Page

• Changed Absolute Maximum Ratings for voltage at SCL, SDA and ADD0 pin ..................................................................... 4• Changed Absolute Maximum Ratings for voltage at ALERT pin............................................................................................ 4

Revision F (September 2018) かからら Revision G にに変変更更 Page

• Changed input voltage maximum value from: 3.6 V to: 4 V................................................................................................... 4• Changed output voltage maximum value from: 3.6 V to: ((V+) + 0.5) and ≤ 4 V................................................................... 4• Changed Junction-to-ambient thermal resistance from 200 °C/W to 210.3 °C/W ................................................................. 5• Changed Junction-to-case (top) thermal resistance from 73.7 °C/W to 105.0 °C/W ............................................................. 5• Changed Junction-to-board thermal resistance from 34.4 °C/W to 87.5 °C/W ...................................................................... 5• Changed Junction-to-top characterization parameter from 3.1 °C/W to 6.1 °C/W................................................................. 5• Changed Junction-to-board characterization parameter from 34.2 °C/W to 87.0 °C/W......................................................... 5• 「ドキュメントの更新通知を受け取る方法」セクションを追加........................................................................................................ 24

Revision E (April 2015) かからら Revision F にに変変更更 Page

• TI Designを追加 ...................................................................................................................................................................... 1• 「特長」にNISTの箇条書き項目を追加 ....................................................................................................................................... 1• 「概要」セクションに最後の段落を追加 ....................................................................................................................................... 1

Revision D (December 2014) かからら Revision E にに変変更更 Page

• Changed the MAX value for the Supply voltage from 3.6 to 4 in the Absolute Maximum Ratings table ............................... 4• Changed MIN, TYP, and MAX values for the Temperature Accuracy (temperature error) parameter .................................. 5• Changed the frequency from 2.85 to 3.4 MHz in the POWER SUPPLY section of the Electrical Characteristics table ....... 6• Changed the Temperature Error vs Temperature graph in the Typical Characteristics section ............................................ 7

http://www.tij.co.jp/product/jp/tmp102?qgpn=tmp102http://www.tij.co.jp

3

TMP102www.ti.com JAJS306H –AUGUST 2007–REVISED DECEMBER 2018


• Changed the Temperature Error at 25°C graph in the Typical Characteristics section ......................................................... 7

Revision C (October 2012) かからら Revision D にに変変更更 Page

• Added Handling Rating table, Feature Description section, Device Functional Modes, Application andImplementation section, Power Supply Recommendations section, Layout section, Device and DocumentationSupport section, and Mechanical, Packaging, and Orderable Information section ............................................................... 4

• Changed parameters in Timing Requirements ...................................................................................................................... 6

Revision B (October 2008) かからら Revision C にに変変更更 Page

• Changed values for Data Hold Time parameter in Timing Requirements .......................................................................... 12

http://www.ti.com/product/tmp102?qgpn=tmp102http://www.ti.com

1

2

3

6

5

4

SDA

V+

ADD0

SCL

GND

ALERT

CB

Z

4

TMP102JAJS306H –AUGUST 2007–REVISED DECEMBER 2018 www.ti.com


5 Pin Configuration and Functions

DRL Package6-Pin SOT563

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNO. NAME1 SCL I Serial clock. Open-drain output; requires a pullup resistor.2 GND — Ground3 ALERT O Overtemperature alert. Open-drain output; requires a pullup resistor.4 ADD0 I Address select. Connect to GND or V+5 V+ I Supply voltage, 1.4 V to 3.6 V6 SDA I/O Serial data. Open-drain output; requires a pullup resistor.

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.

(2) Input voltage rating applies to all TMP102 input voltages.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITSupply Voltage 4 VVoltage at SCL, SDA and ADD0 (2) –0.5 4 V

Voltage at ALERT ((V+) + 0.3)and ≤ 4 V

Operating temperature –55 150 °CJunction temperature 150 °CStorage temperature, Tstg –60 150 °C

(1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allowssafe manufacturing with a standard ESD control process.

(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

6.2 Handling RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000Machine model (MM) ±200


5



6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITV+ Supply voltage 1.4 3.3 3.6 VTA Operating free-air temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport (SPRA953).

6.4 Thermal Information

THERMAL METRIC (1)TMP102

UNITDRL (SOT563)6 PINS

RθJA Junction-to-ambient thermal resistance 210.3 °C/WRθJC(top) Junction-to-case (top) thermal resistance 105.0 °C/WRθJB Junction-to-board thermal resistance 87.5 °C/WψJT Junction-to-top characterization parameter 6.1 °C/WψJB Junction-to-board characterization parameter 87.0 °C/W

6.5 Electrical CharacteristicsAt TA = 25°C and VS = 1.4 to 3.6 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITTEMPERATURE INPUT

Range –40 125 °C

Accuracy (temperature error)–25°C to 85°C ±0.5 ±2

°C–40°C to 125°C ±1 ±3

vs supply 0.2 0.5 °C/VResolution 0.0625 °C

DIGITAL INPUT/OUTPUTInput capacitance 3 pF

VIH Input logic high 0.7 × (V+) 3.6 VVIL Input logic low –0.5 0.3 × (V+) VIIN Input current 0 < VIN < 3.6 V 1 μA

VOL Output logicSDA

V+ > 2 V, IOL = 3 mA 0 0.4

VV+ < 2 V, IOL = 3 mA 0 0.2 × (V+)

ALERTV+ > 2 V, IOL = 3 mA 0 0.4V+ < 2 V, IOL = 3 mA 0 0.2 × (V+)

Resolution 12 BitConversion time 26 35 ms

Conversion modes

CR1 = 0, CR0 = 0 0.25

Conv/sCR1 = 0, CR0 = 1 1CR1 = 1, CR0 = 0 (default) 4CR1 = 1, CR0 = 1 8

Timeout time 30 40 ms

http://www.ti.com/product/tmp102?qgpn=tmp102http://www.ti.comhttp://www.ti.com/lit/pdf/SPRA953

6



Electrical Characteristics (continued)At TA = 25°C and VS = 1.4 to 3.6 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITPOWER SUPPLY

Operating supply range +1.4 +3.6 V

IQ Average quiescent current

Serial bus inactive, CR1 = 1, CR0 =0 (default) 7 10

μASerial bus active, SCL frequency =400 kHz 15

Serial bus active, SCL frequency =3.4 MHz 85

ISD Shutdown current

Serial bus inactive 0.5 1

μASerial bus active, SCL frequency =400 kHz 10

Serial bus active, SCL frequency =3.4 MHz 80

TEMPERATURESpecified range –40 125 °COperating range –55 150 °C

6.6 Timing RequirementsSee the Timing Diagrams section for additional information.

FAST MODE HIGH-SPEED MODEUNIT

MIN TYP MAX MIN TYP MAXƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.85 MHz

t(BUF)Bus-free time between STOP andSTART condition

See Figure 7

600 160 ns

t(HDSTA)

Hold time after repeated STARTcondition.After this period, the first clock isgenerated.

600 160 ns

t(SUSTA) repeated start condition setup time 600 160 nst(SUSTO) STOP condition setup time 600 160 nst(HDDAT) Data hold time 100 900 25 105 nst(SUDAT) Data setup time 100 25 nst(LOW) SCL-clock low period V+ , see Figure 7 1300 210 nst(HIGH) SCL-clock high period See Figure 7 600 60 nstFD Data fall time See Figure 7 300 80 ns

tRD Data rise timeSee Figure 7 300 nsSCLK ≤ 100 kHz,see Figure 7 1000 ns

tFC Clock fall time See Figure 7 300 40 nstRC Clock rise time See Figure 7 300 40 ns


Temperature (qC)

Tem

pera

ture

Err

or (qC

)

-60 -40 -20 0 20 40 60 80 100 120 140-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

D002

MeanMean + 3 VMean � 3 V

Temperature Error (qC)

Pop

ulat

ion

-0.3

5

-0.3

-0.2

5

-0.2

-0.1

5

-0.1

-0.0

5 0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0

10

20

30

40

50

60

70

D001

40

38

36

34

32

30

28

26

24

22

20

Temperature (°C)

-60 -20 40 60 140 160

Convers

ion

Tim

e (

ms)

3.6 V Supply

1.4 V Supply

-40 200 80 100 120

100

90

80

70

60

50

40

30

20

10

0

Bus Frequency (Hz)

1k 10k 100k 1M 10M

I(

A)

Qμ

-55 °C+25 °C

+125 °C

10

9

8

7

6

5

4

3

2

1

0

Temperature (°C)

-60 -40 0 40 140 160

I(

A)

SD

μ

3.6 V Supply

1.4 V Supply

-20 20 60 80 100 120

20

18

16

14

12

10

8

6

4

2

0

Temperature (°C)

-60 -20 40 60 140 160

I(

A)

Qμ

3.6 V Supply

-40 0 20 80 100 120

1.4 V Supply

7



6.7 Typical CharacteristicsAt TA = 25°C and V+ = 3.3 V, unless otherwise noted.

Four conversions per second

Figure 1. Average Quiescent Current vs TemperatureFigure 2. Shutdown Current vs Temperature

Figure 3. Conversion Time vs Temperature Figure 4. Quiescent Current vs Bus Frequency(Temperature at 3.3-V Supply)

Figure 5. Temperature Error vs Temperature Figure 6. Temperature Error at 25°C


Diode

Temp.

Sensor

DS

A/D

Converter

OSC

Control

Logic

Serial

Interface

Config.

and Temp.

Register

Temperature

SCL1

3

6

4ALERT

SDA

GND2 5

V+

ADD0

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7 Detailed Description

7.1 OverviewThe TMP102 device is a digital temperature sensor that is optimal for thermal-management and thermal-protection applications. The TMP102 device is two-wire, SMBus and I2C interface-compatible. The device isspecified over an operating temperature range of –40°C to 125°C. See Functional Block Diagram for a blockdiagram of the TMP102 device.

The temperature sensor in the TMP102 device is the chip itself. Thermal paths run through the package leads aswell as the plastic package. The package leads provide the primary thermal path because of the lower thermalresistance of the metal.

An alternative version of the TMP102 device is available. The TMP112 device has highest accuracy, the samemicro-package, and is pin-to-pin compatible.

Table 1. Advantages of TMP112 versus TMP102

DEVICE COMPATIBLEINTERFACES PACKAGESUPPLY

CURRENT

SUPPLYVOLTAGE

(MIN)

SUPPLYVOLTAGE

(MAX)RESOLUTION LOCAL SENSOR ACCURACY(MAX)

SPECIFIEDCALIBRATIONDRIFT SLOPE

TMP112 I2C

SMBusSOT563

1.2 × 1.6 × 0.6 10 µA 1.4 V 3.6 V12 bit

0.0625°C0.5°C: (0°C to 65°C)

1°C: (-40°C to 125°C) Yes

TMP102 I2C

SMBusSOT563

1.2 × 1.6 × 0.6 10 µA 1.4 V 3.6 V12 bit

0.0625°C2°C: (25°C to 85°C)

3°C: (-40°C to 125°C) No

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Digital Temperature OutputThe digital output from each temperature measurement is stored in the read-only temperature register. Thetemperature register of the TMP102 device is configured as a 12-bit, read-only register (configuration register EMbit = 0, see the Extended Mode (EM) section), or as a 13-bit, read-only register (configuration register EM bit = 1)that stores the output of the most recent conversion. Two bytes must be read to obtain data and are listed inTable 8 and Table 9. Byte 1 is the most significant byte (MSB), followed by byte 2, the least significant byte(LSB). The first 12 bits (13 bits in extended mode) are used to indicate temperature. The least significant bytedoes not have to be read if that information is not needed. The data format for temperature is summarized inTable 2 and Table 3. One LSB equals 0.0625°C. Negative numbers are represented in binary twos-complementformat. Following power-up or reset, the temperature register reads 0°C until the first conversion is complete. BitD0 of byte 2 indicates normal mode (EM bit = 0) or extended mode (EM bit = 1) , and can be used to distinguishbetween the two temperature register data formats. The unused bits in the temperature register always read 0.


9



Feature Description (continued)

(1) The resolution for the Temp ADC in Internal Temperature mode is 0.0625°C/count.

Table 2. 12-Bit Temperature Data Format (1)

TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX128 0111 1111 1111 7FF

127.9375 0111 1111 1111 7FF100 0110 0100 0000 64080 0101 0000 0000 50075 0100 1011 0000 4B050 0011 0010 0000 32025 0001 1001 0000 190

0.25 0000 0000 0100 0040 0000 0000 0000 000

–0.25 1111 1111 1100 FFC–25 1110 0111 0000 E70–55 1100 1001 0000 C90

Table 2 does not list all temperatures. Use the following rules to obtain the digital data format for a giventemperature or the temperature for a given digital data format.

To convert positive temperatures to a digital data format:1. Divide the temperature by the resolution2. Convert the result to binary code with a 12-bit, left-justified format, and MSB = 0 to denote a positive sign.

Example: (50°C) / (0.0625°C / LSB) = 800 = 320h = 0011 0010 0000

To convert a positive digital data format to temperature:1. Convert the 12-bit, left-justified binary temperature result, with the MSB = 0 to denote a positive sign, to a

decimal number.2. Multiply the decimal number by the resolution to obtain the positive temperature.

Example: 0011 0010 0000 = 320h = 800 × (0.0625°C / LSB) = 50°C

To convert negative temperatures to a digital data format:1. Divide the absolute value of the temperature by the resolution, and convert the result to binary code with a

12-bit, left-justified format.2. Generate the twos complement of the result by complementing the binary number and adding one. Denote a

negative number with MSB = 1.

Example: (|–25°C|) / (0.0625°C / LSB) = 400 = 190h = 0001 1001 0000

Two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000

To convert a negative digital data format to temperature:1. Generate the twos compliment of the 12-bit, left-justified binary number of the temperature result (with MSB

= 1, denoting negative temperature result) by complementing the binary number and adding one. Thisrepresents the binary number of the absolute value of the temperature.

2. Convert to decimal number and multiply by the resolution to get the absolute temperature, then multiply by–1 for the negative sign.

Example: 1110 0111 0000 has twos compliment of 0001 1001 0000 = 0001 1000 1111 + 1

Convert to temperature: 0001 1001 0000 = 190h = 400; 400 × (0.0625°C / LSB) = 25°C = (|–25°C|);(|–25°C|) × (–1) = –25°C


10



Table 3. 13-Bit Temperature Data FormatTEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX

150 0 1001 0110 0000 0960128 0 1000 0000 0000 0800

127.9375 0 0111 1111 1111 07FF100 0 0110 0100 0000 064080 0 0101 0000 0000 050075 0 0100 1011 0000 04B050 0 0011 0010 0000 032025 0 0001 1001 0000 0190

0.25 0 0000 0000 0100 00040 0 0000 0000 0000 0000

–0.25 1 1111 1111 1100 1FFC–25 1 1110 0111 0000 1E70–55 1 1100 1001 0000 1C90

7.3.2 Serial InterfaceThe TMP102 device operates as a slave device only on the two-wire bus and SMBus. Connections to the busare made through the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spikesuppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP102device supports the transmission protocol for both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 2.85 MHz)modes. All data bytes are transmitted MSB first.

7.3.3 Bus OverviewThe device that initiates the transfer is called a master, and the devices controlled by the master are calledslaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the busaccess, and generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a highto low logic level when SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of theclock, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, theslave being addressed responds to the master by generating an acknowledge and by pulling SDA pin low.

A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the datatransfer the SDA pin must remain stable when SCL is high, because any change in SDA pin when SCL pin ishigh is interpreted as a START signal or STOP signal.

When all data have been transferred, the master generates a STOP condition indicated by pulling SDA pin fromlow to high, when the SCL pin is high.

7.3.4 Serial Bus AddressTo communicate with the TMP102, the master must first address slave devices via a slave address byte. Theslave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read orwrite operation.

The TMP102 features an address pin to allow up to four devices to be addressed on a single bus. Table 4describes the pin logic levels used to properly connect up to four devices.


11



Table 4. Address Pin and Slave AddressesDEVICE TWO-WIRE ADDRESS A0 PIN CONNECTION

1001000 Ground1001001 V+1001010 SDA1001011 SCL

7.3.5 Writing and Reading OperationAccessing a particular register on the TMP102 device is accomplished by writing the appropriate value to thepointer register. The value for the pointer register is the first byte transferred after the slave address byte with theR/W bit low. Every write operation to the TMP102 device requires a value for the pointer register (see Figure 8).

When reading from the TMP102 device, the last value stored in the pointer register by a write operationdetermines which register is read by a read operation. To change the register pointer for a read operation, a newvalue must be written to the pointer register. This action is accomplished by issuing a slave address byte with theR/W bit low, followed by the pointer register byte. No additional data are required. The master then generates aSTART condition and sends the slave address byte with the R/W bit high to initiate the read command. SeeFigure 7 for details of this sequence. If repeated reads from the same register are desired, continually sendingthe Pointer Register bytes is not necessary because the TMP102 remembers the Pointer Register value until it ischanged by the next write operation.

Register bytes are sent with the most significant byte first, followed by the least significant byte.

7.3.6 Slave Mode OperationsThe TMP102 can operate as a slave receiver or slave transmitter. As a slave device, the TMP102 never drivesthe SCL line.

7.3.6.1 Slave Receiver ModeThe first byte transmitted by the master is the slave address, with the R/W bit low. The TMP102 thenacknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. TheTMP102 then acknowledges reception of the pointer register byte. The next byte or bytes are written to theregister addressed by the pointer register. The TMP102 acknowledges reception of each data byte. The mastercan terminate data transfer by generating a START or STOP condition..

7.3.6.2 Slave Transmitter ModeThe first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledgesreception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte ofthe register indicated by the pointer register. The master acknowledges reception of the data byte. The next bytetransmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. Themaster terminates data transfer by generating a Not-Acknowledge on reception of any data byte, or generating aSTART or STOP condition.

7.3.7 SMBus Alert FunctionThe TMP102 device supports the SMBus alert function. When the TMP102 device operates in Interrupt Mode(TM = 1), the ALERT pin can be connected as an SMBus alert signal. When a master senses that an ALERTcondition is present on the ALERT line, the master sends an SMBus alert command (0001 1001) to the bus. Ifthe ALERT pin is active, the device acknowledges the SMBus alert command and responds by returning theslave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the ALERT conditionwas caused by the temperature exceeding THIGH or falling below TLOW. For POL = 0, the LSB is low if thetemperature is greater than or equal to THIGH; this bit is high if the temperature is less than TLOW. The polarity ofthis bit is inverted if POL = 1. See Figure 10 for details of this sequence.

If multiple devices on the bus respond to the SMBus alert command, arbitration during the slave address portionof the SMBus alert command determines which device clears the ALERT status. The device with the lowest two-wire address wins the arbitration. If the TMP102 device wins the arbitration, its ALERT pin inactivates at thecompletion of the SMBus alert command. If the TMP102 device loses the arbitration, its ALERT pin remainsactive.


SCL

SDA

t(LOW)

tRC

tFC t(HDSTA)

t(HDSTA)

t(HDDAT) t(SUDAT)

t(HIGH) t(SUSTA) t(SUSTO)

t(BUF)

S SP P

tRD tFD

12



7.3.8 General CallThe TMP102 device responds to a two-wire general call address (000 0000) if the eighth bit is 0. The deviceacknowledges the general call address and responds to commands in the second byte. If the second byte is0000 0110, the TMP102 device internal registers are reset to power-up values. The TMP102 device does notsupport the general address acquire command.

7.3.9 High-Speed (HS) ModeIn order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an HS-Mode master code (0000 1xxx) as the first byte after a START condition to switch the bus to high-speedoperation. The TMP102 device does not acknowledge this byte, but switches the input filters on SDA and SCLand the output filters on SDA to operate in HS-mode, allowing transfers of up to 2.85 MHz. After the HS-Modemaster code has been issued, the master transmits a two-wire slave address to initiate a data transfer operation.The bus continues to operate in HS-Mode until a STOP condition occurs on the bus. Upon receiving the STOPcondition, the TMP102 device switches the input and output filters back to fast-mode operation..

7.3.10 Timeout FunctionThe TMP102 device resets the serial interface if SCL is held low for 30 ms (typ) between a start and stopcondition. The TMP102 device releases the SDA line if the SCL pin is pulled low and waits for a start conditionfrom the host controller. To avoid activating the time-out function, maintaining a communication speed of at least1 kHz for SCL operating frequency is necessary..

7.3.11 Timing DiagramsThe TMP102 device is two-wire, SMBus, and I2C-interface compatible. Figure 7, Figure 8, Figure 9, andFigure 10 list the various operations on the TMP102 device. Parameters for Figure 7 are defined in the TimingRequirements table. The bus definitions are defined as follows:

Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device thatacknowledges must pull down the SDA line during the acknowledge clock pulse in such a way thatthe SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and holdtimes must be taken into account. On a master receive, the termination of the data transfer can besignaled by the master generating a not-acknowledge (1) on the last byte that has been transmittedby the slave.

Bus Idle Both SDA and SCL lines remain high.Data Transfer The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The TMP102 device can also be used for single byte updates.To update only the MS byte, terminate the communication by issuing a START or STOPcommunication on the bus.

Start Data Transfer A change in the state of the SDA line, from high to low, when the SCL line is high, defines aSTART condition. Each data transfer is initiated with a START condition.

Stop Data Transfer A change in the state of the SDA line from low to high when the SCL line is high defines aSTOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Figure 7. Two-Wire Timing Diagram


Frame 1 Two-Wire Slave Address Byte Frame 2 Pointer Register Byte

1

Start By

Master

ACK By

Device

ACK By

Device

Frame 3 Two-Wire Slave Address Byte Frame 4 Data Byte 1 Read Register

Start By

Master

ACK By

Device

ACK By

Master(2)

From

Device

1 9 1 9

1 9 1 9

SDA

SCL

0 0 1 R/W 0 0 0 0 0 0 P1 P0

¼

¼

¼

SDA

(Continued)

SCL

(Continued)

SDA

(Continued)

SCL

(Continued)

1 0 0 1

0 A1(1)

A0(1)

0 A1(1)

A0(1) R/W D7 D6 D5 D4 D3 D2 D1 D0

Frame 5 Data Byte 2 Read Register

Stop By

Master

ACK By

Master(3)

From

Device

1 9

D7 D6 D5 D4 D3 D2 D1 D0

Stop By

Master

NOTE: (1) The value of A0 and A1 are determined by the ADD0 pin.

(2) Master should leave SDA high to terminate a single-byte read operation.

(3) Master should leave SDA high to terminate a two-byte read operation.

Frame 1 Two-Wire Slave Address Byte Frame 2 Pointer Register Byte

Frame 4 Data Byte 2

1

Start By

Master

ACK By

Device

ACK By

Device

ACK By

Device

Stop By

Master

1 9 1

1

D7 D6 D5 D4 D3 D2 D1 D0

9

Frame 3 Data Byte 1

ACK By

Device

1

D7SDA

(Continued)

SCL

(Continued)

D6 D5 D4 D3 D2 D1 D0

9

9

SDA

SCL

0 0 1 0 A1(1) A0(1) R/W 0 0 0 0 0 0 P1 P0 ¼

¼


13



Figure 8. Two-Wire Timing Diagram for Write Word Format

Figure 9. Two-Wire Timing Diagram for Read Word Format


Startup Start of

Conversion

Delay(1)

26ms26ms


Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address From Device

Start By

Master

ACK By

Device

From

Device

NACK By

Master

Stop By

Master

1 9 1 9

SDA

SCL

ALERT

0 0 0 1 1 0 0 R/W 1 0 0 1 A1 A0 Status

14



Figure 10. Timing Diagram for SMBus Alert

7.4 Device Functional Modes

7.4.1 Continuos-Conversion ModeThe default mode of the TMP102 device is continuos conversion mode. During continuos-conversion mode, theADC performs continuos temperature conversions and stores each results to the temperature register,overwriting the result from the previous conversion. The conversion rate bits, CR1 and CR0, configure theTMP102 device for conversion rates of 0.25 Hz, 1 Hz, 4 Hz, or 8 Hz. The default rate is 4 Hz. The TMP102device has a typical conversion time of 26 ms. To achieve different conversion rates, the TMP102 device makesa conversion and then powers down to wait for the appropriate delay set by CR1 and CR0. Table 5 lists thesettings for CR1 and CR0.

Table 5. Conversion Rate SettingsCR1 CR0 CONVERSION RATE

0 0 0.25 Hz0 1 1 Hz1 0 4 Hz (default)1 1 8 Hz

After power-up or general-call reset, the TMP102 immediately starts a conversion, as shown in Figure 11. Thefirst result is available after 26 ms (typical). The active quiescent current during conversion is 40 μA (typical at+27°C). The quiescent current during delay is 2.2 μA (typical at +27°C).

(1) Delay is set by CR1 and CR0.

Figure 11. Conversion Start

7.4.2 Extended Mode (EM)The Extended-Mode bit configures the device for Normal mode operation (EM = 0) or Extended mode operation(EM = 1). In Normal mode, the Temperature Register and high- and low-limit registers use a 12-bit data format.Normal mode is used to make the TMP102 device compatible with the TMP75 device.

Extended mode (EM = 1) allows measurement of temperatures above 128°C by configuring the TemperatureRegister, and high- and low-limit registers for 13-bit data format.

http://www.ti.com/product/tmp102?qgpn=tmp102http://www.ti.comhttp://focus.ti.com/docs/prod/folders/print/tmp75.html

15



7.4.3 Shutdown Mode (SD)The Shutdown-mode bit saves maximum power by shutting down all device circuitry other than the serialinterface, reducing current consumption to typically less than 0.5 μA. Shutdown mode enables when the SD bit is1; the device shuts down when current conversion is completed. When SD is equal to 0, the device maintains acontinuous conversion state.

7.4.4 One-Shot/Conversion Ready (OS)The TMP102 device features a one-shot temperature measurement mode. When the device is in ShutdownMode, writing a 1 to the OS bit starts a single temperature conversion. During the conversion, the OS bit reads'0'. The device returns to the shutdown state at the completion of the single conversion. After the conversion, theOS bit reads 1. This feature reduces power consumption in the TMP102 device when continuous temperaturemonitoring is not required.

As a result of the short conversion time, the TMP102 device achieves a higher conversion rate. A singleconversion typically takes 26 ms and a read can take place in less than 20 μs. When using One-Shot Mode, 30or more conversions per second are possible.

7.4.5 Thermostat Mode (TM)The thermostat-mode bit indicates to the device whether to operate in comparator mode (TM = 0) or Interruptmode (TM = 1).

7.4.5.1 Comparator Mode (TM = 0)In Comparator mode (TM = 0), the Alert pin is activated when the temperature equals or exceeds the value in theT(HIGH) register and remains active until the temperature falls below the value in the T(LOW)register. For moreinformation on the comparator mode, see the High- and Low-Limit Registers section.

7.4.5.2 Interrupt Mode (TM = 1)In Interrupt mode (TM = 1), the Alert pin is activated when the temperature exceeds T(HIGH) or goes below T(LOW)registers. The Alert pin is cleared when the host controller reads the temperature register. For more informationon the interrupt mode, see the High- and Low-Limit Registers section.

7.5 Programming

7.5.1 Pointer RegisterFigure 12 illustrates the internal register structure of the TMP102 device. The 8-bit Pointer Register of the deviceis used to address a given data register. The Pointer Register uses the two least-significant bytes (LSBs) (seeTable 15 and Table 16) to identify which of the data registers must respond to a read or write command. Table 6identifies the bits of the Pointer Register byte. During a write command, P2 through P7 must always be '0'.Table 7 describes the pointer address of the registers available in the TMP102 device. The power-up reset valueof P1 and P0 is 00. By default, the TMP102 device reads the temperature on power up.


I/O

Control

Interface

SCL

SDA

Temperature

Register

Configuration

Register

TLOWRegister

THIGHRegister

Pointer

Register

16



Programming (continued)

Figure 12. Internal Register Structure

Table 6. Pointer Register ByteP7 P6 P5 P4 P3 P2 P1 P00 0 0 0 0 0 Register Bits

Table 7. Pointer AddressesP1 P0 REGISTER0 0 Temperature Register (Read Only)0 1 Configuration Register (Read/Write)1 0 TLOW Register (Read/Write)1 1 THIGH Register (Read/Write)

(1) Extended mode 13-bit configuration shown in parenthesis.

7.5.2 Temperature RegisterThe Temperature Register of the TMP102 is configured as a 12-bit, read-only register (Configuration RegisterEM bit = 0, see the Extended Mode section), or as a 13-bit, read-only register (Configuration Register EM bit = 1)that stores the output of the most recent conversion. Two bytes must be read to obtain data, and are describedin Table 8 and Table 9. Note that byte 1 is the most significant byte, followed by byte 2, the least significant byte.The first 12 bits (13 bits in Extended mode) are used to indicate temperature. The least significant byte does nothave to be read if that information is not needed.

Table 8. Byte 1 of Temperature Register (1)

D7 D6 D5 D4 D3 D2 D1 D0T11 T10 T9 T8 T7 T6 T5 T4

(T12) (T11) (T10) (T9) (T8) (T7) (T6) (T5)


17




Table 9. Byte 2 of Temperature Register (1)

D7 D6 D5 D4 D3 D2 D1 D0T3 T2 T1 T0 0 0 0 0

(T4) (T3) (T2) (T1) (T0) (0) (0) (1)

7.5.3 Configuration RegisterThe Configuration Register is a 16-bit read/write register used to store bits that control the operational modes ofthe temperature sensor. Read/write operations are performed MSB first. Table 10 and Table 11 list the formatand the power-up or reset value of the configuration register. For compatibility, Table 10 and Table 11correspond to the configuration register in the TMP75 device and TMP275 device (for more information see thedevice data sheets, SBOS288 and SBOS363, respectively). All registers are updated byte by byte.

Table 10. Byte 1 of Configuration and Power-Up or Reset FormatD7 D6 D5 D4 D3 D2 D1 D0OS R1 R0 F1 F0 POL TM SD0 1 1 0 0 0 0 0

Table 11. Byte 2 of Configuration and Power-Up or Reset FormatD7 D6 D5 D4 D3 D2 D1 D0

CR1 CR0 AL EM 0 0 0 01 0 1 0 0 0 0 0

7.5.3.1 Shutdown Mode (SD)The Shutdown-mode bit saves maximum power by shutting down all device circuitry other than the serialinterface, reducing current consumption to typically less than 0.5 μA. Shutdown mode enables when the SD bit is1; the device shuts down when current conversion is completed. When SD is equal to 0, the device maintains acontinuous conversion state

7.5.3.2 Thermostat Mode (TM)The Thermostat mode bit indicates to the device whether to operate in Comparator mode (TM = 0) or Interruptmode (TM = 1). For more information on comparator and interrupt modes, see the High- and Low-Limit Registerssection.

7.5.3.3 Polarity (POL)The polarity bit allows the user to adjust the polarity of the ALERT pin output. If the POL bit is set to 0 (default),the ALERT pin becomes active low. When the POL bit is set to 1, the ALERT pin becomes active high and thestate of the ALERT pin is inverted. The operation of the ALERT pin in various modes is illustrated in Figure 13.

http://www.ti.com/product/tmp102?qgpn=tmp102http://www.ti.comhttp://www.ti.com/lit/pdf/SBOS288http://www.ti.com/lit/pdf/SBOS363

Measured

Temperature

THIGH

TLOW

Device ALERT PIN

(Comparator Mode)

POL = 0

Device ALERT PIN

(Interrupt Mode)

POL = 0

Device ALERT PIN

(Comparator Mode)

POL = 1

Device ALERT PIN

(Interrupt Mode)

POL = 1

Read Read

Time

Read

18



Figure 13. Output Transfer Function Diagrams

7.5.3.4 Fault Queue (F1/F0)A fault condition exists when the measured temperature exceeds the user-defined limits set in the THIGH andTLOW registers. Additionally, the number of fault conditions required to generate an alert may be programmedusing the fault queue. The fault queue is provided to prevent a false alert as a result of environmental noise. Thefault queue requires consecutive fault measurements in order to trigger the alert function. Table 12 defines thenumber of measured faults that may be programmed to trigger an alert condition in the device. For THIGH andTLOW register format and byte order, see the High- and Low-Limit Registers section.

Table 12. TMP102 Fault SettingsF1 F0 CONSECUTIVE FAULTS0 0 10 1 21 0 41 1 6

7.5.3.5 Converter Resolution (R1/R0)The converter resolution bits, R1 and R0, are read-only bits. The TMP102 converter resolution is set at devicestart-up to 11 which sets the temperature register to a 12 bit-resolution.

7.5.3.6 One-Shot (OS)When the device is in Shutdown Mode, writing a 1 to the OS bit starts a single temperature conversion. Duringthe conversion, the OS bit reads '0'. The device returns to the shutdown state at the completion of the singleconversion. For more information on the one-shot conversion mode, see the One-Shot/Conversion Ready (OS)section.

7.5.3.7 EM BitThe Extended-Mode bit configures the device for Normal Mode operation (EM = 0) or Extended Mode operation(EM = 1). In normal mode, the temperature register, high-limit register, and low-limit register use a 12-bit dataformat. For more information on the extended mode, see the Extended Mode (EM) section.


19




7.5.3.8 Alert (AL Bit)The AL bit is a read-only function. Reading the AL bit provides information about the comparator mode status.The state of the POL bit inverts the polarity of data returned from the AL bit. When the POL bit equals 0, the ALbit reads as 1 until the temperature equals or exceeds T(HIGH) for the programmed number of consecutive faults,causing the AL bit to read as 0. The AL bit continues to read as 0 until the temperature falls below T(LOW) for theprogrammed number of consecutive faults, when it again reads as 1. The status of the TM bit does not affect thestatus of the AL bit..

7.5.3.9 Conversion Rate (CR)The conversion rate bits, CR1 and CR0, configure the TMP102 device for conversion rates of 0.25 Hz, 1 Hz, 4Hz, or 8 Hz. The default rate is 4 Hz. For more information on the conversion rate bits, see Table 5.

7.5.4 High- and Low-Limit RegistersThe temperature limits are stored in the T(LOW) and T(HIGH) registers in the same format as the temperature result,and their values are compared to the temperature result on every conversion. The outcome of the comparisondrives the behavior of the ALERT pin, which operates as a comparator output or an interrupt, and is set by theTM bit in the configuration register.

In Comparator mode (TM = 0), the ALERT pin becomes active when the temperature equals or exceeds thevalue in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pinremains active until the temperature falls below the indicated TLOW value for the same number of faults.

In Interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value inTHIGH for a consecutive number of fault conditions (as shown in Table 5). The ALERT pin remains active until aread operation of any register occurs, or the device successfully responds to the SMBus Alert Responseaddress. The ALERT pin will also be cleared if the device is placed in Shutdown mode. When the ALERT pin iscleared, it becomes active again only when temperature falls below TLOW, and remains active until cleared by aread operation of any register or a successful response to the SMBus Alert Response address. When the ALERTpin is cleared, the above cycle repeats, with the ALERT pin becoming active when the temperature equals orexceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General Call Resetcommand. This action also clears the state of the internal registers in the device, returning the device toComparator mode (TM = 0).

Both operational modes are represented in Figure 13. Table 13 through Table 16 describe the format for theTHIGH and TLOW registers. Note that the most significant byte is sent first, followed by the least significant byte.Power-up reset values for THIGH and TLOW are: THIGH = +80°C and TLOW = +75°C. The format of the data for THIGHand TLOW is the same as for the Temperature Register.

Table 13. Byte 1 Temperature Register HIGH(1)

D7 D6 D5 D4 D3 D2 D1 D0H11 H10 H9 H8 H7 H6 H5 H4

(H12) (H11) (H10) (H9) (H8) (H7) (H6) (H5)

Table 14. Byte 2 Temperature Register HIGHD7 D6 D5 D4 D3 D2 D1 D0H3 H2 H1 H0 0 0 0 0

(H4) (H3) (H2) (H1) (H0) (0) (0) (0)


Table 15. Byte 1 Temperature Register LOW(1)

D7 D6 D5 D4 D3 D2 D1 D0L11 L10 L9 L8 L7 L6 L5 L4

(L12) (L11) (L10) (L9) (L8) (L7) (L6) (L5)


20



Table 16. Byte 2 Temperature Register LOWD7 D6 D5 D4 D3 D2 D1 D0L3 L2 L1 L0 0 0 0 0

(L4) (L3) (L2) (L1) (L0) (0) (0) (0)


SCL

GND

ALERT

2

4

1

ADD0

V+

6

3

5

0.01 µF

Two-WireHost Controller

TMP102

1.4 V to 3.6 V

SDA

Pullup Resistors


Supply Voltage

5 k�

21



8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe TMP102 device is used to measure the PCB temperature of the board location where the device is mounted.The programmable address options allow up to four locations on the board to be monitored on a single serialbus.

8.2 Typical Application

Figure 14. Typical Connections

8.2.1 Design RequirementsThe TMP102 device requires pullup resistors on the SCL, SDA, and ALERT pins. The recommended value forthe pullup resistors is 5-kΩ. In some applications the pullup resistor can be lower or higher than 5 kΩ but mustnot exceed 3 mA of current on any of those pins. A 0.01-μF bypass capacitor on the supply is recommended asshown in Figure 14. The SCL and SDA lines can be pulled up to a supply that is equal to or higher than V+through the pullup resistors. To configure one of four different addresses on the bus, connect the ADD0 pin toeither the GND, V+, SDA, or SCL pin.

8.2.2 Detailed Design ProcedurePlace the TMP102 device in close proximity to the heat source that must be monitored, with a proper layout forgood thermal coupling. This placement ensures that temperature changes are captured within the shortestpossible time interval. To maintain accuracy in applications that require air or surface temperature measurement,care must be taken to isolate the package and leads from ambient air temperature. A thermally-conductiveadhesive is helpful in achieving accurate surface temperature measurement.


Time (s)

Tem

pera

ture

(qC

)

-1 1 3 5 7 9 11 13 15 17 19253035404550556065707580859095

100

Device

SCL SDA

GND V+

ALERT ADD0C(F) 10 nF≥

R(F) 5 k≤ Ω

Supply Voltage

22



Typical Application (continued)The TMP102 device is a very low-power device and generates very low noise on the supply bus. Applying an RCfilter to the V+ pin of the TMP102 device can further reduce any noise that the TMP102 device might propagateto other components. R(F) in Figure 15 must be less than 5 kΩ and C(F) must be greater than 10 nF.

Figure 15. Noise Reduction Techniques

8.2.3 Application CurveFigure 16 shows the step response of the TMP102 device to a submersion in an oil bath of 100ºC from roomtemperature (27ºC). The time-constant, or the time for the output to reach 63% of the input step, is 0.8 s. Thetime-constant result depends on the printed circuit board (PCB) that the TMP102 device is mounted. For this test,the TMP102 device was soldered to a two-layer PCB that measured 0.375 inch × 0.437 inch.

space

Figure 16. Temperature Step Response


Serial Bus Traces

Pullup Resistors


Via to Power or Ground Plane

Via to Internal Layer

Supply Voltage

SCL

GND

ALERT ADD0

V+

SDA

Ground Plane forThermal Coupling

to Heat Source

Heat Source

23

TMP102www.tij.co.jp JAJS306H –AUGUST 2007–REVISED DECEMBER 2018


9 Power Supply RecommendationsThe TMP102 device operates with power supply in the range of 1.4 to 3.6 V. The device is optimized foroperation at 3.3-V supply but can measure temperature accurately in the full supply range.

A power-supply bypass capacitor is required for proper operation. Place this capacitor as close as possible to thesupply and ground pins of the device. A typical value for this supply bypass capacitor is 0.01 μF. Applicationswith noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supplynoise.

10 Layout

10.1 Layout GuidelinesPlace the power-supply bypass capacitor as close as possible to the supply and ground pins. The recommendedvalue of this bypass capacitor is 0.01 μF. Additional decoupling capacitance can be added to compensate fornoisy or high-impedance power supplies. Pull up the open-drain output pins (SDA , SCL and ALERT) through 5-kΩ pullup resistors.

10.2 Layout Example

Figure 17. TMP102 Layout Example

http://www.tij.co.jp/product/jp/tmp102?qgpn=tmp102http://www.tij.co.jp

24

TMP102JAJS306H –AUGUST 2007–REVISED DECEMBER 2018 www.tij.co.jp


11 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト

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11.1.1 関関連連資資料料関連資料については、以下を参照してください。

• TMP175、TMP75データシート、SBOS288• TMP275データシート、SBOS363• 「静電容量タッチ操作車載用LEDドーム・ライト、ハプティクス・フィードバック付き」デザイン・ガイド

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11.3 ココミミュュニニテティィ・・リリソソーーススThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™オオンンラライインン・・ココミミュュニニテティィ TIののE2E（（Engineer-to-Engineer））ココミミュュニニテティィ。。エンジニア間の共同作業を促進するために開設されたものです。e2e.ti.comでは、他のエンジニアに質問し、知識を共有し、アイディアを検討して、問題解決に役立てることができます。

設設計計ササポポーートト TIのの設設計計ササポポーートト役に立つE2Eフォーラムや、設計サポート・ツールをすばやく見つけることができます。技術サポート用の連絡先情報も参照できます。

11.4 商商標標E2E is a trademark of Texas Instruments.SMBus is a trademark of Intel, Inc.All other trademarks are the property of their respective owners.

11.5 静静電電気気放放電電にに関関すするる注注意意事事項項これらのデバイスは、限定的なESD（静電破壊）保護機能を内蔵しています。保存時または取り扱い時は、MOSゲートに対する静電破壊を防止するために、リード線同士をショートさせておくか、デバイスを導電フォームに入れる必要があります。

11.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。この情報は、そのデバイスについて利用可能な最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もあります。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。

http://www.tij.co.jp/product/jp/tmp102?qgpn=tmp102http://www.tij.co.jphttp://www.ti.com/lit/pdf/SBOS288http://www.ti.com/lit/pdf/SBOS363http://www.tij.co.jp/tool/jp/TIDA-00156http://www.ti.com/corp/docs/legal/termsofuse.shtmlhttp://www.ti.com/corp/docs/legal/termsofuse.shtmlhttp://e2e.ti.comhttp://support.ti.com/http://www.ti.com/lit/pdf/SLYZ022

重重要要ななおお知知ららせせとと免免責責事事項項

TI は、技術データと信頼性データ（データシートを含みます）、設計リソース（リファレンス・デザインを含みます）、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。

これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。TI の製品は、TI の販売条件（www.tij.co.jp/ja-jp/legal/termsofsale.html）、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用されるTI の保証または他の保証の放棄の拡大や変更を意味するものではありません。IMPORTANT NOTICE

Copyright © 2019, Texas Instruments Incorporated日本語版日本テキサス・インスツルメンツ株式会社

http://www.tij.co.jp/ja-jp/legal/termsofsale.htmlhttp://www.tij.co.jp/

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TMP102AIDRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CBZ

TMP102AIDRLRG4 ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 CBZ

TMP102AIDRLT ACTIVE SOT-5X3 DRL 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CBZ

TMP102AIDRLTG4 ACTIVE SOT-5X3 DRL 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 CBZ

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TMP102AIDRLR SOT-5X3 DRL 6 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3

TMP102AIDRLR SOT-5X3 DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

TMP102AIDRLT SOT-5X3 DRL 6 250 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

TMP102AIDRLT SOT-5X3 DRL 6 250 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TMP102AIDRLR SOT-5X3 DRL 6 4000 184.0 184.0 19.0

TMP102AIDRLR SOT-5X3 DRL 6 4000 202.0 201.0 28.0

TMP102AIDRLT SOT-5X3 DRL 6 250 202.0 201.0 28.0

TMP102AIDRLT SOT-5X3 DRL 6 250 184.0 184.0 19.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

1.71.5

4X 0.5

2X 1

6X 0.30.1

0.6 MAX

6X 0.180.08

6X 0.40.2

0.050.00 TYP

6X 0.270.15

B 1.31.1

A

1.71.5

NOTE 3

SOT - 0.6 mm max heightDRL0006APLASTIC SMALL OUTLINE

4223266/B 12/2020

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.4. Reference JEDEC registration MO-293 Variation UAAD

16

PIN 1ID AREA

34

SEATING PLANE

0.05 C

SCALE 8.000

0.1 C A B0.05

SYMM

SYMM

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAXAROUND

0.05 MINAROUND

6X (0.67)

6X (0.3)

(1.48)

4X (0.5)

(R0.05) TYP

4223266/B 12/2020


NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLESCALE:30X

SYMM1

3 4

6

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKDEFINED

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

(PREFERRED)

SOLDERMASK DETAILS

www.ti.com

EXAMPLE STENCIL DESIGN

(1.48)

4X (0.5)

6X (0.67)

6X (0.3)

(R0.05) TYP


4223266/B 12/2020

NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCIL

SCALE:30X

SYMM

SYMM1

34

6

重要なお知らせと免責事項TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適したTI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。TI の製品は、TI の販売約款 (https://www.tij.co.jp/ja-jp/legal/terms-of-sale.html)、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。IMPORTANT NOTICE

日本語版日本テキサス・インスツルメンツ合同会社Copyright © 2021, Texas Instruments Incorporated

https://www.tij.co.jp/ja-jp/legal/terms-of-sale.htmlhttps://www.tij.co.jp/

1 特長2 アプリケーション3 概要目次4 改訂履歴5 Pin Configuration and Functions6 Specifications6.1 Absolute Maximum Ratings6.2 Handling Ratings6.3 Recommended Operating Conditions6.4 Thermal Information6.5 Electrical Characteristics6.6 Timing Requirements6.7 Typical Characteristics

7 Detailed Description7.1 Overview7.2 Functional Block Diagram7.3 Feature Description7.3.1 Digital Temperature Output7.3.2 Serial Interface7.3.3 Bus Overview7.3.4 Serial Bus Address7.3.5 Writing and Reading Operation7.3.6 Slave Mode Operations7.3.6.1 Slave Receiver Mode7.3.6.2 Slave Transmitter Mode

7.3.7 SMBus Alert Function7.3.8 General Call7.3.9 High-Speed (HS) Mode7.3.10 Timeout Function7.3.11 Timing Diagrams

7.4 Device Functional Modes7.4.1 Continuos-Conversion Mode7.4.2 Extended Mode (EM)7.4.3 Shutdown Mode (SD)7.4.4 One-Shot/Conversion Ready (OS)7.4.5 Thermostat Mode (TM)7.4.5.1 Comparator Mode (TM = 0)7.4.5.2 Interrupt Mode (TM = 1)

7.5 Programming7.5.1 Pointer Register7.5.2 Temperature Register7.5.3 Configuration Register7.5.3.1 Shutdown Mode (SD)7.5.3.2 Thermostat Mode (TM)7.5.3.3 Polarity (POL)7.5.3.4 Fault Queue (F1/F0)7.5.3.5 Converter Resolution (R1/R0)7.5.3.6 One-Shot (OS)7.5.3.7 EM Bit7.5.3.8 Alert (AL Bit)7.5.3.9 Conversion Rate (CR)

7.5.4 High- and Low-Limit Registers

8 Application and Implementation8.1 Application Information8.2 Typical Application8.2.1 Design Requirements8.2.2 Detailed Design Procedure8.2.3 Application Curve

9 Power Supply Recommendations10 Layout10.1 Layout Guidelines10.2 Layout Example

11 デバイスおよびドキュメントのサポート11.1 ドキュメントのサポート11.1.1 関連資料

11.2 ドキュメントの更新通知を受け取る方法11.3 コミュニティ・リソース11.4 商標11.5 静電気放電に関する注意事項11.6 Glossary

12 メカニカル、パッケージ、および注文情報