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TL850 Rev C Preliminary Specification Version 3.0
July 2000
TERALOGIC CONFIDENTIAL - DO NOT COPY
This material is confidential and is provided under an existing NDA
© 2000, 1999, 1998, 1997 TeraLogic, Inc.
All rights reserved worldwide.
This specification contains information that is confidential to TeraLogic, Inc. and is subject to the terms and conditions, including confidentiality obligations, set forth in the applicable Nondisclosure Agreement and/or License Agreement between Teralogic, Inc. and User.
Information herein is subject to change without notice. TeraLogic, Inc. assumes no responsibility for any use of, or reliance on, the information contained herein.
THIS SPECIFICATION AND ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE. TERALOGIC, INC. AND ITS SUPPLIERS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE.
TeraLogic® is a registered trademark of TeraLogic, Inc. The TeraLogic logo is a trademark of TeraLogic, Inc.
All other trademarks are the properties of their respective owners.
TeraLogic, Inc.
1240 Villa Street
Mountain View, CA 94041-1124
Tel: (650) 526-2000
Fax: (650) 526-2006
http://www.teralogic-inc.com
Doc # PD-850-DS-101-03
ii TERALOGIC CONFIDENTIAL - DO NOT COPY July 2000 Rev. 3.0
TL850CAdvanced Digital TV Decoder
Preliminary Specification
This material is confidential and is provided under an existing Non Disclosure Agreement
1. FEATURES & BENEFITSHigh-Performance Digital Video Decoder
• MP@HL MPEG2 decoder• All ATSC-compliant decode formats• Decodes 1 HD (MP@HL) or 4 SD (MP@ML) streams
simultaneously• Multiple decode contexts; decode and display multiple
programs simultaneously
Flexible Format Converter
• High-quality scan conversions from ATSC, NTSC source formats to many output display formats
• High-quality up-conversion and down-conversion of source video to selected display format
• Integrated high-quality line doubler
Memory Controller
• 32-bit/64-bit wide SDRAM interface up to 125 MHz• Programmable clock generator• Up to 64 Mbytes addressing range• Advanced Memory Reduction (AMR) mode supports HD
decode in 8 Mbytes of commodity SDRAM• AMR mode supports HD decode and down-conversion to
standard definition display format (480I and 480P) using 4 Mbytes of commodity SDRAM
NTSC Video Integration
• Video capture port for NTSC/PAL digital video, ITU-R 656 compatible
• Simultaneous output in HD and 704x480I; supports analog VCR recording of off-air programming (Option for no OSD)
Audio Integration & Processing
• Supports integration of an external Dolby Digital (AC3) or MPEG audio decoder
• Supports software audio decode• Provides audio rate buffer• Supports audio and video PTS synchronization• Audio capture to memory or bypass to output• Audio stream play from memory• Audio mix, cross-fade, and attenuate between sources• Six-channel audio input and output• IEC-958 formatted output supported
High-Performance Display Processor
• Multiple output display formats supported, including 1920x1080I, 1280x720P, 704x480P, and 704x480I
• Many nonstandard input and output formats supported• Letterbox and pan-and-scan options for displaying 16:9 video
on 4:3 displays• Multiple video services displayed on the same screen; supports
viewing of multiplex services, Picture-in-Picture, and Picture out of Picture applications
• Graphics overlay plane with up to 24 bits per pixel and 8-bit alpha channel
• Cursor plane with 32x32 pixel cursor with 4-bit index (16 colors with 8-bit alpha blending)
• Analog RGB or YCC output for HDTV display or SD display in down-conversion mode
• EIA 770, SMPTE 274M, SMPTE 296M, and SMPTE 293M compatible tri-level sync on analog output supported
• EIA770.3 output through primary output port is EIA805 compatible, supporting CGMS and data output during blanking.
• 16- or 24-bit digital video output in YCrCb or RGB mode• Video output signals are copy-protected using CGMS Layer 1/2
and DirecTV CGMS.
Programmable Transport Demultiplexer
• ATSC/ARIB/DVB/DSS compliant transport demultiplexing
Accelerated 2-D Graphics
• 256 ROP hardware BLT engine• 1-, 4-, 8-, 15-, 16-, and 24-bit per pixel RGB graphics support• 1-, 4- or 8-bit per-pixel, and global alpha channel• Alpha channel arithmetic engine• Hardware color expansion and reduction• Hardware flicker reduction for interlaced display
PCI Bus Interface
• 32-bit interface with 54 MHz bus clock• PCI Master/Slave capability supported• DMA master capability over PCI bus supported
Technology
• 2.5-V core, 3.3-V I/O, 0.25-µ CMOS• 348-pin Ball Grid Array package
Figure 1 TL850C System Block Diagram
QPSK, QAM,VSB
Receiver
VideoDecoderTuner
AudioA/D
SDRAM16 MB – 64 MB
PCI Bus
HDTV
AudioDACs
32
Digital RF
Analog RF
Transport
ITU-R 656
I2S
RGB or YPbPr
I2S ... 5.1 Channels
32/64and Sync
TL850C
TERALOGIC CONFIDENTIAL - DO NOT COPY Doc # PD-850-DS-101-03July 2000 Rev. 3.0
This material is confidential and is provided under an existing NDA
2. APPLICATIONS • ATSC/ARIB/DVB/DSS compliant SD/HD TV• HD to SD Down-Conversion Set-Top Boxes (STB)
• DBS/Cable/Terrestrial STB
3. GENERAL DESCRIPTION
The TL850C is an integrated MPEG-2 MP@HL video decoder,display processor with scan rate converter, and graphics acceleratorfor Advanced Digital Television. It complies with all ATSC-recommended performance metrics and supports direct video outputto a variety of display types, using an on-chip, very high-quality scanconverter to convert between formats. The coded data input providesthe MPEG/ATSC streams for the TL850C to decode. The TL850C canhandle either transport or PES formats. It supports decoding a singleHD program (MP@HL) or up to four SD programs (MP@ML). Anintegrated graphics accelerator renders text and graphics to anindependent on-screen display (OSD) bitmap. The TL850C cancapture digital video from a decoded NTSC source and up-convert itfor display on HDTV monitors. This eliminates the need for a separateline doubler when building a hybrid analog/digital TV. It supports ratebuffering of audio data, allowing the use of a standard AC3 decoderchip or AC3 software on a host CPU for audio decoding. Theintegrated high-performance memory controller uses SynchronousDRAM for frame store, rate buffer, and graphics bitmap storage. Thedevice has a PCI interface.
3.1 MPEG2 MP@HL Video Decoder
The video decoder complies with ISO/IEC 13818-2 MP@HL andISO/IEC 11172-2. It also complies with the recommendations of theAdvanced Television Systems Committee (the ATSC DigitalTelevision Standard), including the recommended compression formatconstraints. Because digital terrestrial broadcast is in the evolutionarystate, the decoder can decode other formats, provided the combinedthroughput does not exceed 250,000 macroblocks/sec. The TL850Ccan decode multiple stream contexts simultaneously. It cansimultaneously decode up to four MP@ML video pictures.
Thus it can decode and display multiple program channels on thescreen at the same time, allowing the reception of simulcast programmultiplexes, provided the content does not exceed the throughputlimit. For example, four standard definition programs meet thiscriteria. Figure 2 shows typical SD PIP displays. The decoded videocan be displayed either on an HDTV monitor, SDTV monitor, or in awindow on a PC monitor through the graphics chip in a PC.
Figure 2 Multiple SD PIP Typical Display
The TL850C supports a video capture port that is ITU-R 656compatible and enables a typical PIP display as shown in Figure 3.
Figure 3 HD PIP Typical Display
The AMR technology allows a high-definition ATSC stream to bedecoded and displayed using less than 8 Mbytes memory. Less than4 Mbytes are used when performing down-conversion to standarddefinition. Figure 4 illustrates the path taken by the MPEG datathrough the TL850C.
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Figure 4 MPEG Data Flow
The video decoder is controlled by an on-chip microprocessor.Depending on the product variant, it executes its program from an on-chip ROM or RAM. The RAM, if present, is loaded from an externalhost CPU at boot time. The processor is not user-programmable.Firmware is provided by TeraLogic. The on-chip controller performsall real-time processing to reconstruct the video stream. External CPUintervention is required only to service interrupts, which generallyoccur once each field time. Additional CPU intervention might berequired when decoding a program multiplex (multi-program decode).
Motion-compensated block replacement provides error concealment.Field repeat is also available in I or P pictures.
3.2 Transport Demultiplexer
The TL850C includes a transport demultiplexing function that iseffected in an embedded, programmable microcode unit (MCU), asshown in Figure 5. The MCU performs all real-time transport streamprocessing and separates less time-critical stream data into a set ofsystem buffers for processing by the CPU. TeraLogic providesfirmware for this function.
Figure 5 Transport Processor Unit
3.3 Display Processor
The display processor provides scan conversion for compositing oneor more video sequences, the graphics plane, and cursor plane, as wellas displaying the resulting image on a CRT. The TL850C can supportmultiple base resolutions, including those typically found in PC
monitors as well as standard and high-definition television. A systemimplementation can use any one of these formats, selected at time ofmanufacture, or selected dynamically.
In general, video sequences are decoded at their full resolution andthen scan converted to the target display resolution. The scanconversion can be an up-conversion or a down-conversion. Scanconversions are done with very high-quality filters that can removevirtually all aliasing from the image.
3.3.1 Horizontal Sample Rate conversion
The TL850C can adjust the horizontal size of the source imagesequence to that required in the output image. The sample rateconverter uses a low-pass anti-aliasing filter with 17 taps, followed bya polyphase filter with four taps and 16 phases. The low-pass filter canbe programmed to select the appropriate trade-off between sharpnessand aliasing for the selected conversion. The polyphase filter canarbitrarily scale the image up or down.
3.3.2 Vertical Sample Rate conversion
The TL850C can adjust the vertical size of the source image to thatrequired in the output image. The sample rate converter uses a lowpass anti-aliasing filter with 17 taps, followed by a polyphase filterwith four taps and 16 phases. This filter is capable of removingvirtually all aliasing artifacts when down-converting.
The TL850C also comprises an integrated line doubler (see Section5.3.3.2), which is used to up-convert standard definition video (eitherMPEG video, or captured legacy video) for viewing on a high-definition display. This line doubler uses a two-field motion-adaptiveedge-line interpolator.
3.3.3 Frame Rate Conversion
Conversions from 24 to 30 fps are done using pull-downs. Pull-downcan occur in any frame. Conversions from 59.94 to 60 fps are doneusing field-repeat every 1000 fields. Conversions from 60 to 59.94 fpsare done using field- or frame-skips approximately every 1000pictures (or 2000, for frames); frame-skips are used in frame modesequences, field-skips are used in field mode sequences. If B-picturesare present in the stream, firmware selects them; otherwise, the last P-picture in a group of pictures is skipped.
The TL850C performs the necessary rate conversions required totrack the PTS in a similar manner.
3.3.4 Video Tiles: Picture-in-Picture (PIP) and Picture-Outside-of-Picture (POP)
The display processor supports the composition of multiple videotiles. These can contain separate video sequences reconstructed by thedecoder. They can be different sizes and overlap. This feature allowsthe display of multiple program streams from the same programsource (e.g. multiple camera views of the same sporting event). Thenumber of macroblocks to be decoded in the sequence set cannotexceed 250,000 macroblocks/sec. The video tiles are constructed onthe fly, using picture data stored in memory. Video tiles can be resizedarbitrarily before compositing.
M P E G
Transport
B uffers
Video
D eco der
M P @ H L
M em ory
E lem entary
S tream
E lem entary
S tream
D isp lay
Processor
VideoTransportP rocessor
MPEGTransport
ClockRecovery
TransportBuffer
27 MHz
PWM
(Pulse Width Modulated)
Microcode
Transport /PES Streams
Unit
Firmware
VideoES (1-4)
HostCPU
SystemBuffers
AudioES
SDRAM
Transport /
ES
Source Info
ES
PES
Audio
A/V Time StampsClock Ref Time Stamps
Data
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Video tiling is considered a “trick mode.” Some extremecombinations of source and display resolutions might produceunsatisfactory results, usually due to the available memory band-width being insufficient for the required processing. The TL850C alsosupports PIP displays, as shown in Figure 2 and Figure 3.
3.3.5 Graphics Overlay
The TL850C supports a graphic overlay plane that can be used forcaptioning, program guides, or other data services. The plane cansupport 4, 8, 16 and 32 bits per pixel (bpp) simultaneously in differentregions of the display, using a linked-list technique. The four- andeight-bit modes use a color palette to expand to 8, 16, or 32 bpp. Theeight-bit mode uses a palette map to the displayed colors.
The four- and eight-bit modes can be used at any time, including in allvideo source and display modes. The 16- and 24-bit modes can beused when a) there is no video, b) the decoder is operating with alower resolution display, or c) when using fast SDRAM.
The graphics plane is composited with the video sequence in real-time. The per-pixel alpha channel is used to determine the opacity ofthe graphics overlay at every sample point. A global alpha is used forcompositing the planes.
The graphics plane can be resized by an integer scale factor prior tocompositing. This can be used for a high-resolution bitmap whenthere is insufficient memory. Scaling of the graphics plane is by pixelreplication.
There is a hardware anti-flicker filter that can be used in 4i- and 8i-pixel modes, which reduces graphics flicker on interlaced displays.
The HD digital output on the TL850C chip is compliant with theVIP1.x and VIP2.0 standards. Hence, in most add-in cards the designmight bypass the graphics engine within the TL850C chip. The digitaloutput of the chip may be connected to a pre-existing graphics cardwithin the PC wherein the graphics features of the graphics chip areused with video from the TL850C chip.
3.3.6 Cursor Overlay
There is a separate 32 x 32 cursor plane independent of the graphicsand video planes. It has four bpp. Two of the bits define the cursoropacity, two define the cursor color.
3.3.7 Video Output
The video is output as analog RGB or YPbPr. The TL850C requiresthat the video sample rate clock be supplied. Video timing isprogrammable: it can match the ATSC standard or be relaxed tosimplify the interface to the display electronics. This follows SMPTEstandards 274M and 296M, as well as EIA 770. The TL850C slavesthe video output off the supplied clock.
The TL850C’s programmable color space converter can color correctthe source-video chromaticity.
The TL850C also has a 16-bit or 24-bit digital video output. This cansupport connection to fully digital display devices, such as plasmapanels. Sin X/X DAC distortion correction is supported.
3.4 NTSC Video Integration
The TL850C supports integration of legacy analog NTSC for aseamless integration of digital and analog TV programming.
3.4.1 Video Capture
The TL850C has an eight-bit capture port for digitized YCbCr datacompatible with ITU-R 656. The capture port can interface to a digitalcomposite video decoder. Data from the video port is captured tomemory as two separate fields. Once in memory, it is processed by thedisplay processor or graphics accelerator. In a typical application, thedisplay processor performs an up-conversion on the captured picturedata and displays it.
3.4.2 Simultaneous NTSC Output
The TL850C can simultaneously output SD video in ITU-R 656 (orITU-R 601) format. The video on the SD output is downconvertedversion of the video that is output on the HD port. The field rates ofthe two outputs must be the same. Note that this is not possible withSMPTE 274M and SMPTE 296M unless the video sample clock isreduced to 74.25/1.001 MHz. The simultaneous NTSC output isintended for home video recording on an analog VCR. The TL850Cresamples the HD display channel to derive this data. The output isalways pan & scan if the main display is 16:9. It is not possible tooutput letterbox unless the main display is also letterbox (e.g., is in704 x 576P mode with letterbox enabled). The graphics overlay OSDcan be disabled in the simultaneous NTSC output. This output may beused to record a particular video channel to a VCR.
3.5 Graphics Accelerator
The TL850C can support display bitmaps at 4, 8, 16, and 32 bpp. Off-screen bitmaps can be 1, 4, 8, 16, or 32 bpp. Bitmap draws, fills, andmoves are accelerated using a 32-bit Bit Block Transfer (BITBLT)accelerator that can perform 256 raster operations on source, pattern,and destination bitmaps. Operations between bitmaps of differentsizes can be done using hardware color expansion or color reduction.For example, character fonts stored in off-screen memory as 1 bpp canbe copied to an on-screen bitmap of eight bpp without the CPU havingto perform either the color expansion or the block copy. There is a256-entry color palette used by the eight bpp mode. The palettecontains a 24-bit color entry and an 8-bit alpha entry for each colorindex. The 16-bit and 32-bit color modes bypass the color palette.
There is also a complimentary set of bitmap formats capable ofsupporting alpha-per-pixel operations. These are 8i8a, 8c8a, 12c4aand 24c8a (i-indexed, c-rgb color, a-alpha). The Block Transfer (BLT)engine can do complete source/destination compositing using the per-pixel alpha channel. The operation on each color component is: Cd =
Cs + (1-As)*Cd. The alpha value written to the destination is of the
form Ad = As + Ad - (As * Ad). A per-BLT alpha is available for
bitmaps without a per-pixel alpha channel.
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The graphics accelerator supports paced BLTs. Here, the BLT enginefollows a script of operations stored in memory. Each operation can bemade dependent on the display state (e.g., a certain line has beendisplayed). You can build a linked list of BLT commands to generateanimation sequences that render and repeat themselves without CPUintervention. This allows dynamic user interfaces to be designedwithout overloading the CPU.
3.6 Audio Integration
The TL850C provides support for an external audio AC3/MPEGdecoder that can be implemented in hardware or software. It integratesthe rate buffer needed for audio/video synchronization, and it providesan audio capture input that permits integrating analog TV audio(NTSC audio) and digital audio. TeraLogic has developed thesoftware required for the AC-3 audio decode function.
3.6.1 Audio Rate Buffer Control
A transport stream containing audio PES data can enter the TL850Cover the coded data port. The TL850C can store the PES data directlyto the audio rate buffer, or (optionally) it can parse the time stampinformation from it. The audio PES stream is subsequently read frommemory and presented to the audio decoder. The amount of time theaudio data stays in the buffer is a function of the presentation timestamp of the audio payload. Integration of the audio rate buffer in theTL850C eliminates the need for an external rate buffer when usinglow-cost AC3 decoders designed for DVD applications. The TL850C
can extract more than one audio stream from a transport multiplex,thus supporting the ATSC dual stream requirement.
3.6.2 Audio Processor
The TL850C provides three serial audio inputs, supporting up to sixchannels. These inputs operate in three-wire serial mode. The audiostreams can be stored in memory, or passed directly to the output.
Up to six channels of audio can be played from the attached DRAM.These PCM-coded streams are either written by the external CPU, orthey come from audio capture. Audio streams from different sourcescan be mixed in the TL850C before they are output. Mixing, crossfading, and attenuating is done in 0.5dB increments.
3.7 Memory Controller
The TL850C memory controller is a highly optimized x32/x64SDRAM controller running between 81 MHz and 125 MHz. Theinterface can have either two, four, or eight x 16 SDRAMs. The two-device option is only supported for down-conversions in reducedmemory mode.
Device performance is a function of memory speed. Operation at 1920x 1080I is only guaranteed with 100-MHz SDRAM or faster.
3.8 PCI Interface
The TL850C PCI Interface supports versions 2.1 and 2.2 of the PCIbus specification at up to 54 MHz. It can be a master/slave device.
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4. PIN LIST
Figure 6 TL850C Signal Summary
SADR[13:0]SDATA[63:0]
SCASSCLKI
SCLKO[2:0]SCS[1:0]
SDQM[7:0]SRASSWE
BLUE/PB*GREEN/Y*
RED/PR*
DDC0 (GPIO)
DDC1 (GPIO)
HSYNC (CSYNC) (GPIO)
PCLKVSYNC (GPIO)
PIXIN[7:0]VCLKI
ADATAI[2:0]ADATAO[2:0]
BCLKLRCLK
CCLKCDATA[7:0]CFRAME
TCLK/EE_SKTDI/EE_DITDO/EE_DOTMSTRST
AD[31:0]
PERR
C/BE[3:0]HCLKDEVSELFRAMEGNTIDSELINTA
IRDYPAR
RSTSERRSTOPTRDY
AGND, VGND
AVDD, VVDD
SGND, PGND
SVDD, PVDD
CLKIN
REQ
MemoryInterface
PrimaryVideoOutput
VideoInputs
AudioInput/Output
CodedDataInput
Boundary Scan/
PCI Bus
Analog Power
Miscellaneous
Interface
ACLK
VVLD
IECOUT
CDVALID
EE_CS/INTB
AUXO[7:0]
VCLKO
AuxiliaryVideoOutput
PCI Configuration
VREFIN*VREFOUT*
COMP* CPWM
* indicates analog signal
TL850C
OSDP
BUSCLK
PLL_BP
PIXOUT[23:0]
RSET*
Display
CGND
CVDD
IGND
IVDD
Digital Power
DAC
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SYMBOL I/O DESCRIPTION
Memory Interface
SADR[13:0] O Memory Address Bus. Multiplexed row/column address to attached memory. The bus can support 4 M x 16 SDRAMs, 1 M x 16 SDRAMs, 1M x 32 SDRAMs, 2M x 32 SDRAMs, 512 K x 32 SGRAMs or 2 M x 32 SGRAMs. The maximum fanout is eight SDRAM address loads per pin (e.g., two banks of 4 x 1 M x 16).
SDATA[63:0] I/O Memory Data Bus. 64-bit bidirectional bus to attached memory. Maximum fanout is two SDRAM data bus loads per pin.
SCAS O SDRAM column address strobe. When sampled at the rising edge of SCLK, this signal defines the oper-ation of the SDRAM. The maximum fanout is eight SDRAM loads.
SCLKI I Memory Clock Feedback Input. Required for correct timing of the SDRAM. Connect to SCLKO through the PCB trace that connects half of the attached SDRAMs, so that SCLKI is at the end of the trace. The maximum frequency of SCLKI is 125 MHz; it is asynchronous to the device clock.
SCLKO[2:0] O Memory Clock Out. Used to clock the attached SDRAM. SCLK operates at up to 125 MHz, and is asyn-chronous to the device clock. Each clock output drives up to four SDRAM clock loads, the trace, and the SCLKI pin load. At high clock frequencies, assume this trace to be a transmission line, and route it accordingly.
SCS[1:0] O SDRAM Chip Selects. Select between two banks of SDRAM. A high level indicates that the command to the selected SDRAM is valid. SCS[0] corresponds to the lower address space. SCS[1] corresponds to the upper address space. Maximum fanout is four SDRAM loads.
SDQM[7:0] O SDRAM Data Input/Output Mask. The 64-bit bus can be accessed as eight bytes during writes. This ensures compatibility with the BLT engine write requirements. SDQM[7] selects the most significant byte. SDQM[0] selects the least significant byte. Maximum fanout is two SDRAM loads per pin.
SRAS O SDRAM Row Address Strobe. When sampled at the rising edge of SCLK, this signal defines the opera-tion of the SDRAM. The maximum fanout is eight SDRAM loads.
SWE O SDRAM Write Enable. When sampled at the rising edge of SCLK, this signal defines the operation of the SDRAM. The maximum fanout is eight SDRAM loads.
Primary Video Output
BLUE/PB AO Blue/Pb Pixel data output. This analog output comes from an 8-bit integrated D-A converter. It can drive a doubly terminated 75-Ω load (37.5 Ω equivalent load).
GREEN/Y AO Green/Y Pixel data output. This analog output comes from an 8-bit integrated D-A converter. It can drive a doubly terminated 75-Ω load (37.5 Ω equivalent load).
RED/PR AO Red/Pr Pixel data output. This analog output comes from an 8-bit integrated D-A converter. It can drive a doubly terminated 75-Ω load (37.5 Ω equivalent load).
DDC0 (GPIO)
O(I/O)
General-purpose I/O, suitable for use with the DDC monitor clock. (DDC is a standard for digital control of computer and TV monitors based on the Philips I2C interface and widely supported by “Plug & Play” computer monitors.)
DDC1 (GPIO) I/O General-purpose I/O, suitable for use with DDC data.
HSYNC (CSYNC)(GPIO)
I/O Primary Horizontal Sync Output. When asserted at the rising edge of PCLK, HSYNC indicates the hori-zontal sync for the primary video output. Software selects this pin to be input or output. It is an input immediately following reset. CSYNC supports external analog NTSC encoder chips for use in low-cost down-converters. This signal may be programmed to output HBLANK timing.
OSDP O On-Screen Display (OSD) Present. Assertion HIGH of this output indicates the OSD is present during pixel time. This signal can be used to control external graphics mixing.
PCLK I Pixel Clock Input. This is the optional video clock supplied from an external source. Its maximum fre-quency is 27 MHz.
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PIXOUT[23:0](GPIO)
O(I/O)
Digital video data output. RGB output in compliance with SMPTE 274M, SMPTE 296M, and SMPTE293M formats.PIXOUT[7:0] = RED[7:0], Pr[7:0] (24-bit mode) = PbPr[7:0] (16-bit mode) PIXOUT[15:8] = GREEN[7:0], Y[7:0] (24-bit mode) = Y[7:0] (16-bit mode) = YPbPr[7:0] (8-bit mode) PIXOUT[23:16] = BLUE[7:0], Pb[7:0] (24-bit mode)
VSYNC (GPIO) I/O Primary Vertical Sync Output. When asserted at the rising edge of PCLK, VSYNC indicates the vertical sync for the primary video output. Software selects this pin to be input or output. It is an input immedi-ately following reset. This signal may be programmed to output VBLANK timing.
Auxiliary Video Output
AUXO[7:0] O Eight bit, parallel pixel data output. The format is YCbCr 4:2:2 digital video (ITU-R 656, ITU-R 601).
VCLKO O Video Clock Output. The clock frequency is nominally 27 MHz with a 27 MHz device clock.
Video Inputs
PIXIN[7:0] I Pixel Input. This eight-bit bus is used to input video from an external video source. The format is YCbCr, 4:2:2 digital video (ITU-R 656, ITU-R 601, SMPTE 125M).
VCLKI I Video Clock In. A clock signal, nominally 27 MHz, from an external video source. The signal does not have to be synchronous to the device clock.
VVLD I Video valid signal indicating that the data on PIXIN[7:0] is valid.
Audio Input/Output
ACLK I/O Audio Clock. This clock is 256 or 384 times the audio sample clock (LRCLK). It is used to generate the IEC-958 formatted output. It is divided to create the BCLK and LRCLK.
ADATAI[2:0] I Serial Audio Data Input. Audio data are input on these pins, clocked by BCLK and framed by LRCLK. There are up to six audio channels, which must have the same sample rate.
ADATAO[2:0] O Serial Audio Data Output. Audio data are output on these pins, clocked by BCLK. There are up to six audio channels. All audio output channels must have the same sample rate.
BCLK I/O Bit Clock. Software determines whether this pin is an input or an output. As an output, it provides a serial audio clock with software selectable frequency. The clock is typically n times the audio sample rate, where n = 32, 48, 64, or 128. As an input, it represents a serial clock for LRCLK and ADATAO. It is nominally 64 times the audio sample rate. This pin is configured as an input upon device reset.
LRCLK I/O Left/Right Channel Selector. Software determines whether this pin is an input or an output. LRCLK indicates left and right channel selection on the serial audio input; it also indicates the audio sample rate. The polarity of LRCLK is programmable. As an output, LRCLK transitions at the sample rate. As an input, LRCLK determines the sample rate. In this case, the timing accuracy of LRCLK determines the positional accuracy of the output samples.
IECOUT O This output carries audio data formatted in IEC 958 format. This signal can be used to drive external hardware audio decoders.
Coded Data Input
CCLK I Coded Data Clock. Clocks CDATA on the rising edge. This clock is asynchronous to other clocks in the system.
CDATA[7:0] I Coded Data Stream. An MPEG2 transport stream at up to 80 Mbits/sec.
CFRAME I When high, this signal indicates that the current CDATA byte is the first byte in the MPEG frame.
CDVALID I This signal indicates that the data on CDATA[7:0] is valid.
CPWM O Pulse Width Modulator for VCXO Control. This signal is generated to control the VCXO frequency for System Time Clock Recovery (PCR recovery from transport streams).
Boundary Scan/ PCI configuration EEPROM Interface
TCLK/EE_SK I Test Clock for boundary scan./PCI configuration EEPROM serial clock.
TDI/EE_DI I Test Data Input. This is used for boundary scan./PCI configuration EEPROM data output.
TDO/EE_DO O Test Data Out. This is used for boundary scan./PCI configuration EEPROM address/mode input.
SYMBOL I/O DESCRIPTION
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TMS I Test Mode Select. This is used for boundary scan.
TRST I Test Reset. This is used for boundary scan.
EE_CS O PCI configuration EEPROM chip select.
PCI Interface
AD[31:0] I/O Address and data multiplexed on the same PCI pins. A bus transaction consists of an address phase, fol-lowed by one or more data phases.
C/BE[3:0] I/O Bus command and byte enable are multiplexed on the same PCI pins. During the address phase of a transaction, they define the bus command. During the data phase, they are used as byte enables.
HCLK I Provides timing for all transactions on the PCI bus. Operates at 54 MHz.
DEVSEL I/O Device select, when actively driven, indicates the driving device has decoded its address as the target of the current access.
FRAME I/O Cycle frame is driven by the current master to indicate the beginning and duration of an access.
GNT I The PCI bus arbiter drives this pin active to grant control of the PCI bus to the TL850C.
IDSEL I Initialization device select is used as a chip select during configuration read and write transactions.
INTA O Used to request an interrupt.
IRDY I/O Initiator ready indicates the bus master’s ability to complete the current data phase of the transaction.
PAR I/O Parity is even parity across AD[31:0] and C/BE[3:0].
PERR I/O Parity Error is for reporting data parity data errors during all PCI transactions except a Special Cycle.
REQ O The TL850C drives this pin active to request control of the PCI bus.
RST I Active LOW reset signal from the PCI bus.
SERR I/O System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result is fatal.
STOP I/O Indicates that the TL850C is requesting the master to stop the current transaction.
TRDY I/O Target ready indicates the TL850C’s ability to complete the current data phase of the transaction.
Display DAC Interface
COMP AI Voltage reference for the Display DACs. This DAC-related signal connects to a 0.01µF capacitor to AVDD (5V).
RSET AI Set point resistor for the internal DAC. A 370Ω 1% resistor is required between RSET and AGND.
VREFIN AI Voltage reference for the Display DACs. It connects with VREFOUT to a 0.01µF capacitor to GND.
VREFOUT AO Voltage reference for the Display DACs. It connects with VREFIN to a 0.01µF capacitor to GND.
Analog Power
AGND GND Analog ground and power pins for noise isolation of the internal DAC. AGND must be common with digital ground but tightly decoupled to AVDD. AVDD must be isolated from VDD. See Figure 7.AVDD VDD
PGND GND Analog ground and power pins for noise isolation of the internal clock synthesizer for VCLKI. PGND must be common with digital ground but tightly decoupled to PVDD. See Figure 7.PVDD VDD
SGND GND Analog ground and power pins for noise isolation of the internal clock synthesizer for SCLKO. SGND must be common with digital ground but tightly decoupled to SVDD. See Figure 7.SVDD VDD
VGND GND Analog ground and power pins for noise isolation of the internal clock synthesizer. VGND must be com-mon with digital ground but tightly decoupled to VVDD. See Figure 7.VVDD VDD
Digital Power
CGND GND Digital ground and power for the core logic.
CVDD VDD
SYMBOL I/O DESCRIPTION
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Figure 7 Isolation of AVDD from VDD
5. ARCHITECTURE DESCRIPTION
Figure 8 is a block diagram of the TeraLogic TL850C. The majorcomponent blocks are described in the following subsections.
IGND GND Digital ground and power for the I/O.
IVDD VDD
Miscellaneous
BUSCLK O This clock is the PCI/CPU clock. It operates between 33 MHz and 133 MHz.
CLKIN I Device clock. Nominally 27 MHz. This clock is internally multiplied by three to produce the operating clock frequency.
PLL_BP I This input must be left unconnected for proper operation of your system.
SYMBOL I/O DESCRIPTION
0.1 µF
10 µHAVDD, VVDD
AGND, VGND
VDD
GNDVDD = Digital VDDGND = Digital GND
PVDD, SVDD
PGND, SGND
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Figure 8 TL850C Block Diagram
5.1 MPEG2 MP@HL Decoder Engine Architecture Overview
As shown in Figure 9, the Decoder Engine incorporates a special-purpose datapath and an on-chip microcontroller. The datapath
performs all computationally intensive operations; the microcontrollerperforms most of the control operations. The microcontroller containsfirmware provided by TeraLogic for the application.
SDRAMInterface
64 14
CtlAddrData
8
VideoCapture
YCC
AudioCapture
Y/C SeparatedDigitized Video
PCI Interface
32
CtlAddr/Data
PCI/DRAMBridge
32 32
GraphicsAccelerator
MP@HL(ATSC) decoder
Video Processor& Compositing
Audio Processor& Compositing
Audio StreamsPlayer
TVAudio
AC3Audio
TransportDemux
8
FromDemodulator
Valid
DACs
RGBSyncsAudio Out
128-bit Internal Bus
To on-chipperipherals
ParallelVideo Out
PIXOUT[23:0]
FilterEngine
AUXVideo Out
Aux. Video Out(SMPTE 125M)
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Figure 9 Decoder Engine Block Diagram
The Top-Of-Channel (TOC) DMA controller reads the MPEGbitstream from a circular buffer maintained in memory. The TOCDMA is configured by the CPU at the beginning of operation, or ateach context switch. The TOC DMA tries to keep the TOC Buffer full,and transfers data to it when it is enabled and there is sufficient spacein the buffer for a complete burst of data.
The microcontroller begins by instructing the Sync Detect circuit tofind the next sync code. This circuit searches the TOC until a synccode is detected. The microcontroller then examines the byte at thetop of the TOC buffer. If it is not a slice start code, the microcontrollergenerates an interrupt to the CPU, then waits for a command from itshost control port. If it is a slice level start code, the microcontrollerbegins to process the slice under control of its firmware. If necessary,the header data has already been parsed by the CPU and
communicated to the microcontroller; this processing parses the slicepayload. Otherwise, the processing requires searching for the nextsync code using the Sync Detect circuit.
When the CPU is interrupted by the microcontroller, it accesses theTOC through the multiplexer. Since the microcontroller does notaccess the Control Bus while waiting for activity on the Control/Param port, the CPU can use a shared control bus. The CPU has fastaccess to the TOC buffer in the Memory Interface (MIF) since this isthe sole activity of the MPEG engine at this time. The TOC bufferappears to the CPU as a small random access memory. It reads thefirst byte in the TOC to determine how to retire the payload. With theexception of a slice, the payload can be for any video structure,including PES header. The CPU can read subsequent words from theTOC Buffer, as necessary, under application program control. After
Top ofChannel
DMA
Mux
Top ofChannel
Buffer
VLD/
Internal Memory Bus (A-bus)
Source/Dest Block
DMA
Half PelInterpolation/
ZZ-1/Interstage
Delay
IDCTRLD/
QuantTables
Boot ROM
MicroProgram
RAMMCUCore
RAM
HostControl/Param
Register file
Host CPU Bus
Microcontroller Bus
Memory Controller Bus
Pipeline
Memory
Logic
Microcontroller
SyncDetect
Control bus
AMR Up
Q-1
Internal Memory Bus (C-bus)
Memory
WriteBuffer
ReadBuffer
TOCRandom
Access
Interface(MIF)
abcde
a
bbb b
b b
bb
c c
c c c c c
d
d
d d d
ea
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parsing part, or all, of the header, the CPU can instruct the DMAcontroller to discard a number of bytes from the front of the TOCBuffer. These are bytes that the CPU has read, parsed, and are nolonger required. This operation continues until the CPU encounters aslice start code, or exits the PES header. The CPU then instructs theDMA controller to advance the TOC to that point.
The CPU uses the parameters extracted from the stream to inform themicrocontroller of the attributes of this image or image sequence. TheCPU writes a parameter set to the Control/Param port, and signals themicrocontroller to resume interpreting the parameters.
If the TL850C is decoding more than one stream, the parameter listmust be completely updated each presentation unit, since themicrocontroller lacks sufficient storage for more than one context.
Once provided with a correctly formatted parameter list, themicrocontroller can resume processing the slice. It issues a dispatch tothe Variable Length Decoder/Run Length Decoder (VLD/RLD)circuit, which is capable of performing macroblock header parsingand block VLD in hardware. The header parsing is done in hardwareto maximize throughput and minimize load on the microcontroller.The RLD expands the run-length code into block coefficients andempties them into the ZZ buffer, which is also used as an interstagepipeline delay. The macroblock parameters from the macroblockheader are made available as a series of registers that can be read bythe microcontroller.
The microcontroller uses these parameters to set the mode of thereconstruction datapath (Inverse Discrete Cosine Transfer [IDCT] andHalf Pel Interpolator [HPI]) and to program the Source/Dest BlockDMA unit. To do this, the microcontroller performs a series ofarithmetic operations to compute the address of the source anddestination blocks. These operations are the principal role of themicrocontroller during normal operation. Once the functional blockshave been configured, the microcontroller issues a dispatch to them.At this point, macroblock decoding completes by itself, so themicrocontroller can continue with the next macroblock.
5.1.1 Software/Firmware/Hardware Partitioning
The general-purpose CPU parses the stream above the slice level. Theon-chip microcontroller processes the slice level and macroblockheader. The macroblock pipeline is a custom datapath dispatched bythe microcontroller. The system timebase is set by the scheduler in thememory controller.
5.1.2 Advanced Memory Reduction (AMR)
This technology reduces the amount of memory required to decode aHD sequence while simultaneously performing down-conversion. It isnot strictly MPEG compliant, since the predictor is modified.
AMR supplies near-lossless 2:1 compression of framestores, whichallows HD decoding and display to operate in less than 8 Mbytes ofmemory. It also supplies a 4:1 compression mode for use in down-conversion applications, where, for example, the output is always astandard definition display. This mode requires only 4 Mbytes ofmemory for HD decoding and display with down-conversion.
AMR can also be used when displaying a graphics overlay on video.The memory saved can be used for graphics framestore.
5.2 Transport Framer
The TL850C integrates a Transport Framer/Parser to facilitate the useof software controlled transport stream decoding. The framer/parsersupports an unlimited number of PIDs. You can select multiple videoand audio streams concurrently. A block diagram of the transportframer/parser is shown in Figure 10.
Figure 10 Transport Framer Block Diagram
5.2.1 Packet Framing
Transport packets arrive one byte at a time over an eight-bitasynchronous interface or from the PCI bus. The sustained rate shouldnot exceed 80 Mbits/sec for more than two packet periods. At anytime, the framer is in one of three states: locked, unlocked, or hunting.The framer is locked when the sync byte has been found at theexpected position for the last three received frames. It becomesunlocked once the framer fails to detect the sync byte a certain numberof times (programmable) at the expected position. It then remainsunlocked until directed by the CPU to enter hunt mode. Here, theframer searches for three consecutive frames in which the sync code isat the expected position, at which point the framer becomes lockedagain. The framer passes frames to the parser stage only when it islocked.
5.2.2 Packet Parsing
Once a packet has been framed, it can be parsed. The MCU handles allpacket processing. Multiple packets can be buffered in the MCU dataRAM during processing. To allow for CPU latency, there is a FIFObetween the Packet Framer and the Packet Parser.
5.2.2.1 Program Clock Reference (PCR) Recovery
The TL850C maintains a local, 48-bit System Time Clock Recovery(SCR) counter clocked by the 27-MHz system clock. This counter islatched into a register at the same time as the interrupt is generated(when a complete transport packet is in the local buffer). The value inthis register can be read by the MCU as part of the PCR recoveryprocess. Note that the latched value can vary from the ideal timebecause of time delay in the FIFO. This effect is indistinguishable
SCR Counter
Framer
MCU
DMAChannel
DataRAM
PWM Control
AddrData
CPU Data
CPU Address
Out
Ofs
Latch
TransportStream
27 MHz
PWM Out
Random
In
Access
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from network jitter, and can easily be corrected by filtering the SCRvalues.
5.2.2.2 Header Handler
The MCU reads the header word, performs some processingoperations on it, and then indicates to the TL850C hardware how toretire the packet.
5.2.3 Adaptation Field Processing
The TL850C can allow CPU access to the adaptation field after thepacket is retired. The CPU can read the contents of the local buffer,which holds the transport packet payload.
5.2.3.1 Accessing the Adaptation Field
The adaptation field is stored in a system buffer in SDRAM as 32-bitwords, in accordance with the syntax in ISO/IEC 13818-1, Table 2.6.The CPU can access this data directly to parse it.
5.2.3.2 System Time Clock Recovery
The adaptation field can include the PCR. The CPU must subtract thePCR from the Current_SCR counter, filter the result, provide gain andDC offset, if necessary, and use the resulting value to control the 27-MHz VCXO. The TL850C supplies a Pulse Width Modulated outputthat, after external analog filtering, can drive the VCXO frequencycontrol voltage.
5.2.4 DMA Channel
There is a single DMA channel shared by all transport streams. It isprogrammed by the MCU after the header is parsed. It thenautonomously transfers the data in the payload to the location inmemory indicated by the DMA channel write pointer. The DMAcontroller manages a circular buffer, limited by the Start and Endpointers. The write pointer is incremented by the number of byteswritten to memory. Once it crosses the end pointer, the write pointerwraps back to the start pointer.
5.3 Display Processor
The display processor reads data from the framestore, reformats it ifnecessary, and outputs it to a display device. There are two types ofdata object: video and graphics. Video objects are stored in YCC colorspace and might require horizontal, vertical, and temporal sample rateconversion. Graphics objects are stored as indexed bitmaps or as colormapped bitmaps; they do not undergo sample rate conversion.
The display processor supports multiple video objects, multiplegraphic objects, and a hardware cursor. They are composited anddisplayed in real-time in one of several formats.
Display formats can match the standardized ones exactly, or they canbe modified to reduce the cost of the TV tube drive electronics. Forexample, the sample rate can be increased to give a larger horizontalblanking interval; this, in turn, can relax the specification on the driveelectronics and horizontal deflection coil.
If the frame rate matches the standard composite video frame rate(e.g., 29.97 for NTSC), an auxiliary video output can produce adownsampled standard definition output at the same time as high-definition video is being displayed. This feature is for home analogVCR recording.
Up to four standard definition video channels can be composited onthe display. Each video channel can be independently scaled andpositioned. This feature is for viewing of multiplex programming.
5.3.1 Primary Display Timebase Generation
The display processor generates the timebase for a raster-scanneddisplay device. It uses an externally supplied reference clock at therequired sample frequency (see Figure 11). The timebase generator isprogrammable and supports a large number of possible displaytimings. The sample frequency can be up to 100 MHz.
Figure 11 Display Processor Block Diagram
5.3.1.1 Base Scanning Formats
Base scanning formats are required to support standardized scanningrates for digital television. The TL850C supports all ATSC scanningrates.
Note that the best frame rate is 59.94/1:1 or 59.94/2:1, since thedevice can support simultaneous standard definition video out in thesemodes.
5.3.1.2 Extended Scanning Formats
Extended scanning formats can be achieved by increasing the samplefrequency and reprogramming the horizontal timing parameters.These formats reduce the cost of horizontal scan coil and driveelectronics by relaxing their requirements. Note that the vertical scanremains constant.
TimebaseGenerator
PrimaryVideo
Output
VideoFIFO
GraphicsFIFO
VideoSource
GraphicsSource
Analog
HSync
VSync
Reference
SecondaryVideo
ITU-R 601/656
Sample Clock
PLL(nominally ~ 27 MHz)
Programmable
CLK
Display Clock
Clock
output
OutputDigital
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The typical sampling frequency supported by the device is 81 MHz.Assuming that the horizontal line time remains constant, the numberof samples per total line can increase to 2400 in this case. Because thesamples per active line remains constant, the blanking interval canincrease to 480 samples at 81 MHz, or about 5.93 µs. This valuecompares favorably with 3.77 µs at 74.25 MHz.
5.3.2 Primary Video Output
The primary video output is used to output video in the formatprogrammed by the timebase generator. It consists of a chroma upsample, color space converter, and DAC. Sin X/X correction filter isintegrated.
There are two sources of data for the primary output: the videochannel, and the graphics channel. The video channel is in YCC colorspace; the graphics channel is in RGB or YCC space. The graphicschannel also contains alpha information. You can select which ofthese two channels undergoes color space conversion. The twostreams, which are now in a common color space, are then combinedusing the graphics channel per-pixel alpha, a global alpha, and aselected composition method. Finally, the combined stream ispresented to the DACs, where it is converted to analog RGB or YCC.
5.3.2.1 Alpha Compositing
The graphics channel presents an alpha value per pixel. This iscombined with a global alpha using the composition methods shownin Table 1.
5.3.2.2 Color Space Conversion
This fully programmable matrix converts between color spaces. It alsoperforms linear transformations on the color space, such asmodification to hue, saturation, and brightness. The results are clippedto the range 0 to 255.
The TL850C provides an optional color space conversion from ATSCto NTSC color (digital to standard format).
5.3.2.3 Image Compositing
Graphics and video are composited using alpha channel data from thegraphics channel, according to the following formula:
COi = ac*CGi + (1-ac)*CVi
where CG is a graphics channel component, CV is a video channelcomponent, CO is the resulting composited output component, and i iseither (R,G,B) or (YCC), depending on the output color space.
5.3.3 Sample Rate Conversion
The TL850C can up-convert or down-convert video sequences beforedisplay. Down-conversion uses a functional block referred to as aFilter Engine; up-conversion uses an in-line interpolator.
5.3.3.1 Filter Engine
The Filter Engine performs one- and/or two-dimensional signalprocessing operations on two-dimensional rectangular overlappingpatches of image data. Mainly, it down-samples an image using high-quality filtering operations.
Coefficients of the filter are programmable. For example, low-passequiripple filters can perform as shown in Table 2.
To avoid aliasing in the resampled image requires a stopbandattenuation of approximately 40 dB.
The decoded picture in memory is read by the Filter Engine, filtered,resampled, and written back to memory at the size required fordisplay. The TL850C integrates a 17-tap, low-pass filter, followed bya 4-tap, 16-phase interpolator for both horizontal and verticaldecimation. This produces completely anti-aliased down-convertedimages. The response of the low-pass filter is user-programmable.
5.3.3.2 Deinterlacing Video
The Filter Engine can be used to deinterlace a video sequence, eitherfrom the video capture port or from the MPEG2 decoder. This isreferred to as line doubling. The engine tries to detect motion in theimage by correlating the current field and the previous field for everypixel in the image. If the pixel in the previous field is highly correlatedwith its neighbors in the current field, it is assumed there is no motionbetween the two fields, and the previous field pixel is used tosynthesize a new output line. If there is poor correlation, it is assumedthat there is motion, and the pixel is synthesized from the current fieldonly using edge-directed interpolation. This interpolation methodavoids “jaggies” on interpolated objects edges. The deinterlacemethod adaptively modifies itself between sharpness and motionreproduction.
Table 1: Alpha Composition Methods
Code Name Operation
00 Replace [ac,R,G,B] = [ag,R,G,B]
01 Darken [ac,R,G,B] = [ap, ag*R, ag*G, ag *B]
10 Opaque [ac,R,G,B] = [ag*ap, R, G, B]
11 Fade [ac,R,G,B] = [ag*ap, ag*R, ag*G, ag*B]
Table 2: Filter Programmability
Stopband Attenuation Transition Bandwidth1
1. Transition Bandwidth = (wr - wp)/2pi.
>30 dB 0.070
>40 dB 0.110
>50 dB 0.125
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5.3.3.3 Picture-in-Picture
The Filter Engine can scale more than one image if the source imagesare lower resolution. For example, if multiple standard definitionsequences being decoded, the Filter Engine can scale each of them insequence to different locations in memory for composition by thedisplay processor. The scaled images can overlap each other inmemory, since the Filter Engine only has to process them in back-to-front sequence. This allows many dynamic user interface effects inPIP mode.
The Filter Engine is a general-purpose scaler. Any sequence that canbe decoded by the MPEG engine can also be scaled by the FilterEngine.
5.3.4 Background Graphics
If the scaled video picture is smaller than the display, the output buffercan be configured to be the same size as the display, and the scaledpicture can be written inside it by the Filter Engine. The unused partsof the output buffer can be allocated for “background graphics”.Background graphics must be in YUV 4:2:0.
5.3.5 Anamorphic Projection of 4:3 Source to 16:9 Display
If a 4:3 source video is to be displayed over the entire area of a 16:9display, it must undergo anamorphic projection (i.e., the horizontaland vertical scale factors are not the same). This can producedistortion that is unacceptable to many viewers. There are three waysto correct the distortion: underscanning, overscanning, and non-uniform projection.
5.3.5.1 Underscanning
When underscanning, the 4:3 source video occupies only part of thedisplay. The unused areas are set to a default color, usually black. Thiscan be combined with a slight amorphism, so that the unused areas aremade smaller. Underscanning is done by programming the startlocation and interpolation rate of the source image.
5.3.5.2 Overscanning
When overscanning, the 4:3 source video occupies the entire width ofthe screen, but the top and/or bottom of the picture is cropped. Thiscan be combined with a slight amorphism, so that less area is cropped.Overscanning is done by programming the start location andinterpolation rate of the source image.
5.3.5.3 Nonuniform Projection
Here, the center of the image undergoes a near-isomorphic projection.The edges of the image undergo a more severe isomorphic projection.Consider the 16:9 image segmented as shown in Figure 12. Most ofthe area of interest is in segment 4. To reduce perceived distortion,segment 4 must be as uniform as possible. Regions 1, 2, and 3 areregarded as the border; these are less important because of psycho-visual effects, which make the viewer tolerant of isomorphicdistortion in these areas.
Figure 12 Nonuniform Projection
The TL850C can support different interpolation ratios for each of thesegments: 1, 2, 3, 4. As shown in Figure 12, it has two sets ofinterpolation parameters for each horizontal and vertical scanningdirection, and switches between interpolators at programmedboundaries. In the literature, the aspect ratios of 1 to 1.5, 1.4, 1.153,and 1.077 are chosen for regions 1, 2, 3, and 4, respectively.
5.3.6 Graphics Overlay
For overlay, a graphics channel is composited with video inside thePrimary Video Output unit. The following subsections describe howthe graphics plane is delivered to the composing circuit.
5.3.6.1 Graphics Plane Storage
The graphics plane is stored in memory as a contiguous array of bytes.It is fetched from memory, then passed through format conversionlogic to the compositor.
The sample rate of the graphics plane is always an integer multiple ofthe sample rate of the display system. It is not possible to scale thegraphics plane except by integer scale factors.
5.3.6.2 Palette Expansion
The TL850C integrates a 256 x 32-bit memory used for colorexpansion (see Figure 13). The outputs of the palette memory are R/(Y-R), G/Y, B/(Y-B) and A (alpha). Indexed colors are first expandedto 8i using a mapping table, then applied to the input of the palettememory.
Figure 13 Color Palette Expansion Scheme
1 1
1 1
2
2
3 34
x1 x2
y1
y2
2bpp
4bpp
8bpp
Map Table 4 to 8
Map Table 2 to 8
Mux LUT
G/Y
R(Y-R)
B(Y-B)
Alpha
256 x 32
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The map tables contain 16 and 4 entries, respectively. They are loadedusing the palette loading mechanism, described in Section 5.3.7. If thegraphics mode has its own alpha channel (for example, 8a8i), the pixelalpha replaces the alpha from the LUT.
5.3.6.3 Direct Mapped Expansion
This mode is used for pixels with high color depth: 8, 16, and 32 colorbits. The pixels are expanded up to 24-bit RGB by copying theavailable bits into the LSBs of the expanded color component, MSBfirst, and repeating, as necessary. For example, the three-bit value 011becomes 011,011,01 in eight-bit format. This method correctlypreserves the dynamic range.
The alpha channel can come from the color palette, or from directmapping. It can have four or eight bits in direct map mode. It isexpanded up to eight bits using the following means:a[8] = a[4] * 8 * (1 + 1/16). This yields correct values for 0 (transparency) and 15 (opacity). Ifthere is no alpha channel, it is derived from a global alpha channelregister.
5.3.6.4 Global Graphics Control
The graphics overlay is controlled by a set of global parameters and adisplay list.
The graphics plane can be enabled or disabled. A TL850C registerprovides the pointer to a display list held in memory. The display listis parsed by the TL850C to produce the graphics overlay in real-time.
The graphics overlay is described by a display list containing a seriesof descriptors for each of the multiple regions in the display. Thedisplay list is scanned by the display processor as it renders thedisplay. The process then fetches pixel map data and color palettedata, as directed by the display list. Each display list descriptor is 128bits long. There is an implementation limit of one active graphicsregion per scan line.
5.3.7 Palette Descriptor
If the display list links to a palette descriptor, the color palette can beupdated dynamically. The palette update can not occur to the samepalette entries as those currently being displayed. This means:
1. Updates of small (16 entry) palettes can occur during the hori-zontal blanking interval.
2. Updates of large (256 entry) palettes must occur when no pallet-ized pixmap is displayed. There must be at least one display scan line between palletized pixmaps that use different palettes.
5.3.7.1 Scaling of the Graphics Plane
The graphics plane can be scaled by integer amounts. Horizontalscaling is by pixel replication. Vertical scaling is by line duplication.The horizontal and vertical scale factors can be independently set.
Graphics pixels are square in most ATSC modes, including the high-definition modes, so aspect ratio correction in the graphics plane is notperformed.
5.3.7.2 Cursor Plane
The TL850C supports a 32 x 32 pixel hardware cursor at 4 bpp. Itoverlays the video and graphics planes. The cursor is composited withthe combined video and graphics planes just before the video outputstage.
5.3.7.3 Hardware Anti-Flicker Filter
An anti-flicker filter supports four- and eight-bit palletized bitmaps. Itdoes not support direct mapped bitmaps, since the line delay requiredis much larger line delay. Also, the anti-flicker operation can besimulated in software, or using prefiltered fonts.
Anti-flicker uses a three-tap filter vertical on the output graphicsimage. Any scaling of the graphics plane is applied before the anti-flicker filter.
5.3.8 Digital-to-Analog Converters (DACs)
Three 8-bit DACs operate at up to 100 MHz. Table 3 shows thespecifications for these converters.
Each DAC drives into a 75-Ω, doubly terminated load. There is adynamic range of 700 mV in each DAC. The reference black levelcorresponds to the DAC input 0; the reference white level correspondsto the DAC input 255.
In YCC output mode, the Y channel reference black corresponds tothe DAC input 0. The Cb and Cr channel reference level correspondsto the DAC input 128 (350 mV). Values in the active video region areconstrained to 16-240, (43-656mV).
5.3.9 Digital Video Output
The digital video output provides a 24-bit RGB/YCC or a 16-bit/8-bitYCC output, timing compatible with the SMPTE 274M, SMPTE296M, and SMPTE 293M standards for users not wishing to use theinternal DACs, users wishing to use an external scan converter, or forfactory testing of the TL850C with or without the DACs.
For users interested in using the TL850C internal DACs, the samedigital video output is fed into the DACs and analog RGB/YCC canbe used. Tri-level sync as specified by the EIA770 standard isimplemented on the analog outputs. The EIA770.3 output through the
Table 3: DAC Specifications
Parameter Min Typ Max Units
Output Voltage 1.5 V
Output Current 21 mA
Full Scale Error ± 5 %
DAC to DAC Correlation 1.27 %
DAC Linearity ± 2 LSB
Glitch Energy 200 ps
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primary video output port is EIA805 compatible. It supports CGMSand data output during blanking.
All video output signals can be copy-protected using CGMS Layer 1/2and DirecTV CGMS.
Progressive mode SMPTE 274M is not supported. For true SMPTE274M, SMPTE296M, and SMPTE 293M compatibility, users couldsupply an external clock at the sample rate (nominally 74.25 MHz),which would be ideally locked to the system clock using an externalPLL or can use the internally generated clock. The maximumscanning rate of this interface can be up to ~100MHz.
5.4 NTSC Video Integration
5.4.1 Video Input and Post Processing
The Video Input Unit captures ITU-R 656 formatted video stream.
The video input is asynchronous to the device clock. The videochannels first are synchronized to the device clock. The video input isassumed to be in ITU-R 656 eight-bit parallel format. The device canslave to the SAV/EAV sync words embedded in the ITU-R 656 streamor to the optional external video syncs (VSYNC and HSYNC).
An active region of interest (ROI) can be defined in the source imageto implement a cropping function. The ROI also can be used toimplement a panning feature. The starting and ending coordinates ofthe ROI must be on an even pixel. Channels 0 and 1 are independentlyprogrammed and have identical features.
Brightness and contrast are performed on the luma component, wherebrightness is an offset adjustment to achieve “blackness” of thepicture, and contrast is a scale factor to expand the range betweenblack and white. Brightness and contrast are performed on the lumacomponent as shown in the following equation. Y’ is clipped to arange between 16 and 235.
Y’ = (Y-16) * CONTRAST + BRIGHTNESS
Saturation is a scaling of the chroma component to adjust colordifference as shown in the following equation. Cb’ and Cr’ are clippedto the range (16,240).
Cb’ (Cr’) = (Cb (Cr) - 128)* SATURATION + 128
5.4.2 Video Input Functional Timing
Figure 14 through Figure 16 show the timing of the expected digitalvideo input.
When using an external HSYNC and VSYNC to detect the even-oddfield, the TL850C checks if the falling edge of VSYNC is coincidentto the falling edge of HSYNC (within a certain time window). If theedges are coincident, the field is odd (first).
Figure 14 Digital Video Input Timing
Figure 15 Video Line Timing for PAL
Figure 16 Video Line Timing for NTSC
5.4.3 Secondary Video Output
The secondary video output resamples the video stream at the primaryoutput to produce a video stream compatible with ITU-R 656/ITU-R601. This stream can be used for home video recording when attachedto an external composite video encoder on the PCB. The secondaryvideo output carries the same programming as the primary output,with the exception that 16:9 programming is reformatted to 4:3 pan &scan video. It is not possible to display 16:9 video in letterbox formatunless the primary output is also in letterbox format (i.e., also in a 4:3aspect ratio). Finally, the primary output must have the same framerate (or field rate) as the secondary output. If the primary output is at59.94 frames/sec (progressive); the secondary is at 59.94 fields/sec(interlaced).
Figure 17 shows the video integration process for NTSC and PAL.
VCLKI
Cb0 Y0 Cr0PIXIN
864T cycles (@ 13.5 MHz)
Active line: 720 Luma +360 Cb and Cr samples 12T132T
50% of Hsync
T = 1/13.5MHz
858T cycles (@ 13.5 MHz)
Active line: 720 Luma +360 Cb and Cr samples 16T122T
50% of Hsync
T = 1/13.5MHz
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Figure 17 NTSC and PAL Video Integration Process
5.4.3.1 Region of Interest (ROI)
The video source can be in 16:9 format. This must be cropped to a 4:3ratio before output on the secondary channel. You can select whichhorizontal span of the source picture is to be displayed. The size of thehorizontal span varies according to the source resolution. Table 4provides recommended values for preserving the aspect ratio.
5.4.3.2 Resampling
Once the horizontal span is known, the output can be resampled toITU-R 601 rates. Horizontal resampling is performed first; thisreduces the number of output sample points to 704. Verticalresampling then reduces the number of scan lines to 243 in each field.
5.5 Graphics Acceleration
The TL850C integrates a 32-bit graphics accelerator, which canperform a comprehensive set of functions on two-dimensional pixelmaps in a variety of pixel map formats.
5.5.1 Pixel Formats
The TL850C supports the pixel formats shown in Table 5. The 1i, 4i,and 4a formats are supported only as source formats.
5.5.2 Color Expansion
If the source and destination pixmaps are in different formats, colorexpansion is required. If the destination format has a different colorspace than the source, the operands are first converted to thedestination format. Table 6 shows the method used for color expansion.Bits from the source color field are copied to the destination color fieldaccording to the mapping shown in the columns R, G, B.
For example, when performing the expansion 8c to 16c, the operationis as shown in Figure 18. The duplication of the MSBs into the LSBsof the expanded color properly preserves the dynamic range.
Figure 18 Color Expansion Example
Table 4: Horizontal Scale Factors
PrimaryActiveImage
ScaleFactor
Region of Interest
Field 1 Field 2
S E S E
1920 x 1080I 2.14 1438 x 1040 45 564 608 1127
1280 x 720P 1.43 960 x 695 30 725 – –
SecondaryROI
HorizontalScaler
Intermediate
ScalerVertical
Results Mem.1408 x 8
OutputFIFO
~2816 x 8
ITU-R 601Timebase
Field
VSync
From Primary RefClk
ITU-R 601ITU-R 601Framing Output
Primary
Input
Threshold
Video
Timebase (27 MHz)
Table 5: TL850C Supported Pixel Formats
Format Description
8c 3:3:2 RGB
16c 5:6:5 RGB
24c 8:8:8 RGB
4a12c 4:4:4:4 aRGB
8a24c 8:8:8:8 aRGB
1i 1-bit index
4i four-bit index
8i eight-bit index
8a8i 8:8 alpha, index
4a four-bit alpha
15c 5:5:5 RGB
YCbCr 4:2:2
Table 6: Color Expansion Method
SRC DST R G B
8c 12c 2,1,0,2 2,1,0,2 1,0,1,0
8c 16c 2,1,0,2,1 2,1,0,2,1,0 1,0,1,0,1
8c 24c 2,1,0,2,1,0,2,1 2,1,0,2,1,0,2,1 1,0,1,0,1,0,1,0
12c 16c 3,2,1,0,3 3,2,1,0,3,2 3,2,1,0,3
12c 24c 3,2,1,0,3,2,1,0 3,2,1,0,3,2,1,0 3,2,1,0,3,2,1,0
1i 8i, 8c, 12c, 16c, 24c
Use foreground, background register
4i 8i Align at LSB of index map
4i,8i 8c, 12c,16c, 24c
Use color look-up table
15 0
7 0R2 R1 R0 G1 G0 B1 B0
R2 R1 R0 G1 G0R2 R1
G2
G2 G2 G1 G0 B1 B0 B1 B1B0
8c
16c
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5.5.3 Supported Operations
Table 7 shows the legal operations for various source and destinationpixmap formats. If a source format has no alpha value, but theoperation requires one, a global (per BLT) alpha value must besupplied in a device register. Expansion of per-pixel alpha values(from four to eight bits) is done via: a[8] = a[4] * 8 * (1 + 1/16)This yields correct values for 0 (transparency) and 15 (opacity).
5.5.4 Boolean Operations
The TL850C supports all 256 possible Boolean raster operations(ROPs) on pixel maps with up to two source bitmaps and onedestination bitmap. The source and destination bitmaps must haveequal size, though they can have different color depths orrepresentation. The ROP codes are identical to those used byMicrosoft Windows. Boolean operations are performed bitwise on theindex or color planes. They are not applied to the alpha plane, ifpresent.
5.5.5 Alpha Channel Operations
The TL850C supports alpha blending between source and destinationpixel maps (see Table 8). The eight-bit alpha mode supports valuesbetween 128 (opaque) and 0 (transparent). The four-bit alpha modesupports values between 15 (opaque) and 0 (transparent).
.
The operation is applied to each color component separately. If thedestination pixel map has an alpha-per-pixel, the destination alphavalue becomes one of the following:
• Sa + Da - Sa * Da
• Sa
• Da
• 1-Sa
• 1-Da.
5.5.6 Color Reduction
If the source pixel map has greater color depth than the destination,color reduction is applied. There are two modes for color reduction:linear and dither. Table 9 shows the method used for n-bit to m-bitlinear color reduction applied to each color component. The ditheralgorithm applies a 2 x 2 pixel error diffusion operation to thedestination pixels during rounding. The quantization error due torounding is weighted according to the destination pixel location withrespect to the pixmap origin and pitch. If the result is <1, thedestination pixel color value is increased by 1.
Table 7: Valid Source/Destination Pixmap Formats
Source Dest Operation
1i 8i BoolOp
1i 8a8i BoolOp, Alpha
4i 8i BoolOp
4i 8a8i BoolOp, Alpha
8i 8i BoolOp
8i 8a8i BoolOp, Alpha
8a8i 8a8i BoolOp, Alpha
1i, 4i, 8i, 8a8i RGB BoolOp, Blend, Reduce
1i, 4i, 8i, 8a8i aRGB BoolOp, Blend, Reduce, Alpha
RGB RGB BoolOp, Blend, Reduce
aRGB RGB BoolOp, Blend, Reduce
RGB aRGB BoolOp, Blend, Reduce, Alpha
aRGB aRGB BoolOp, Blend, Reduce, Alpha
Table 8: Supported Alpha Modes
Mode Equation
S over D Sc + (1 - Sa) * Dc
S in D Da * Sc
S xor D (1-Da) * Sc + (1-Sa) * Dc
S only Sa * Sc
D only Da * Dc
S atop D Da * Sc + (1-Sa) * Dc
D atop S Sa * Dc + (1-Da) * Sc
Special Sa * Sc + (1-Sa) * Dc
Table 9: Linear Color Reduction
n m Operation
4 3 (x[4] − (x[4]>>3) + 2^0) >> 1
4 2 (x[4] − (x[4]>>2) + 2^1) >> 2
5 3 (x[5] − (x[5]>>3) + 2^1) >> 2
5 2 (x[5] − (x[5]>>2) + 2^2) >> 3
5 4 (x[5] − x[5]>>4) + 2^0) >> 1
6 3 (x[6] − (x[6]>>3) + 2^2) >> 3
6 4 (x[6] − (x[6]>>4) + 2^1) >> 2
8 2 (x[8] − (x[8] >>2) + 2^5) >> 6
8 3 (x[8] − (x[8] >>3) + 2^4) >> 5
8 4 (x[8] − (x[8] >>4) + 2^3) >> 4
8 5 (x[8] − (x[8] >>5) + 2^2) >> 3
8 6 (x[8] − (x[8] >>6) + 2^1) >> 2
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5.5.7 YCbCr Conversion
The TL850C can convert YCbCr images to 16c format during BLT.No other operations (Boolean, Alpha) can be performed at the same
time. The conversion uses the following matrix:
The YCbYCr data must be in memory in the byte order Cb, Y, Cr, Y.
5.5.8 Paced Block Transfers (BLTs)
The CPU can program BLT engine operations, or the TL850C canfetch them from a display list maintained in memory. The display listis a linked list of BLT commands, which are executed in sequence bythe TL850C (see section 5.3.6.4). Programmers can use thismechanism to animate graphical sequences without CPU intervention.BLT operations can be suspended until the occurrence of a displayevent or external stimulus. Display events are the display of aspecified scan line or vertical sync. External events are flagged by theCPU writing to a control register. Because the BLT engine writes thecolor palette used by the display controller and BLT engine (forexpansions), changes to the palette can be included in paced BLTs.
5.6 Audio
The TL850C has three stereo audio input ports and three stereo outputports. Input or captured audio streams can be mixed with up to threeother stereo audio streams stored in DRAM (internal audio). TheTL850C also supports full six-channel cross-fading of mixed audio.
Input and output ports follow I2S protocol (three-wire). The TL850Csupports several I2S variations with resolutions up to 24 bits persample. It also includes one IEC-958 compliant output port.
5.6.1 Audio Input Ports
The ports are compatible with the audio output stream of mostMPEG2 decoders and other consumer audio ICs. There is nocompletely standardized audio interface; each manufacturer hasadopted slight variations. Figure 19 shows some of the supportedmodes on the TL850C.
All modes are LRCLK triggered. The left-justified modes clock in upto 24 bits, MSB first. If fewer than 24 bits are available, the LSBs arezero-filled. Note that the number of BCLK cycles in each LRCLKperiod is not defined. The BCLK does not need to be continuous;there can be a large number of cycles for each LRCLK high or low in
which no new LSB bits are presented. The TL850C clocks in at most24 data points; additional BCLK cycles are ignored.
The right-justified mode clocks in up to 24 bits per channel, MSBfirst. Operational modes are controlled by an internal TL850Cregister.
Figure 19 TL850C Supported MPEG2 Audio Modes
5.6.2 Audio Capture
Once the data have been recovered, they can be captured into theattached SDRAM memory. Up to 24 bits of audio data from eachchannel are captured and written to memory. Audio capture also canbe used to capture nonaudio data, which is formatted to be compatiblewith an audio stream (a VCD 2.0 stream, for example). The TL850Csupports up to three capture streams, one from each audio input.
5.6.3 Audio Play
The TL850C can play up to three audio streams from memory. Theaudio data is stored as 16-bit PCM data, either mono, or as a stereopair. The data is fetched from memory at a rate governed by thesample rate. You can set the sample rate for a particular stream in thedevice registers. You can use the audio play feature for user-interfacesounds or other CPU-generated audio, including software AC3decode. Audio capture and audio play can be active at the same time.
5.6.4 Audio Processor
Figure 20 shows a block diagram of the Audio Processor.
R
G
B
1.164 1.596 0
1.164 0.813– 0.392–
1.164 0 2.017
Y 16–( )Cr 128–( )Cb 128–( )
×=
MSB LSB
MSB LSB
LSBMSB
MSB LSB
MSB LSB
MSBMSB
Left Sample Right Sample
BCLK(rckp=1)
BCLK(rckp=0)
LRCLK
ADATA(rrel=0)
ADATA(rrel=1)
BCLK(rckp=1)
BCLK(rckp=0)
LRCLK
ADATA
ddir = 0
ddir = 1
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Figure 20 TL850C Audio Processor Block Diagram
Mix and cross-fade coefficients determine the attenuation or gainapplied to audio samples. In the case of mixing, each coefficientaffects both left and right channels of the corresponding audio stream.In contrast, cross-fade coefficients can be specified independently foreach of the six audio channels (three stereo pairs). A value of 0
corresponds to 100% ( dB) attenuation.
Values between 1 and 195 correspond to an attenuation of 97 to 0 dB(unity gain), respectively, in 0.5 dB increments. Mix coefficientsabove 195 are treated as 195. In the case of cross-fade coefficients,values from 196 to 255 correspond to gains of 0.5 dB to 30 dB,respectively.
The mixing operation blends captured audio (cau) with internal audio(iau) streams. Internal audio streams can be mono or stereo. Internalaudio samples are 16 bits wide. Figure 21 shows how internal audiodata is organized in memory.
Figure 21 Audio Data Organization in Memory
5.6.5 Audio Output
There are three serial audio outputs, each supporting a stereo channel.The output format is programmable to the same extent as the audioinput ports. All audio outputs must operate at the same sample rateand share a common BCLK and LRCLK. BCLK can be generatedinternally or provided from an external source. The internallygenerated BCLK must be an integer multiple of the device clock. Theexternal BCLK is recommended when using most oversamplingDACs.
The IEC-958 output produces an audio stream in IEC-958 format. Thestream can be selected to be one of the three serial audio outputs. TheIEC-958 circuit must receive an external audio clock at 128 times theaudio sample rate.
5.7 Memory Interface (MIF)
This unit supports 32-bit and 64-bit wide SDRAM-based memory atup to 125 MHz. It controls all transactions between the main memoryand other functional modules on the chip.
Figure 22 shows a typical memory configuration that has eight1 M x 16 SDRAM chips, for a total of 16 Mbytes. The chips areconfigured as two banks of 64-bit-wide memory.
Figure 22 Typical Memory Configuration
Route SRAS, SCAS, SWE, and SADR[11:0] to all chips. RouteSCLKO[0] to 4 chips and SCLKO[1] to 4 chips. Return SCLKO[0] toTL850C SCLKI input. Circuit board chip placement and trace routingis critical; contact TeraLogic for more details.
The maximum memory configuration supported by the TL850C useseight 4 M x 16 SDRAMs, for a total of 64 Mbytes, configured in thesame way as shown in Figure 22. The TL850C also supports 1M x 32and 2M x 32 SDRAM chip configurations.
Figure 23 shows a minimum memory configuration which provides4 MB of memory configured as one bank of 32-bit-wide memory.
Figure 23 Minimum Memory Configuration
This configuration is suitable for SD MPEG decode or for HD MPEGdecode using 4-to-1 AMR compression and down-conversion toNTSC resolution.
3 x 23
x 2
3 x
2
3 x
2
In te rna l D M C B us
A D ATA O
IE C O U T
LR C LK
A D ATA I
A udioC apture
I2S
S /P[2 :0] [2 :0]
A udio
P layback
M ix/
C ross
F ade
In ternal
A udio
I2S
P/S
IEC 958
E ncoder
D R A M
Interface
C lock
G en.B C LK
A C L K
∞–
Ln
31 0Rn
Ln+1 Rn+1
An
31 0An+1
An+2 An+3
MonoStereo
SCS1
SCS0
SDATA[63:48], SDQM[7:6]
SDATA[47:32], SDQM[5:4]
SDATA[31:16], SDQM[3:2]
SDATA[15:0], SDQM[1:0]
1 M x 16SDRAM
TL850C
SCS0
SDATA[31:16], SDQM[3:2]
SDATA[15:0], SDQM[1:0]
1 M x 16SDRAM
(for 4:2:0)
1 M x 16 x 8SDRAM
(for 4:2:2)TL850C
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Some possible memory configurations are listed in Table 10. Note thatmemory configurations must be made up of the same memory chips(i.e., do not mix 1 M x 16 with 4 M x 16).
5.8 PCI Bus Interface
Figure 24 shows the PCI Interface. The TL850C PCI Interfacesupports versions 2.1 and 2.2 of the PCI bus specification at up to 54MHz. It can be a master or a slave device on the PCI Bus. TheTL850C responds only to memory bus transactions. I/O PCItransactions are ignored. Internal registers are accessed as memorymapped registers. PCI Configuration registers are implemented asrequired in the PCI specification.
5.8.1 TL850C Interactions with Other PCI Resources
The following subsections discuss access, memory read, memorywrite, I/O read and write, configuration read and write, memory readmultiple, memory read line, as well as memory write and invalidatecycles.
5.8.2 Access Cycles
PCI access cycles are: memory read and write, I/O read and write,configuration read and write, Memory Read Multiple (MRM),Memory Read Line (MRL), and Memory/Write and Invalidate(MWI).
Figure 24 PCI Bus Interface
5.8.3 Read and Write Buffer Coherency
Transactions to SDRAM are buffered in read and write buffers.Transactions to internal on-chip register resources are immediatelyretired (there is a single word write buffer to memory mapped registerresources to allow one-deep coherent write posting).
5.8.4 Configuration
The TL850C implements a standard PCI configuration space,accessed in configuration cycles in which IDSEL is also asserted.Burst transactions are permitted to configuration registers. Fields suchas Vendor ID, Subvendor ID are included in the configuration space.
5.8.5 Base Address Registers
The TL850C supports three address spaces: memory-mapped I/O, SDRAM, transport input buffer.
5.8.5.1 Memory Mapped I/O
The addressing range of the I/O space is 1 Mbyte.
5.8.5.2 SDRAM
The addressing range of the SDRAM space is 64 Mbytes. Thismemory space can be accessed using big-endian or little-endian byteordering.
5.8.5.3 Transport Input Buffer
The addressing range is 64 Kbytes.
Table 10: Example Memory Configurations
SDRAM Chip
Width (bits)
Width (chips)
# of Banks
Total Memory
1 M x 16 32 2 1 4 Mbytes
512 K x 32 64 2 2 8 Mbytes
2 M x 8 32 4 1 8 Mbytes
1 M x 32 32 1 1 4 Mbytes1
1. AMR down-conversion to 480I.
1 M x 32 32 2 1 8 Mbytes2
2. AMR for HD operation to 480I.
1 M x 32 64 2 1 8 Mbytes
1 M x 32 32 4 1 16 Mbytes
1 M x 16 64 4 2 16 Mbytes
2 M x 32 32 1 1 16 Mbytes
2 M x 32 64 2 1 16 Mbytes
4 M x 16 64 4 2 64 Mbytes
Read Buffer
Write Back/Burst Buffer
Byte/Valid Bits
Write ThroughBuffer
Hint Address Register
To other on-chip register and I/O resources
MIFHIF
From on-chip register resources
To transport input buffer
PCI
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5.8.6 Burst Transfers to the Transport Input Buffer
The TL850C supports burst transfers to the transport input buffer. Thisis usually a recipient of a DMA transfer from another PCI bus master.
The TL850C HIF provides a 64 Kbyte contiguous region of memorymapped space for the Transport stream. Any memory transfer to thisspace is assembled to byte order and written into the MPEG Transportdecoder. There is a maximum bandwidth of 266 Mbytes/sec attainableon the PCI bus; however, the transport input cannot operate above216 Mbytes/sec.
The TL850C HIF directs data written by PCI to the Transport Streamto an eight-DWORD write buffer, which is shared with the SDRAMchannel. If the buffer is unavailable, the HIF causes the PCI to issue aRetry Terminate. If the buffer becomes full as part of a bursttransaction, a Disconnect Terminate is issued. The HIF then sends thedata from the write buffer to the transport interface. Byte enables aresignificant, since the data can have any alignment in memory. Thedata is written in the order it was received in the write buffer.
The HIF write buffer acts as an elastic synchronization buffer betweenthe HIF clock domain and the transport clock domain. It is very
desirable that the write buffer begins to feed the transport as soon asdata is available (i.e., the write buffer is not full). This lets the burstcontinue for more than eight DWORDs, providing there is space inthe transport buffer.
The HIF monitors the write buffer. if the write buffer becomes full, theHIF performs a Disconnect Abort on the PCI bus. The PCI thenattempts a Retry. The HIF issues Retry Aborts until the write buffer isflushed (becomes empty). This prevents thrashing on the PCI bus,since the eight-DWORD write buffer is guaranteed empty at thebeginning of a transfer.
5.8.7 Hinted Reads
The TL850C supports hinted reads. The CPU can write an SDRAMaddress to a register (Hint Register) in the memory mapped I/O space,which causes the HIF read buffer to be filled with data from thatSDRAM location. Hinted reads are used by the application code toprefetch data to the read buffer to improve read latency.
5.8.8 Interrupts
All interrupts are mapped to the INTA pin.
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6. PINOUT (348-Pin BGA)
Table 11 lists the pinout of the TL850C. Note that unused pins aredesignated as N/C (not connected); these should be left unconnectedon the PCB.
Table 11: TL850C Pinout
Signal Name Pin # I/O
ACLK V10 I/O
AD00 Y5 I/O
AD01 Y1 I/O
AD02 Y4 I/O
AD03 Y2 I/O
AD04 W5 I/O
AD05 Y3 I/O
AD06 W4 I/O
AD07 W1 I/O
AD08 W2 I/O
AD09 V4 I/O
AD10 W3 I/O
AD11 V3 I/O
AD12 V1 I/O
AD13 U5 I/O
AD14 V2 I/O
AD15 U4 I/O
AD16 P3 I/O
AD17 P1 I/O
AD18 N4 I/O
AD19 N2 I/O
AD20 N3 I/O
AD21 N1 I/O
AD22 M4 I/O
AD23 M2 I/O
AD24 M3 I/O
AD25 L2 I/O
AD26 L4 I/O
AD27 L1 I/O
AD28 L3 I/O
AD29 K2 I/O
AD30 K4 I/O
AD31 K1 I/O
ADATAI0 W8 Input
ADATAI1 Y8 Input
ADATAI2 Y9 Input
ADATAO0 Y10 Output
ADATAO1 W11 Output
ADATAO2 Y11 Output
AGND D5 Power
AGND D6 Power
AGND D7 Power
AGND E9 Power
AUXO0 B14 Output
AUXO1 C13 Output
AUXO2 A13 Output
AUXO3 B13 Output
AUXO4 C12 Output
AUXO5 A12 Output
AUXO6 B12 Output
AUXO7 C11 Output
AVDD C5 Power
AVDD C6 Power
AVDD C7 Power
AVDD D9 Power
BCLK V9 Input
BLU0 (GPIO) E3 I/O
BLU1 (GPIO) E2 I/O
BLU2 (GPIO) E1 I/O
BLU3 (GPIO) E4 I/O
BLU4 (GPIO) F2 I/O
BLU5 (GPIO) F1 I/O
BLU6 (GPIO) F4 I/O
BLU7 (GPIO) F3 I/O
BLUE/PB B5 Output
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
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BUSCLK T2 Output
C/BE0# V5 I/O
C/BE1# U1 I/O
C/BE2# P2 I/O
C/BE3# M1 I/O
CCLK U13 Input
CDATA0 V11 Input
CDATA1 W12 Input
CDATA2 Y12 Input
CDATA3 V12 Input
CDATA4 W13 Input
CDATA5 Y13 Input
CDATA6 V13 Input
CDATA7 W14 Input
CDVALID T10 I/O
CFRAME U12 Input
CGND E10 Power
CGND E12 Power
CGND E7 Power
CGND F15 Power
CGND G5 Power
CGND J16 Power
CGND K5 Power
CGND L16 Power
CGND N16 Power
CGND P5 Power
CGND T13 Power
CGND T8 Power
CLKIN U9 Input
COMP C8 Input
CPWM U11 Output
CVDD E11 Power
CVDD E13 Power
CVDD E15 Power
CVDD E8 Power
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
CVDD F6 Power
CVDD H16 Power
CVDD J5 Power
CVDD K16 Power
CVDD L5 Power
CVDD M16 Power
CVDD R6 Power
CVDD T11 Power
DDC0 A10 I/O
DDC1 B10 I/O
DEVSEL# R1 I/O
EE_CS H1 Output
EE_DI H3 Input
EE_DO G2 Output
EE_SK G1 Input
FRAME# P4 I/O
GNT# J2 Input
GREEN/Y B6 Output
GRN0 (GPIO) A4 I/O
GRN1 (GPIO) B4 I/O
GRN2 (GPIO) C4 I/O
GRN3 (GPIO) A3 I/O
GRN4 (GPIO) B3 I/O
GRN5 (GPIO) D4 I/O
GRN6 (GPIO) A2 I/O
GRN7 (GPIO) A1 I/O
HCLK J1 Input
HSYNC (GPIO) A11 Output
IDSEL M5 Input
IECOUT W10 Output
IGND E14 Power
IGND F5 Power
IGND G16 Power
IGND H10 Power
IGND H11 Power
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
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IGND H12 Power
IGND H13 Power
IGND H8 Power
IGND H9 Power
IGND J10 Power
IGND J11 Power
IGND J12 Power
IGND J13 Power
IGND J8 Power
IGND J9 Power
IGND K10 Power
IGND K11 Power
IGND K12 Power
IGND K13 Power
IGND K8 Power
IGND K9 Power
IGND L10 Power
IGND L11 Power
IGND L12 Power
IGND L13 Power
IGND L17 Power
IGND L8 Power
IGND L9 Power
IGND M10 Power
IGND M11 Power
IGND M12 Power
IGND M13 Power
IGND M8 Power
IGND M9 Power
IGND N10 Power
IGND N11 Power
IGND N12 Power
IGND N13 Power
IGND N5 Power
IGND N8 Power
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
IGND N9 Power
IGND P16 Power
IGND T12 Power
IGND T5 Power
IGND T7 Power
INTA# H4 Output
INTB# H1 Output
IRDY# R2 I/O
IVDD D15 Power
IVDD E5 Power
IVDD E6 Power
IVDD F14 Power
IVDD F16 Power
IVDD H5 Power
IVDD K17 Power
IVDD P15 Power
IVDD R5 Power
IVDD R7 Power
IVDD R14 Power
IVDD T9 Power
LRCLK W9 Input
OSDP K3 Output
PAR U3 I/O
PCLK U10 Output
PERR# T1 I/O
PGND T14 Power
PIXIN0 U6 Input
PIXIN1 V6 Input
PIXIN2 Y6 Input
PIXIN3 W6 Input
PIXIN4 W7 Input
PIXIN5 Y7 Input
PIXIN6 V7 Input
PIXIN7 U7 Input
PLL_BP H2 Input
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
July 2000 Rev. 3.0 TERALOGIC CONFIDENTIAL - DO NOT COPY 27
This material is confidential and is provided under an existing NDA
PVDD U14 Power
RED/PR B7 Output
RED0 (GPIO) B2 I/O
RED1 (GPIO) B1 I/O
RED2 (GPIO) C3 I/O
RED3 (GPIO) C2 I/O
RED4 (GPIO) C1 I/O
RED5 (GPIO) D3 I/O
RED6 (GPIO) D2 I/O
RED7 (GPIO) D1 I/O
REQ# J3 Output
RSET B8 Input
RST# J4 Input
SADR00 M20 Output
SADR01 M19 Output
SADR02 L20 Output
SADR03 L19 Output
SADR04 K19 Output
SADR05 K20 Output
SADR06 J19 Output
SADR07 J20 Output
SADR08 J18 Output
SADR09 H19 Output
SADR10 M18 Output
SADR11 H20 Output
SADR12 N19 Output
SADR13 N20 Output
SCAS# N17 Output
SCLKI L18 Input
SCLKO0 E16 Output
SCLKO1 T16 Output
SCLKO2 K18 Output
SCS0# G17 Output
SCS1# H17 Output
SDATA00 A14 I/O
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
SDATA01 C14 I/O
SDATA02 B15 I/O
SDATA03 A15 I/O
SDATA04 C15 I/O
SDATA05 B16 I/O
SDATA06 A16 I/O
SDATA07 C16 I/O
SDATA08 B17 I/O
SDATA09 C17 I/O
SDATA10 A18 I/O
SDATA11 B18 I/O
SDATA12 C18 I/O
SDATA13 A19 I/O
SDATA14 B19 I/O
SDATA15 A20 I/O
SDATA16 B20 I/O
SDATA17 D17 I/O
SDATA18 C19 I/O
SDATA19 C20 I/O
SDATA20 D18 I/O
SDATA21 D19 I/O
SDATA22 D20 I/O
SDATA23 E17 I/O
SDATA24 E19 I/O
SDATA25 F18 I/O
SDATA26 F20 I/O
SDATA27 F19 I/O
SDATA28 G18 I/O
SDATA29 G20 I/O
SDATA30 G19 I/O
SDATA31 H18 I/O
SDATA32 N18 I/O
SDATA33 P19 I/O
SDATA34 P20 I/O
SDATA35 P18 I/O
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
TERALOGIC CONFIDENTIAL - DO NOT COPY July 2000 Rev. 3.0 28
This material is confidential and is provided under an existing NDA
SDATA36 R19 I/O
SDATA37 R20 I/O
SDATA38 R18 I/O
SDATA39 T19 I/O
SDATA40 T17 I/O
SDATA41 U20 I/O
SDATA42 U19 I/O
SDATA43 U18 I/O
SDATA44 V20 I/O
SDATA45 V19 I/O
SDATA46 U17 I/O
SDATA47 W20 I/O
SDATA48 Y20 I/O
SDATA49 W19 I/O
SDATA50 Y19 I/O
SDATA51 V18 I/O
SDATA52 W18 I/O
SDATA53 Y18 I/O
SDATA54 V17 I/O
SDATA55 W17 I/O
SDATA56 V16 I/O
SDATA57 Y16 I/O
SDATA58 W16 I/O
SDATA59 V15 I/O
SDATA60 Y15 I/O
SDATA61 W15 I/O
SDATA62 V14 I/O
SDATA63 Y14 I/O
SDQM0 D16 Output
SDQM1 A17 Output
SDQM2 E18 Output
SDQM3 E20 Output
SDQM4 T20 Output
SDQM5 T18 Output
SDQM6 Y17 Output
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
SDQM7 U16 Output
SERR# U2 I/O
SGND R15 Power
SRAS# P17 Output
STOP# R4 I/O
SVDD R16 Power
SWE# R17 Output
TCLK G1 Input
TDI H3 Input
TDO G2 Output
TMS G4 Input
TRDY# R3 I/O
TRST G3 Input
VCLKI U8 Input
VCLKO D11 Output
VGND T15 Power
VREFIN C9 Input
VREFOUT B9 Output
VSYNC (GPIO) B11 Output
VVDD U15 Power
VVLD (GPIO) V8 Input
Table 11: TL850C Pinout (Cont.)
Signal Name Pin # I/O
July 2000 Rev. 3.0 TERALOGIC CONFIDENTIAL - DO NOT COPY 29
This material is confidential and is provided under an existing NDA
Figure 25 TL850C Top View Package Drawing
A
BC
DE
FG
HJ
KL
MN
PR
TU
VW
Y
A
BC
DE
FG
HJ
KL
MN
PR
TU
VW
Y
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SD
ATA
15
SD
ATA
13
SD
ATA
10
SD
ATA
16
SD
ATA
14
SD
ATA
11
SD
ATA
08
SD
ATA
19
SD
ATA
18
SD
ATA
12
SD
ATA
09
SD
ATA
06S
DA
TA05
SD
ATA
07
SD
ATA
03S
DA
TA02
SD
ATA
04
SD
ATA
00S
DA
TA01
SD
ATA
22
SD
ATA
21
SD
ATA
20
SD
ATA
17
SD
ATA
26
SD
ATA
27
SD
ATA
25
SD
ATA
24
SD
ATA
23
SD
ATA
29
SD
ATA
30
SD
ATA
28S
DA
TA31
SD
QM
1
SD
QM
3
SD
QM
2
SD
QM
0
NC
SC
LKO
0
NC
IVD
D
AU
XO
0
CV
DD
CG
ND
IVD
D
IGN
DIV
DD
CV
DD
CV
DD
SC
S0#
SC
S1#
CV
DD
CV
DD
IGN
D
CG
ND
AU
XO
3A
UX
O1
AU
XO
6A
UX
O4
AU
XO
2
AU
XO
5
NC
NC
AU
XO
7H
SY
NC
VS
YN
CV
CLK
O
CG
ND
CG
ND
CV
DD
CG
ND
SA
DR
11
SA
DR
09
SA
DR
07
SA
DR
06
SA
DR
08
NC
IVD
D
SA
DR
05
SA
DR
04
SC
LKO
2
SA
DR
02
SA
DR
03
SC
LKI
IGN
D
SA
DR
00
SA
DR
01
SA
DR
10
NC
SA
DR
13
SA
DR
12
SD
ATA
32
SC
AS
#
SD
ATA
34
SD
ATA
33
SD
ATA
35
SR
AS
#
IGN
D
IVD
D
SV
DD
SG
ND
SD
ATA
37
SD
ATA
36
SD
ATA
38
SW
E#
SC
LKO
1
VG
ND
SD
QM
4
SD
ATA
39
SD
QM
5
SD
ATA
40
SD
QM
7
VV
DD
SD
ATA
41
SD
ATA
42
SD
ATA
43
SD
ATA
46
SD
ATA
56
SD
ATA
59
SD
ATA
44
SD
ATA
45
SD
ATA
51
SD
ATA
54
SD
ATA
62P
GN
DP
VD
D
SD
ATA
58
SD
ATA
61
SD
ATA
47
SD
ATA
49
SD
ATA
52
SD
ATA
55
CD
ATA
7
SD
ATA
57
SD
ATA
60
SD
ATA
48
SD
ATA
50
SD
ATA
53
SD
QM
6
SD
ATA
63
CD
ATA
6C
GN
DC
CLK
CD
ATA
4C
DA
TA5
CD
ATA
3IG
ND
CF
RA
ME
CD
ATA
1C
DA
TA2
CD
ATA
0C
VD
DC
PW
MA
DA
TAO
1A
DA
TAO
2
AC
LKC
DV
ALI
DP
CLK
IEC
OU
TA
DA
TAO
0
IGN
D
IVD
D
CG
ND
PIX
IN7
CLK
IN
VC
LKI
PIX
IN6
BC
LK
VV
LD
PIX
IN4
LRC
LK
AD
ATA
I0
PIX
IN5
AD
ATA
I2
AD
ATA
I1
IVD
DIG
ND
PIX
IN0
PIX
IN1
PIX
IN3
PIX
IN2
CV
DD
NC
AD
13C
/BE
0#A
D04
AD
00IV
DD
IGN
D
AD
15A
D09
AD
06A
D02
ST
OP
#N
C
PA
RA
D11
AD
10A
D05
TR
DY
#N
C
SE
RR
#A
D14
AD
08A
D03
IRD
Y#
BU
SC
LK
C/B
E1#
AD
12A
D07
AD
01D
EV
SE
L#P
ER
R#
AD
09
CV
DD
CV
DD
IVD
DC
GN
DID
SE
LIG
ND
CG
ND
BLU
E/P
BA
GN
DA
VD
DIV
DD
IGN
DC
GN
D
GR
EE
N/Y
AG
ND
NC
AV
DD
IVD
DC
VD
D
RE
D/P
RA
GN
DN
CA
VD
DC
GN
D
RS
ET
NC
CO
MP
CV
DD
VR
EF
OU
TA
VD
DV
RE
FIN
AG
ND
DD
C1
NC
DD
C0
NC
CG
ND
RS
T#
AD
26IN
TA#
AD
30A
D22
AD
18F
RA
ME
#G
RN
1G
RN
5G
RN
0G
RN
2B
LU3
BLU
6T
MS
RE
Q#
AD
28T
DI/
OS
DP
AD
24A
D20
AD
16G
RN
4R
ED
5G
RN
3R
ED
2B
LU0
BLU
7T
RS
T
GN
T#
AD
25P
LL_B
PA
D29
AD
23A
D19
C/B
E2#
RE
D0
RE
D6
GR
N6
RE
D3
BLU
1B
LU4
TD
O/
HC
LKA
D27
EE
_CS
/A
D31
C/B
E3#
AD
21A
D17
RE
D1
RE
D7
GR
N7
RE
D4
BLU
2B
LU5
TC
LK/
IGN
DIG
ND
IGN
DIG
ND
IGN
DIG
ND
IGN
DIG
ND
IGN
DIG
ND
IGN
DIG
ND
IGN
DIG
ND
IGN
DIG
ND
NC
NC
IVD
D
IGN
D
IGN
D
IGN
D
IGN
D
IGN
D
IGN
DIG
ND
IGN
DIG
ND
IGN
D
IGN
D
IGN
D
IGN
D
IGN
D
IGN
DIG
ND
IGN
DIG
ND
IGN
DIG
ND
TL
850C
EE
_DI
EE
_DO
NC
EE
_SK
INT
B#
NC
NC
NC
NC
TERALOGIC CONFIDENTIAL - DO NOT COPY July 2000 Rev. 3.0 30
This material is confidential and is provided under an existing NDA
7. PROTOCOL DIAGRAMS
This section provides functional and timing diagrams that illustratethe following TL850C operations: audio, PCI bus, SDRAM, video,and DPC.
7.1 Audio Data Input/Output
Figure 26 shows the waveforms for audio I/O.
Figure 26 Audio Input/Output Formats
7.2 PCI Bus Timing
Figure 27 shows a PCI configuration read. Figure 28 shows a basicwrite operation. Figure 29 shows a basic read operation.
Figure 27 PCI Configuration Read
Figure 28 Basic PCI Write Operation
MSB LSB
MSB LSB
LSBMSB
MSB LSB
MSB LSB
MSBMSB
Left Sample Right Sample
BCLK
BCLK
LRCLK
ADATAI/O
ADATAI/O
BCLK
BCLK
LRCLK
ADATAI/O
I2S
PCM(Right justified)
(rising)
(falling)
(rising)
(falling)
PCM(Left justified)
ADDRESS
CLK
FRAME#
AD
IDSEL
C/BE#
IRDY#
TRDY#
DEVSEL#
DATA
BE#’sCFG-RD
(HCLK) ADDRESS
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
DATA-1 DATA-2 DATA-3
BE#'s-1 BE#'s-1BUS CMD BE#'s
DAT
A TR
ANSF
ER
WAI
T
DAT
A TR
ANSF
ER
WAI
T
WAI
T
DAT
A TR
ANSF
ER
AddressPhase
DataPhase
Bus Transaction
DataPhase
DataPhase
(HCLK)
July 2000 Rev. 3.0 TERALOGIC CONFIDENTIAL - DO NOT COPY 31
This material is confidential and is provided under an existing NDA
Figure 29 Basic PCI Read Operation
7.3 SDRAM Timing Parameters
Table 12 summarizes the timing parameters assumed by the MIFdesigns. For the parameters marked as “minimum,” the SDRAM canalso be faster (have smaller cycle counts). If the parameter is notmarked as “minimum,” then the SDRAM must have exactly thisdelay.
Note: A key requirement (not supported by all SDRAM/SGRAMs) is the ability to do a full-page, sequential burstsequence. The SDRAM/SGRAMs used must also supportthe burst stop command.
Figure 30 Basic SDRAM Read Timing
Figure 31 Basic SDRAM Write Timing
Figure 32 RAS-to-RAS Delay Time
Figure 33 Termination of a Burst Read Operation
Table 12: SDRAM Timing Parameters (CAS Latency = 3)
Timing Parameter
Delay Description#
CyclesMinimum
TRP PREA to RASA 3 Y
TRCD RASA to CASA 3 Y
TRAS RASA to PREA 7 Y
TRC RASA to RASA 10 Y
TRRD RASA to RASB 3 Y
TWL CASA to Data-InA 0
TCCD CASA to CASB 1
TEP Last Data-OutA to PREA −1 Y
TDP Last Data-InA to PREA 2 Y
TMODE Mode cmd to any cmd 2 Y
TDQW DQM to Data-In Mask 0
TDQZ DQM to Data-out Disable 2
ADDRESS
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
DATA-1 DATA-2 DATA-3
BUS CMD BE#'s
WAI
T
DAT
A TR
ANSF
ER
WAI
T
DAT
A TR
ANSF
ER
WAI
T
DAT
A TR
ANSF
ER
AddressPhase
DataPhase
Bus Transaction
DataPhase
DataPhase
(HCLK)
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Bank ReadA0A
Activate
ReadA1
ReadA2
ReadB0
Precharge A
BankA
Activate
DoutA0
DoutA1
DoutA2
DoutB0
DoutB1
TRC = 10 cycles
TRAS = 7 cycles TRP = 3 cycles
TRCD = 3 cycles TCCD= 1 cycle
TEP= −1 cycle
CAS latency= 3 cycles
COMMAND
DQ
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Bank WriteA0A
Activate
WriteA1
WriteA2
WriteB0
Precharge A
BankA
Activate
DinA0
DinA1
DinA2
DinB0
DinB1
TRC = 10 cycles
TRAS =7 cycles TRP= 3 cycles
TRCD = 3 cycles
TCCD = 1 cycle
TDP = 2 cycles
COMMAND
DQDinB2
DinB3
DinB4
TWL = 0 cycle
CLK
Tn Tn + 1 Tn + 2 Tn + 4
Address
Command
Bank B
Row Address
Bank A
Row Address
Bank B
Activate
Bank A
Activate
NOP NOP
TRRD = 3 cycles
Tn + 3
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
TCK3, DQs
ReadA
NOPBurst
NOPNOP Stop NOPNOPNOP NOP
DoutA0
DoutA1
DoutA2
DoutA3
The Burst ends after a delay equal to the CAS latency.
TERALOGIC CONFIDENTIAL - DO NOT COPY July 2000 Rev. 3.0 32
This material is confidential and is provided under an existing NDA
Figure 34 Termination of a Burst Write Operation
Figure 35 Mode Register Set
Figure 36 Data Mask During Read
Figure 37 Data Mask During Write
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
DQs
NOPBurst
NOP Stop NOPNOPNOP NOP
DinA0
DinA1
AWriteNOP
Input data for the Write is masked.
DinA2
don’tcare
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND Mode
Precharge All Banks
AnyCommand
TRP = 3 Cycles TMODE = 2 Cycles
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMANDRead
A
DoutA0
DoutA1
DoutA4
DoutA5
DQM
DQ
TDQZ = 2 Cycles
CLK
T0 T1 T2 T3 T4 T5
COMMANDWrite
A
DinA0
DinA1
DQM
DQ
TDQW = 0 Cycles
DinA4
DinA5
Data-in is masked while DQM is asserted.
July 2000 Rev. 3.0 TERALOGIC CONFIDENTIAL - DO NOT COPY 33
This material is confidential and is provided under an existing NDA
7.4 Primary Video Out (Analog)
This section shows the horizontal and vertical waveforms for theanalog primary video out.
Figure 38 Horizontal Timing
Vertical Sync
+300
0
-300
Blanking
Broad pulsed
hg
OH
c
ea
bO
H
P'B, P'R
+300+350
-350
0
-300
Y', R' G' B'
+300
+700
0
-300
TERALOGIC CONFIDENTIAL - DO NOT COPY July 2000 Rev. 3.0 34
This material is confidential and is provided under an existing NDA
Figure 39 shows the analog vertical timing for the primary video out.
Figure 39 Vertical Timing (Analog)
bottom
Topline offrame
Bottomline offrame
1121 1122... 1125 1 2 3 4 5 6 7 8 ... 41 42 43 ... 1121 1122 ... 1125 Line #
PROGRESSIVE SYSTEM, FRAME
INTERLACED SYSTEM, FIRST FIELD
INTERLACED SYSTEM, SECOND FIELD
45H
41H
5H
bottom
Topline offrame
1123 1124 1125 1 2 3 4 5 6 7 8 ... 20 21 22 ... 560 561 562 Line #
22H
20H
5H
bottom
Bottomline offrame
560 561 562 563 564 565 566 567 568 569 570 ... 582 583 584 585 ... 1123 1124 1125 Line #
23H
20 1/2H
5H6H
QV
July 2000 Rev. 3.0 TERALOGIC CONFIDENTIAL - DO NOT COPY 35
This material is confidential and is provided under an existing NDA
7.5 Primary Video Out (Digital)
Figure 40 shows the digital vertical timing for the primary video out.
Figure 40 Vertical Timing (Digital)
F V
H
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 0
EA
V
0 0
SA
V
0 0
EA
V
0 0
SA
V
0 0
EA
V
0 0
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
F V
H
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 0
EA
V
0 0
SA
V
0 0
EA
V
0 0
SA
V
0 0
EA
V
0 0
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
Line # 1121 1122 ... 1125 1 2 3 4 5 6 7 8 ... 41 42 43 ... 1121 1122 ... 1125
560 561 562
bottom
PROGRESSIVE SYSTEM, FRAME
Line # 1123 1124 1125 1 2 3 4 5 6 7 8 ... 20 21 22 ...
INTERLACED SYSTEM, FIRST FIELD
1123 1124 1125
F V
H
0 0
SA
V
0 1
EA
V
0 1
SA
V
0 1
EA
V
0 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
1 0
EA
V
1 0
SA
V
1 0
EA
V
1 0
SA
V
1 0
EA
V
1 0
SA
V
1 1
EA
V
1 1
SA
V
1 1
EA
V
1 1
SA
V
0 1
EA
V
Line # 560 561 562 563 564 565 566 567 568 569 570 ... 582 583 584 585 ...
INTERLACED SYSTEM, SECOND FIELD
TERALOGIC CONFIDENTIAL - DO NOT COPY July 2000 Rev. 3.0 36
This material is confidential and is provided under an existing NDA
7.6 DPC
Figure 41 shows the horizontal blanking structure for ITU-R 601.
Figure 41 ITU-R 601 Horizontal Blanking Structure
Digital Blanking
(a) Horizontal Sync Relationship (NTSC)
16T 720T122T
Digital Active Line
0 1857
736
720
719
Last Sample first Sample
Cb
360
Y 7
20
Cr
360
Y72
1
Y 7
19
Cb
428
Y 8
56
Cr
428
Y 8
57
Y85
5
Cb
0
Y 0
Cr
0
Y 1
Replaced by TimingReference Signal SAV
Replaced by TimingReference Signal EAV
(b) Multiplex structure (ITU-R 601 525/60)
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8. TIMING DIAGRAMS
Table 13 lists preliminary AC timing for the TL850C. All units are innanoseconds, unless specified otherwise. The characterization valuesfor each parameter will be provided in a future release of thisdatasheet. The numbers in Figure 43 through Figure 58 correspond to
the numbers listed in column 1 of Table 13. With the exception ofSDRAM timing, all loading is 50 pF. Note that all I/O timing isrelative to the rising edge of the clock pin for that group; for example,all PCI pins are relative to rising edge of HCLK.
Table 13: AC Specifications (TO BE CHARACTERIZED)
Figure Group Parameter Signal(s) I/O Type Min Max Load Notes
42 Coded Data In 1a,2a,3a CCLK I Tcyc 37 2
43 (CCLK) 4 CDATA, CFRAME, CDVALID
I Tsu 3
43 5 CDATA, CFRAME, CDVALID
I Th 2.5
42, 44 Audio 1b,2b,3b BCLK I/O Tcyc 80 50 2, 5
45 (BCLK-output) 6a ADATAI I Tsu 10
45 7a ADATAI I Th 10
45, 47 8a ADATAO, IEC958O, LRCLK O Tval 4 15 50
44, 46 (BCLK-input) 6b ADATAI, LRCLK I Tsu 10
44, 46 7b ADATAI, LRCLK I Th 10
46 8b ADATAO, IEC958O O Tval 4 15 50
45, 42 1c,2c,3c ACLK I Tcyc 20
48, 42 Video In 1d,2d,3d VCLKI I Tcyc 18.5 37 2
48 (VCLKI) 9 PIXIN,VVLD I Tsu 6.5
48 10 PIXIN,VVLD I Th 0
42 Aux Video 1e,2e,3e VCLKO O Tcyc 37 37 50 2
49 (VCLKO) 11 AUXO O Tval 2 4 50
42 Video Out 1f,2f,3f PCLK -output I/O Tcyc 9.3 37 50 2
50 - 52 (PCLK -output) 12a PIXOUT O Tval 3 6 50
50 13a BLUE, GREEN, RED Analog O Tval 0 2 4
50 14a HSYNC,VSYNC O Tval 3 5 50
50 - 52 (PCLK -input) 12b PIXOUT O Tval 8 14.5 50
50 13b BLUE,GREEN,RED Analog O Tval 2 9 4
50 15b HSYNC,VSYNC I Tsu 8
50 16b HSYNC,VSYNC I Th 8
42 PCI master 1g,2g,3g HCLK I Tcyc 15 30 2, 7
53 (HCLK) 17 AD, C/BE, PAR O Tval 2 7.5 50 1
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53 18 FRAME, IRDY I/O Tval 2 8 50
54 19 TRDY, STOP, DEVSEL, SERR
I Tsu 3
54 19 PERR I/O Tsu 3
54 20 TRDY, STOP,DEVSEL,SERR
I Th 0
54 20 PERR I/O Th 0
54 21 AD, PAR I Tsu 3
54 22 AD, C/BE, PAR I Th 0
53 23 REQ O Tval 2 7.5 50
54 24 GNT I Tsu 5
54 25 GNT I Th 0
53 PCI Slave 17 AD, PAR O Tval 2 7.5 50 1
53 (HCLK) 26 INTA,PERR,SERR O Tval 2 9 50
53 27 TRDY, STOP,DEVSEL O Tval 2 9 50
54 21 AD, PAR I Tsu 3
54 22 AD, C/BE, PAR I Th 0
54 28 FRAME, IRDY I Tsu 3
54 29 FRAME, IRDY I Th 0
54 30 RST I Tsu 3
54 31 RST I Th 0
54 32 IDSEL I Tsu 5
54 33 IDSEL I Th 0
42, 58 NVRAM 1h,2h,3h EE_SK O Tcyc 60 50 2
58 (EE_SK) 34 EE_DO I Tsu 3
58 35 EE_DO I Th 2
58 36 EE_DI, EE_CS O Tval 2 14 50
59 - 65 36a EE_CS O Tcs 1 µs 50
62 - 65 36b EE_CS, EE_DO O Twp 15 ms 50
42, 66 SDRAM 1i,2i,3i SCLKO O Tcyc 7 12.5 2
66 (SCLKO) 37 SADR O Tval 4 4.5 70 3
66 38 SRAS,SCAS,SCS,SWE O Tval 3.5 5.5 70 3
Table 13: AC Specifications (TO BE CHARACTERIZED) (Cont.)
Figure Group Parameter Signal(s) I/O Type Min Max Load Notes
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Notes:1. All 3-state outputs should assume an active to float time Toff of 8ns.2. All clocks are 40% minimum duty cycle and 60% maximum duty cycle.3. Allows for external series termination delay.4. Referenced to the falling edge of the clock.5. BCLK can be 32fs, 64fs, 128fs, or 256fs, where fs can be 32 KHz, 44.1KHz, or 48KHz. 6. GPIO input and output is asynchronous and is synchronized with the internal device clock.7. Minimum times for Figures 53-54 are measured at the package pin with the load circuit shown in Figure 57. Maximum times are measured with the load circuit shown in
Figures 55-56.8. HSYNC and VSYNC are asynchronous signals that are internally synchronized.
8.1 Clock Timings
Figure 42 shows the timing parameters for all clocks.
Figure 42 Clock Waveform For All Clocks
8.2 Transport Data Input
Figure 43 shows the input timing waveforms for the transport data.
Figure 43 Transport Input Timing
8.3 Audio Data Input
This section shows the waveforms for the audio input port for bothslave mode and master mode.
Figure 44 Audio Input Port (Slave Mode)
66 39 SDATA, SDQM O Tval 3.5 5.5 35 1
66 40 SDATA I Tsu 0.5
66 41 SDATA I Th 3
42, 49 1j,2j,3j CLKIN I Tcyc 37 37 50 2
Table 13: AC Specifications (TO BE CHARACTERIZED) (Cont.)
Figure Group Parameter Signal(s) I/O Type Min Max Load Notes
3.3 Volt Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
1a ... 1j
2a ... 2j3a ... 3j0.6 Vcc
0.2 Vcc
0.4 Vcc,p-to-p(min.)
(1a ... 1j) means 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j(2a ... 2j) means 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j(3a ... 3j) means 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 3i, 3j
XXX ValidData
ValidData
ValidData
ValidData
ValidData
4 5
CCLK
CDVALID
CDATA[7:0]
CFRAME
BCLK
ADATAI[2:0]
LRCLK
1b
(Input)
(Input)
(Input)
6b 7b
7b6b
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Figure 45 Audio Input Port (Master Mode)
8.4 Audio Data Out
This section shows the waveforms for the audio output port in bothslave mode and master mode.
Figure 46 Audio Output Port (Slave Mode)
Figure 47 Audio Output Port (Master Mode)
8.5 CCIR656/601
Figure 48 shows the waveforms for the digital video data inputs.
ACLK
ADATAI[2:0]
LRCLK
(Input)
(Output)
(Input)
BCLK(Output)
8a
6a7a
1c
BCLK
ADATAO[2:0]
LRCLK
(Input)
(Input)
(Output)
6b 7b
8b
ADATAO[2:0]
LRCLK(Output)
(Output)
BCLK(Output)
8a
8a
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Figure 48 Digital Video Data Input
8.6 AUX Video Out
Figure 49 shows the waveforms for the AUX video outputs.
Figure 49 AUX Video Out Timing
1 0
9
1 d3 d2 d
V C L K I
P IX IN [7 :0 ]
11
CLKIN
VCLKO
AUXO[7:0] 0 1 0
3j2j1j
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8.7 Primary Video Out (Digital)
This section shows the waveforms for primary video out: 24-bit RGB/YPbPr, 16-bit YPbPr, and 8-bit YPbPr.
Figure 50 Primary Video Out (24-bit RGB/YPbPr)
Figure 51 Primary Video Out (16-bit YPbPr)
PCLK(I/O)
VBLANK (in)
HBLANK (in)
(VSYNC)
(HSYNC)
PIXOUT[7:0](RED[7:0])
PIXOUT[15:8](GREEN[7:0])
PIXOUT[23:16](BLUE[7:0]) PIX0
PIX0
PIX0
PIX1
PIX1
PIX1
PIX2
PIX2
PIX2
PIX3
PIX3
PIX3
--------
--------
--------
(Pr[7:0])
(Y[7:0])
(Pb[7:0])
BlankBlank
Blank Blank
Blank Blank
12a, 12b
Analog RGB PIX0 PIX1 PIX2 PIX3 --------Blank Blank
13a, 13b
16a, 16b15a, 15b
Blank
14a, 14b
PCLK(I/O)
VBLANK
HBLANK
(VSYNC)
(HSYNC)
PIXOUT[15:8](Y[7:0])
PIXOUT[7:0](Pb/Pr[7:0]) Pb0
Y0
Pr0
Y1
Pb1
Y2
Pr1
Y3
--------
--------0x100x10
0x80 0x80
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Figure 52 Primary Video Out (8-bit YPbPr)
8.8 PCI Bus
This section shows the timing waveforms related to the PCI bus. Theminimum times for Figure 53 and Figure 54 are measured at thepackage pin with the load circuit shown in Figure 57. The maximumtimes are measured with the load circuit shown in Figure 55 andFigure 56.
Figure 53 PCI Bus Output Timing
Figure 54 PCI Bus Input Timing
Figure 55 Tval (max) Rising Edge
Figure 56 Tval (max) Falling Edge
Figure 57 Tval (min) and Slew Rate
8.9 NVRAM
Figures 58 through 65 show the timing waveforms for the NVRAMinterface.
Figure 58 NVRAM Timing
PCLK(I/O)
VBLANK
HBLANK
(VSYNC)
(HSYNC)
PIXOUT[15:8](YPbPr[7:0]) Pb0 Y0 Pr0 Y1 --------0x100x80
17, 18, 23, 26, 27
output current ≤ leakage current
TBDTBD
HCLK
OutputDelay
3-stateOutput
HCLK
Input
19, 21, 24,
V_maxInputs Valid
20, 22, 25,28, 30, 32 29, 31, 33
OutputBuffer
Pin
1/2in.max.
25ohm10pF
Pin
1/2in.max.
25ohm10pFVcc
OutputBuffer
Pin
1/2in.max.
1Kohm10pF
Vcc1Kohm
36
EE_SK
3h2h1h
3534
EE_DO
EE_DI,EE_CS
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Figure 59 Read Waveforms
Figure 60 Erase/Write Enable (EWEN)
Figure 61 Erase/Write Disable (EWDS)
36aEE_CS
EE_SK
EE_DI
EE_DO
0 AN A0
DN D0
1 1
0
...
...3-state
36aEE_CS
EE_SK
EE_DI 0 X1 ... X0
EE_DO = 3-state
ORG = VCC, 4 X’sORG = VSS, 5 X’x
1 1
36aEE_CS
EE_SK
EE_DI 0 X1 ... X0 0 0
DO = 3-state
ORG = VCC, 4 X’sORG = VSS, 5 X’x
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Figure 62 Erase
Figure 63 Write
Figure 64 Erase All (ERAL)
EE_CS
1
Busy
EE_SK
EE_DI
EE_DO
1 1
Ready3-state
Standby36a
36b
A0
3-state
A6/A5 ...
EE_CS
1
Busy
EE_SK
EE_DI
EE_DO
0 1
Ready
36a
36b
A0A6/A5
D15
or D7 ......
3-state 3-state
EE_SK
Busy
EE_CS
EE_DI
EE_DO Ready
36a
36b
Standby
Ready status signal resets to3-state after clocking in one EE_SKCycle with EE_DI = HIGH
... XX01001
ORG = VCC, 4 X’sORG = VSS, 5 X’s3-state 3-state
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Figure 65 Write All (WRAL)
8.10 TL850C to SDRAM Interface
Figure 66 shows the timing waveforms for the SDRAM interface. Theinterface between the SDRAM and the TL850C is a high-speed busthat requires a tightly controlled layout. The capacitance of both thememory components and the printed circuit board significantly affectsthe propagation delays for the SDRAM signals. To more accuratelymodel the SDRAM timing, contact TeraLogic, Inc.
The propagation delay across the circuit board is partiallycompensated by routing SCLKO to the SDRAM and returning it tothe TL850C as SCLKI. For this compensation to be effective, it isimportant that the signal flow for the address, data, and clock to beunidirectional.
Figure 66 SDRAM Interface
EE_SK
Busy
EE_CS
EE_DI
EE_DO Ready
36a
36b
Standby
Ready status signal resets to3-State after clocking in one EE_SKcycle with EE_DI = HIGH
... D0X1001
ORG = VCC, 4 X’sORG = VSS, 5 X’s
0 X DN ...
3-state
38
38
38
38
39
37
3939
1i
SCLKO[2:0]
SDATA[63:0] (output)
SADR[13:0]
SDQM[7:0]
SCS[1:0]
SRAS
SCAS
SWE
SDATA[63:0] (input)
40 41
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9. ABSOLUTE MAXIMUM RATINGS
Table 14: Absolute Maximum Ratings
Symbol Parameter Limits Unit
TA Maximum Case Temperature 0 to +80 °C
TSTG Storage Temperature −55 to +125 °C
VIN, VOUT Voltage on Any Pin Relative to VSS −0.5 to +4.6 V
VDD Voltage on VDD Relative to VSS −1.0 to +4.6 V
IOS Short Circuit Output Current 50 mA
PD Power Dissipation 3.5 W
TSOLDER Soldering Temperature x Time 260 x 10 °C x sec
Table 15: Recommended DC Operating Conditions
Symbol Parameter Min. Typ. Max. Unit Tolerance
IVDD Power Supply Voltage 3.0 3.3 3.6 V ± 5%
PVDD 2.5 V ± 5%
SVDD 2.5 V ± 5%
VVDD 2.5 V ± 5%
AVDD 2.5 V ± 5%
CVDD 2.5 V ± 5%
VIH Input High Voltage 2.0 – IVDD + 0.3 V –
VIL Input Low Voltage −0.5 – 0.8 V –
IIN Input Leakage Current +/-10 µA –
VOHDC Output Logic 1 Voltage 2.4 V –
VOLDC Output Logic 0 Voltage 0.5 V –
CIN Input Capacitance 5 –
COUT Output Capacitance 5 –
VIHCLK 2.5 –
VILCLK 1 –
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Table 16: Recommended AC Operating Conditions1
Parameter Symbol Value
AC Input High/Low Level Voltage VIH/VIL 2.4 V/0.4 V
Input Timing Measurement Reference Level Voltage VTRIP 1.4 V
Input Rise/Fall Time tr/tf 2
Output Reference Voltage Voutref 1.4 V
Output Load Capacitance for Access Time Measurement2 CL
1. TA = 0 °C to 70 °C, VDD = 3.3V ± 10%, VSS = 0 V, unless otherwise noted.2. Output load to measure access times (tOVC, tOH, etc.) varies to clock frequency. A load is equivalent to two TTL gates
and one capacitance. For the specification, the values used are as follows: CL = 10 pF, for 100 MHz ~ 125 MHz of fCLK; CL = 30 pF, for 80 MHz ~ 100 MHz of f CLK; CL = 50 pF, for below 80 MHz of f CLK.
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10. PACKAGING (348-Pin BGA)
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