Tiva C Series TM4C129XNCZAD Microcontroller Data Sheet (Rev. B)

Tiva TM4C129XNCZAD Microcontroller

DATA SHEET

Copyr ight 2007-2014Texas Instruments Incorporated

DS-TM4C129XNCZAD-15863.2743SPMS444B

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb areregistered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

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June 18, 20142Texas Instruments-Production Data
http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 53About This Document .................................................................................................................... 56Audience .............................................................................................................................................. 56About This Manual ................................................................................................................................ 56Related Documents ............................................................................................................................... 56Documentation Conventions .................................................................................................................. 57

1 Architectural Overview .......................................................................................... 591.1 Tiva C Series Overview .............................................................................................. 591.2 TM4C129XNCZAD Microcontroller Overview .................................................................. 601.3 TM4C129XNCZAD Microcontroller Features ................................................................... 631.3.1 ARM Cortex-M4F Processor Core .................................................................................. 631.3.2 On-Chip Memory ........................................................................................................... 651.3.3 External Peripheral Interface ......................................................................................... 671.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 691.3.5 Advanced Encryption Standard (AES) Accelerator .......................................................... 691.3.6 Data Encryption Standard (DES) Accelerator ................................................................. 701.3.7 Secure Hash Algorithm / Message Digest Algorithm (SHA/MD5) ..................................... 701.3.8 Serial Communications Peripherals ................................................................................ 711.3.9 System Integration ........................................................................................................ 771.3.10 Advanced Motion Control ............................................................................................... 851.3.11 Analog .......................................................................................................................... 871.3.12 JTAG and ARM Serial Wire Debug ................................................................................ 881.3.13 Packaging and Temperature .......................................................................................... 891.4 TM4C129XNCZAD Microcontroller Hardware Details ...................................................... 891.5 Kits .............................................................................................................................. 891.6 Support Information ....................................................................................................... 90

2 The Cortex-M4F Processor ................................................................................... 912.1 Block Diagram .............................................................................................................. 922.2 Overview ...................................................................................................................... 932.2.1 System-Level Interface .................................................................................................. 932.2.2 Integrated Configurable Debug ...................................................................................... 932.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 942.2.4 Cortex-M4F System Component Details ......................................................................... 942.3 Programming Model ...................................................................................................... 952.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 952.3.2 Stacks .......................................................................................................................... 962.3.3 Register Map ................................................................................................................ 962.3.4 Register Descriptions .................................................................................................... 982.3.5 Exceptions and Interrupts ............................................................................................ 1142.3.6 Data Types ................................................................................................................. 1142.4 Memory Model ............................................................................................................ 1142.4.1 Memory Regions, Types and Attributes ......................................................................... 1182.4.2 Memory System Ordering of Memory Accesses ............................................................ 1182.4.3 Behavior of Memory Accesses ..................................................................................... 1182.4.4 Software Ordering of Memory Accesses ....................................................................... 119

3June 18, 2014Texas Instruments-Production Data


2.4.5 Bit-Banding ................................................................................................................. 1202.4.6 Data Storage .............................................................................................................. 1222.4.7 Synchronization Primitives ........................................................................................... 1232.5 Exception Model ......................................................................................................... 1242.5.1 Exception States ......................................................................................................... 1252.5.2 Exception Types .......................................................................................................... 1252.5.3 Exception Handlers ..................................................................................................... 1302.5.4 Vector Table ................................................................................................................ 1302.5.5 Exception Priorities ...................................................................................................... 1312.5.6 Interrupt Priority Grouping ............................................................................................ 1322.5.7 Exception Entry and Return ......................................................................................... 1322.6 Fault Handling ............................................................................................................. 1352.6.1 Fault Types ................................................................................................................. 1362.6.2 Fault Escalation and Hard Faults .................................................................................. 1362.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1372.6.4 Lockup ....................................................................................................................... 1372.7 Power Management .................................................................................................... 1382.7.1 Entering Sleep Modes ................................................................................................. 1382.7.2 Wake Up from Sleep Mode .......................................................................................... 1382.8 Instruction Set Summary .............................................................................................. 139

3 Cortex-M4 Peripherals ......................................................................................... 1463.1 Functional Description ................................................................................................. 1463.1.1 System Timer (SysTick) ............................................................................................... 1473.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1483.1.3 System Control Block (SCB) ........................................................................................ 1493.1.4 Memory Protection Unit (MPU) ..................................................................................... 1493.1.5 Floating-Point Unit (FPU) ............................................................................................. 1543.2 Register Map .............................................................................................................. 1583.3 System Timer (SysTick) Register Descriptions .............................................................. 1613.4 NVIC Register Descriptions .......................................................................................... 1653.5 System Control Block (SCB) Register Descriptions ........................................................ 1753.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 2043.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 213

4 JTAG Interface ...................................................................................................... 2194.1 Block Diagram ............................................................................................................ 2204.2 Signal Description ....................................................................................................... 2204.3 Functional Description ................................................................................................. 2214.3.1 JTAG Interface Pins ..................................................................................................... 2214.3.2 JTAG TAP Controller ................................................................................................... 2234.3.3 Shift Registers ............................................................................................................ 2244.3.4 Operational Considerations .......................................................................................... 2244.4 Initialization and Configuration ..................................................................................... 2274.5 Register Descriptions .................................................................................................. 2274.5.1 Instruction Register (IR) ............................................................................................... 2284.5.2 Data Registers ............................................................................................................ 229

5 System Control ..................................................................................................... 2325.1 Signal Description ....................................................................................................... 2325.2 Functional Description ................................................................................................. 232


Table of Contents

5.2.1 Device Identification .................................................................................................... 2335.2.2 Reset Control .............................................................................................................. 2335.2.3 Non-Maskable Interrupt ............................................................................................... 2405.2.4 Power Control ............................................................................................................. 2415.2.5 Clock Control .............................................................................................................. 2425.2.6 System Control ........................................................................................................... 2525.3 Initialization and Configuration ..................................................................................... 2585.4 Register Map .............................................................................................................. 2605.5 System Control Register Descriptions (System Control Offset) ....................................... 2675.6 Cryptographic System Control Register Description (CCM Offset) .................................. 554

6 Processor Support and Exception Module ........................................................ 5566.1 Functional Description ................................................................................................. 5566.2 Register Map .............................................................................................................. 5566.3 Register Descriptions .................................................................................................. 556

7 Hibernation Module .............................................................................................. 5647.1 Block Diagram ............................................................................................................ 5667.2 Signal Description ....................................................................................................... 5667.3 Functional Description ................................................................................................. 5677.3.1 Register Access Timing ............................................................................................... 5687.3.2 Hibernation Clock Source ............................................................................................ 5687.3.3 System Implementation ............................................................................................... 5717.3.4 Battery Management ................................................................................................... 5727.3.5 Real-Time Clock .......................................................................................................... 5727.3.6 Tamper ....................................................................................................................... 5757.3.7 Battery-Backed Memory .............................................................................................. 5787.3.8 Power Control Using HIB ............................................................................................. 5787.3.9 Power Control Using VDD3ON Mode ........................................................................... 5797.3.10 Initiating Hibernate ...................................................................................................... 5797.3.11 Waking from Hibernate ................................................................................................ 5797.3.12 Arbitrary Power Removal ............................................................................................. 5807.3.13 Interrupts and Status ................................................................................................... 5817.4 Initialization and Configuration ..................................................................................... 5817.4.1 Initialization ................................................................................................................. 5817.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5827.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5827.4.4 External Wake-Up from Hibernation .............................................................................. 5837.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5847.4.6 Tamper Initialization ..................................................................................................... 5847.5 Register Map .............................................................................................................. 5847.6 Register Descriptions .................................................................................................. 586

8 Internal Memory ................................................................................................... 6338.1 Block Diagram ............................................................................................................ 6338.2 Functional Description ................................................................................................. 6358.2.1 SRAM ........................................................................................................................ 6358.2.2 ROM .......................................................................................................................... 6358.2.3 Flash Memory ............................................................................................................. 6378.2.4 EEPROM .................................................................................................................... 6488.2.5 Bus Matrix Memory Accesses ...................................................................................... 654



8.3 Register Map .............................................................................................................. 6548.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 6578.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 6838.6 Memory Register Descriptions (System Control Offset) .................................................. 700

9 Micro Direct Memory Access (DMA) ................................................................ 7119.1 Block Diagram ............................................................................................................ 7129.2 Functional Description ................................................................................................. 7129.2.1 Channel Assignments .................................................................................................. 7139.2.2 Priority ........................................................................................................................ 7149.2.3 Arbitration Size ............................................................................................................ 7159.2.4 Request Types ............................................................................................................ 7159.2.5 Channel Configuration ................................................................................................. 7169.2.6 Transfer Modes ........................................................................................................... 7189.2.7 Transfer Size and Increment ........................................................................................ 7269.2.8 Peripheral Interface ..................................................................................................... 7269.2.9 Software Request ........................................................................................................ 7279.2.10 Interrupts and Errors .................................................................................................... 7279.3 Initialization and Configuration ..................................................................................... 7279.3.1 Module Initialization ..................................................................................................... 7279.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 7289.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 7299.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 7319.3.5 Configuring Channel Assignments ................................................................................ 7349.4 Register Map .............................................................................................................. 7349.5 DMA Channel Control Structure ................................................................................. 7359.6 DMA Register Descriptions ........................................................................................ 742

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 77510.1 Signal Description ....................................................................................................... 77610.2 Pad Capabilities .......................................................................................................... 78110.3 Functional Description ................................................................................................. 78110.3.1 Data Control ............................................................................................................... 78310.3.2 Interrupt Control .......................................................................................................... 78510.3.3 Mode Control .............................................................................................................. 78610.3.4 Commit Control ........................................................................................................... 78710.3.5 Pad Control ................................................................................................................. 78710.3.6 Identification ............................................................................................................... 78810.4 Initialization and Configuration ..................................................................................... 78810.5 Register Map .............................................................................................................. 79010.6 Register Descriptions .................................................................................................. 793

11 External Peripheral Interface (EPI) ..................................................................... 85111.1 EPI Block Diagram ...................................................................................................... 85211.2 Signal Description ....................................................................................................... 85311.3 Functional Description ................................................................................................. 85411.3.1 Master Access to EPI .................................................................................................. 85511.3.2 Non-Blocking Reads .................................................................................................... 85511.3.3 DMA Operation ........................................................................................................... 85611.4 Initialization and Configuration ..................................................................................... 85711.4.1 EPI Interface Options .................................................................................................. 858


Table of Contents

11.4.2 SDRAM Mode ............................................................................................................. 85811.4.3 Host Bus Mode ........................................................................................................... 86211.4.4 General-Purpose Mode ............................................................................................... 88311.5 Register Map .............................................................................................................. 89011.6 Register Descriptions .................................................................................................. 892

12 Cyclical Redundancy Check (CRC) .................................................................... 98212.1 Functional Description ................................................................................................. 98212.1.1 CRC Support .............................................................................................................. 98212.2 Initialization and Configuration ..................................................................................... 98412.2.1 CRC Initialization and Configuration ............................................................................. 98412.3 Register Map .............................................................................................................. 98512.4 CRC Module Register Descriptions .............................................................................. 985

13 Advance Encryption Standard Accelerator (AES) ............................................ 99113.1 AES Overview ............................................................................................................. 99113.2 AES Functional Description .......................................................................................... 99113.2.1 AES Block Diagram ..................................................................................................... 99213.2.2 AES Algorithm ............................................................................................................ 99513.2.3 AES Operating Modes ................................................................................................. 99613.2.4 AES Software Reset .................................................................................................. 100413.2.5 Power Management .................................................................................................. 100413.2.6 Hardware Requests ................................................................................................... 100413.3 AES Performance Information .................................................................................... 100513.4 AES Module Programming Guide ............................................................................... 100713.4.1 AES Low - Level Programming Models ....................................................................... 100713.5 Register Map ............................................................................................................ 101213.6 AES Register Descriptions ......................................................................................... 101413.7 AES DMA Interrupt Register Descriptions (CCM Offset) ............................................. 1036

14 Data Encryption Standard Accelerator (DES) ................................................. 104314.1 DES Functional Description ........................................................................................ 104314.2 DES Block Diagram ................................................................................................... 104414.2.1 DMA Control ........................................................................................................... 104414.2.2 Interrupt Control ........................................................................................................ 104514.2.3 Register Interface ...................................................................................................... 104514.2.4 DES Engine .............................................................................................................. 104514.3 Software Reset ......................................................................................................... 104614.4 DES Supported Modes of Operation ........................................................................... 104614.4.1 ECB Feedback Mode ................................................................................................. 104614.5 DES Module Programming Guide -Low Level Programming Models ............................. 104814.5.1 Surrounding Modules Global Initialization .................................................................... 104814.5.2 Operational Modes Configuration ............................................................................... 104914.5.3 DES Events Servicing ................................................................................................ 105114.6 Register Map ............................................................................................................ 105214.7 DES Register Description .......................................................................................... 105314.8 DES DMA Interrupt Register Descriptions (CCM Offset) ............................................. 1067

15 SHA/MD5 Accelerator ........................................................................................ 107215.1 SHA/MD5 Functional Description ................................................................................ 107215.1.1 SHA/MD5 Block Diagram ........................................................................................... 1072



15.1.2 Power Management .................................................................................................. 107415.1.3 Reset Management ................................................................................................... 107415.1.4 DMA and Interrupt Requests .................................................................................... 107415.1.5 Operation Description ................................................................................................ 107515.1.6 SHA/MD5 Performance Information ............................................................................ 108115.1.7 SHA/MD5 Programming Guide ................................................................................... 108215.2 SHA/MD5 Register Map ............................................................................................. 108615.3 SHA/MD5 Register Descriptions ................................................................................. 108815.4 SHA/MD5 DMA Control Register Descriptions (Encryption Control Offset) ................... 1102

16 General-Purpose Timers .................................................................................... 110716.1 Block Diagram ........................................................................................................... 110816.2 Signal Description ..................................................................................................... 110916.3 Functional Description ............................................................................................... 111016.3.1 GPTM Reset Conditions ............................................................................................ 111116.3.2 Timer Clock Source ................................................................................................... 111116.3.3 Timer Modes ............................................................................................................. 111216.3.4 Wait-for-Trigger Mode ................................................................................................ 112116.3.5 Synchronizing GP Timer Blocks .................................................................................. 112216.3.6 DMA Operation ......................................................................................................... 112316.3.7 ADC Operation .......................................................................................................... 112316.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values .......................................... 112316.4 Initialization and Configuration .................................................................................... 112416.4.1 One-Shot/Periodic Timer Mode .................................................................................. 112416.4.2 Real-Time Clock (RTC) Mode ..................................................................................... 112516.4.3 Input Edge-Count Mode ............................................................................................. 112516.4.4 Input Edge Time Mode ............................................................................................... 112616.4.5 PWM Mode ............................................................................................................... 112616.5 Register Map ............................................................................................................ 112716.6 Register Descriptions ................................................................................................. 1128

17 Watchdog Timers ............................................................................................... 118117.1 Block Diagram ........................................................................................................... 118217.2 Functional Description ............................................................................................... 118217.2.1 Register Access Timing ............................................................................................. 118317.3 Initialization and Configuration .................................................................................... 118317.4 Register Map ............................................................................................................ 118317.5 Register Descriptions ................................................................................................. 1184

18 Analog-to-Digital Converter (ADC) ................................................................... 120618.1 Block Diagram ........................................................................................................... 120718.2 Signal Description ..................................................................................................... 120818.3 Functional Description ............................................................................................... 120918.3.1 Sample Sequencers .................................................................................................. 121018.3.2 Module Control .......................................................................................................... 121018.3.3 Hardware Sample Averaging Circuit ........................................................................... 121618.3.4 Analog-to-Digital Converter ........................................................................................ 121618.3.5 Differential Sampling .................................................................................................. 121818.3.6 Internal Temperature Sensor ...................................................................................... 122018.3.7 Digital Comparator Unit .............................................................................................. 122118.4 Initialization and Configuration .................................................................................... 1226


Table of Contents

18.4.1 Module Initialization ................................................................................................... 122618.4.2 Sample Sequencer Configuration ............................................................................... 122718.5 Register Map ............................................................................................................ 122718.6 Register Descriptions ................................................................................................. 1230

19 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 131519.1 Block Diagram ........................................................................................................... 131619.2 Signal Description ..................................................................................................... 131619.3 Functional Description ............................................................................................... 131819.3.1 Transmit/Receive Logic .............................................................................................. 131919.3.2 Baud-Rate Generation ............................................................................................... 131919.3.3 Data Transmission ..................................................................................................... 132019.3.4 Serial IR (SIR) ........................................................................................................... 132019.3.5 ISO 7816 Support ...................................................................................................... 132219.3.6 Modem Handshake Support ....................................................................................... 132219.3.7 9-Bit UART Mode ...................................................................................................... 132319.3.8 FIFO Operation ......................................................................................................... 132419.3.9 Interrupts .................................................................................................................. 132419.3.10 Loopback Operation .................................................................................................. 132519.3.11 DMA Operation ......................................................................................................... 132519.4 Initialization and Configuration .................................................................................... 132619.5 Register Map ............................................................................................................ 132719.6 Register Descriptions ................................................................................................. 1329

20 Quad Synchronous Serial Interface (QSSI) ..................................................... 138120.1 Block Diagram ........................................................................................................... 138120.2 Signal Description ..................................................................................................... 138220.3 Functional Description ............................................................................................... 138420.3.1 Bit Rate Generation ................................................................................................... 138420.3.2 FIFO Operation ......................................................................................................... 138420.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 138520.3.4 SSInFSS Function ..................................................................................................... 138620.3.5 High Speed Clock Operation ...................................................................................... 138720.3.6 Interrupts .................................................................................................................. 138720.3.7 Frame Formats ......................................................................................................... 138820.3.8 DMA Operation ......................................................................................................... 139520.4 Initialization and Configuration .................................................................................... 139520.4.1 Enhanced Mode Configuration ................................................................................... 139720.5 Register Map ............................................................................................................ 139820.6 Register Descriptions ................................................................................................. 1399

21 Inter-Integrated Circuit (I2C) Interface .............................................................. 143021.1 Block Diagram ........................................................................................................... 143121.2 Signal Description ..................................................................................................... 143221.3 Functional Description ............................................................................................... 143321.3.1 I2C Bus Functional Overview ...................................................................................... 143321.3.2 Available Speed Modes ............................................................................................. 143921.3.3 Interrupts .................................................................................................................. 144121.3.4 Loopback Operation .................................................................................................. 144221.3.5 FIFO and DMA Operation ........................................................................................ 144221.3.6 Command Sequence Flow Charts .............................................................................. 1444



21.4 Initialization and Configuration .................................................................................... 145221.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 145221.4.2 Configure the I2C Master to High Speed Mode ............................................................ 145321.5 Register Map ............................................................................................................ 145421.6 Register Descriptions (I2C Master) .............................................................................. 145621.7 Register Descriptions (I2C Slave) ............................................................................... 148521.8 Register Descriptions (I2C Status and Control) ............................................................ 1502

22 1-Wire Master Module ........................................................................................ 151122.1 Block Diagram ........................................................................................................... 151122.2 Signal Description ..................................................................................................... 151222.3 Functional Description ............................................................................................... 151222.3.1 1-Wire Protocol ......................................................................................................... 151222.3.2 Transport Protocol ..................................................................................................... 151522.3.3 Overdrive .................................................................................................................. 151622.3.4 Timing Override ......................................................................................................... 151622.3.5 Command Protocol .................................................................................................... 151722.3.6 Search (Enumeration) and Sub-Byte ........................................................................... 151822.3.7 Interrupts .................................................................................................................. 151822.3.8 DMA ......................................................................................................................... 151822.3.9 1-Wire Timing ............................................................................................................ 152022.4 Initialization and Configuration .................................................................................... 152022.5 Register Map ............................................................................................................ 152122.6 1-Wire Master Register Descriptions ........................................................................... 1522

23 Controller Area Network (CAN) Module ........................................................... 154023.1 Block Diagram ........................................................................................................... 154123.2 Signal Description ..................................................................................................... 154123.3 Functional Description ............................................................................................... 154223.3.1 Initialization ............................................................................................................... 154323.3.2 Operation .................................................................................................................. 154323.3.3 Transmitting Message Objects ................................................................................... 154423.3.4 Configuring a Transmit Message Object ...................................................................... 154523.3.5 Updating a Transmit Message Object ......................................................................... 154623.3.6 Accepting Received Message Objects ........................................................................ 154623.3.7 Receiving a Data Frame ............................................................................................ 154723.3.8 Receiving a Remote Frame ........................................................................................ 154723.3.9 Receive/Transmit Priority ........................................................................................... 154823.3.10 Configuring a Receive Message Object ...................................................................... 154823.3.11 Handling of Received Message Objects ...................................................................... 154923.3.12 Handling of Interrupts ................................................................................................ 155123.3.13 Test Mode ................................................................................................................. 155223.3.14 Bit Timing Configuration Error Considerations ............................................................. 155423.3.15 Bit Time and Bit Rate ................................................................................................. 155423.3.16 Calculating the Bit Timing Parameters ........................................................................ 155623.4 Register Map ............................................................................................................ 155923.5 CAN Register Descriptions ......................................................................................... 1560

24 Ethernet Controller ............................................................................................ 159124.1 Block Diagram ........................................................................................................... 1592


Table of Contents

24.2 Signal Description ..................................................................................................... 159224.3 Functional Description ............................................................................................... 159424.3.1 Ethernet Clock Control ............................................................................................... 159424.3.2 MII/RMII Interface Signals .......................................................................................... 159724.3.3 DMA Controller ......................................................................................................... 159824.3.4 TX/RX Controller ....................................................................................................... 162224.3.5 MAC Operation ......................................................................................................... 162624.3.6 IEEE 1588 and Advanced Timestamp Function ........................................................... 162824.3.7 Frame Filtering .......................................................................................................... 163724.3.8 Source Address, VLAN, and CRC Insertion, Replacement or Deletion .......................... 163824.3.9 Checksum Offload Engine .......................................................................................... 164024.3.10 MAC Management Counters ...................................................................................... 164124.3.11 Power Management Module ....................................................................................... 164224.3.12 Serial Management Interface ..................................................................................... 164524.3.13 Reduced Media Independent Interface (RMII) ............................................................. 164524.3.14 Interrupt Configuration ............................................................................................... 164524.4 Ethernet PHY ............................................................................................................ 164524.4.1 Integrated PHY Block Diagram ................................................................................... 164624.4.2 Functional Description ............................................................................................... 164624.4.3 Interface Configuration ............................................................................................... 165224.5 Initialization and Configuration .................................................................................... 165324.5.1 Ethernet PHY Initialization .......................................................................................... 165424.6 Register Map ............................................................................................................ 165624.7 Ethernet MAC Register Descriptions ........................................................................... 166024.8 Ethernet PHY Register Descriptions ........................................................................... 1779

25 Universal Serial Bus (USB) Controller ............................................................. 183425.1 Block Diagram ........................................................................................................... 183525.2 Signal Description ..................................................................................................... 183525.3 Register Map ............................................................................................................ 1836

26 LCD Controller .................................................................................................... 184326.1 Block Diagram ........................................................................................................... 184326.2 Signal Description ..................................................................................................... 184426.3 Functional Description ............................................................................................... 184626.3.1 Clocking ................................................................................................................... 184626.3.2 LCD DMA Engine ...................................................................................................... 184826.3.3 LIDD Bus Operation .................................................................................................. 185026.3.4 Raster Control ........................................................................................................... 185126.3.5 LCD Frame Buffer ..................................................................................................... 185426.3.6 Palette RAM .............................................................................................................. 185426.3.7 Palette ...................................................................................................................... 186026.3.8 Gray-Scaler/Serializer - Passive (STN) Mode .............................................................. 186026.3.9 Gray-Scaler/Serializer - Active (TFT) Mode ................................................................. 186026.3.10 Color/Grayscale Intensities and Modulation Rates ....................................................... 186026.3.11 Summary of Color Depth ............................................................................................ 186126.3.12 Output Format ........................................................................................................... 186126.3.13 Subpicture Feature .................................................................................................... 186226.4 Interrupts .................................................................................................................. 186326.5 Bus Transaction Modes ............................................................................................. 1864



26.6 Initialization and Configuration .................................................................................... 186426.7 Register Map ............................................................................................................ 186526.8 Register Descriptions ................................................................................................. 1866

27 Analog Comparators .......................................................................................... 191227.1 Block Diagram ........................................................................................................... 191327.2 Signal Description ..................................................................................................... 191327.3 Functional Description ............................................................................................... 191427.3.1 Internal Reference Programming ................................................................................ 191527.4 Initialization and Configuration .................................................................................... 191727.5 Register Map ............................................................................................................ 191827.6 Register Descriptions ................................................................................................. 1918

28 Pulse Width Modulator (PWM) .......................................................................... 192828.1 Block Diagram ........................................................................................................... 192928.2 Signal Description ..................................................................................................... 193128.3 Functional Description ............................................................................................... 193128.3.1 Clock Configuration ................................................................................................... 193128.3.2 PWM Timer ............................................................................................................... 193228.3.3 PWM Comparators .................................................................................................... 193228.3.4 PWM Signal Generator .............................................................................................. 193328.3.5 Dead-Band Generator ............................................................................................... 193428.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 193428.3.7 Synchronization Methods .......................................................................................... 193528.3.8 Fault Conditions ........................................................................................................ 193628.3.9 Output Control Block .................................................................................................. 193728.4 Initialization and Configuration .................................................................................... 193728.5 Register Map ............................................................................................................ 193828.6 Register Descriptions ................................................................................................. 1941

29 Quadrature Encoder Interface (QEI) ................................................................. 200729.1 Block Diagram ........................................................................................................... 200729.2 Signal Description ..................................................................................................... 200929.3 Functional Description ............................................................................................... 200929.4 Initialization and Configuration .................................................................................... 201229.5 Register Map ............................................................................................................ 201229.6 Register Descriptions ................................................................................................. 2013

30 Pin Diagram ........................................................................................................ 203031 Signal Tables ...................................................................................................... 203131.1 Signals by Pin Number .............................................................................................. 203231.2 Signals by Signal Name ............................................................................................. 205131.3 Signals by Function, Except for GPIO ......................................................................... 206731.4 GPIO Pins and Alternate Functions ............................................................................ 208431.5 Possible Pin Assignments for Alternate Functions ....................................................... 208931.6 Connections for Unused Signals ................................................................................. 2096

32 Electrical Characteristics .................................................................................. 209832.1 Maximum Ratings ...................................................................................................... 209832.2 Operating Characteristics ........................................................................................... 209932.3 Recommended Operating Conditions ......................................................................... 210032.3.1 DC Operating Conditions ........................................................................................... 2100


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32.3.2 Recommended GPIO Operating Characteristics .......................................................... 210032.4 Load Conditions ........................................................................................................ 210332.5 JTAG and Boundary Scan .......................................................................................... 210432.6 Power and Brown-Out ............................................................................................... 210632.6.1 VDDA Levels .............................................................................................................. 210632.6.2 VDD Levels ................................................................................................................ 210732.6.3 VDDC Levels .............................................................................................................. 210832.6.4 Response ................................................................................................................. 210932.7 Reset ........................................................................................................................ 211132.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 211432.9 Clocks ...................................................................................................................... 211532.9.1 PLL Specifications ..................................................................................................... 211532.9.2 PIOSC Specifications ................................................................................................ 211732.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 211732.9.4 Hibernation Clock Source Specifications ..................................................................... 211732.9.5 Main Oscillator Specifications ..................................................................................... 211832.9.6 System Clock Specification with ADC Operation .......................................................... 212232.9.7 System Clock Specification with USB Operation .......................................................... 212232.10 Sleep Modes ............................................................................................................. 212332.11 Hibernation Module ................................................................................................... 212532.12 Flash Memory ........................................................................................................... 212732.13 EEPROM .................................................................................................................. 212832.14 Input/Output Pin Characteristics ................................................................................. 212932.14.1 Types of I/O Pins and ESD Protection ......................................................................... 213132.15 External Peripheral Interface (EPI) .............................................................................. 213332.16 Analog-to-Digital Converter (ADC) .............................................................................. 214132.17 Synchronous Serial Interface (SSI) ............................................................................. 214732.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 215032.19 Ethernet Controller .................................................................................................... 215132.19.1 DC Characteristics .................................................................................................... 215132.19.2 Clock Characteristics ................................................................................................. 215132.19.3 AC Characteristics ..................................................................................................... 215232.20 Universal Serial Bus (USB) Controller ......................................................................... 215932.21 LCD Controller .......................................................................................................... 216132.21.1 LCD Interface Display Driver (LIDD Mode) .................................................................. 216132.21.2 LCD Raster Mode ...................................................................................................... 217132.22 Analog Comparator ................................................................................................... 217832.23 Pulse-Width Modulator (PWM) ................................................................................... 218032.24 Current Consumption ................................................................................................ 2181

A Package Information .......................................................................................... 2186A.1 Orderable Devices ..................................................................................................... 2186A.2 Device Nomenclature ................................................................................................ 2186A.3 Device Markings ........................................................................................................ 2186A.4 Packaging Diagram ................................................................................................... 2188



List of FiguresFigure 1-1. Tiva TM4C129XNCZAD Microcontroller High-Level Block Diagram ...................... 62Figure 2-1. CPU Block Diagram ............................................................................................. 93Figure 2-2. TPIU Block Diagram ............................................................................................ 94Figure 2-3. Cortex-M4F Register Set ...................................................................................... 97Figure 2-4. Bit-Band Mapping .............................................................................................. 122Figure 2-5. Data Storage ..................................................................................................... 123Figure 2-6. Vector Table ...................................................................................................... 131Figure 2-7. Exception Stack Frame ...................................................................................... 134Figure 3-1. SRD Use Example ............................................................................................. 152Figure 3-2. FPU Register Bank ............................................................................................ 155Figure 4-1. JTAG Module Block Diagram .............................................................................. 220Figure 4-2. Test Access Port State Machine ......................................................................... 224Figure 4-3. IDCODE Register Format ................................................................................... 230Figure 4-4. BYPASS Register Format ................................................................................... 230Figure 4-5. Boundary Scan Register Format ......................................................................... 230Figure 5-1. Basic RST Configuration .................................................................................... 236Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 236Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 236Figure 5-4. Power Architecture ............................................................................................ 242Figure 5-5. Main Clock Tree ................................................................................................ 245Figure 5-6. Module Clock Selection ...................................................................................... 254Figure 7-1. Hibernation Module Block Diagram ..................................................................... 566Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 570Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 570Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 571Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 575Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 575Figure 7-7. Tamper Block Diagram ....................................................................................... 575Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 576Figure 8-1. Internal Memory Block Diagram .......................................................................... 634Figure 8-2. Flash Memory Configuration ............................................................................... 638Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 639Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 639Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 640Figure 8-6. Prefetch Fills from Flash ..................................................................................... 641Figure 8-7. Mirror Mode Function ......................................................................................... 642Figure 9-1. DMA Block Diagram ......................................................................................... 712Figure 9-2. Example of Ping-Pong DMA Transaction ........................................................... 719Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 721Figure 9-4. Memory Scatter-Gather, DMA Copy Sequence .................................................. 722Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 724Figure 9-6. Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 725Figure 10-1. Digital I/O Pads ................................................................................................. 782Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 783Figure 10-3. GPIODATA Write Example ................................................................................. 784


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Figure 10-4. GPIODATA Read Example ................................................................................. 784Figure 11-1. EPI Block Diagram ............................................................................................. 853Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 861Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 861Figure 11-4. SDRAM Write Cycle ........................................................................................... 862Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 873Figure 11-6. iRDY Signal Connection ..................................................................................... 873Figure 11-7. PSRAM Burst Read ........................................................................................... 875Figure 11-8. PSRAM Burst Write ........................................................................................... 876Figure 11-9. Read Delay During Refresh Event ...................................................................... 877Figure 11-10. Write Delay During Refresh Event ....................................................................... 877Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 878Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 881Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 881Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 882Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or

Quad CSn ......................................................................................................... 882Figure 11-16. Continuous Read Mode Accesses ...................................................................... 882Figure 11-17. Write Followed by Read to External FIFO ............................................................ 883Figure 11-18. Two-Entry FIFO ................................................................................................. 883Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 886Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 887Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 887Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 888Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 888Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 888Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 888Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 889Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 889Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 889Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 890Figure 13-1. AES Block Diagram ........................................................................................... 992Figure 13-2. AES - ECB Feedback Mode ............................................................................... 996Figure 13-3. AES - CBC Feedback Mode ............................................................................... 997Figure 13-4. AES Encryption With CTR/ICM Mode .................................................................. 997Figure 13-5. AES - CFB Feedback Mode ............................................................................... 998Figure 13-6. AES - F8 Mode .................................................................................................. 999Figure 13-7. AES - XTS Operation ......................................................................................... 999Figure 13-8. AES - F9 Operation .......................................................................................... 1000Figure 13-9. AES - CBC-MAC Authentication Mode .............................................................. 1001Figure 13-10. AES - GCM Operation ...................................................................................... 1002Figure 13-11. AES - CCM Operation ...................................................................................... 1003Figure 13-12. AES Polling Mode ............................................................................................ 1010Figure 13-13. AES Interrupt Service ....................................................................................... 1012Figure 14-1. DES Block Diagram ......................................................................................... 1044Figure 14-2. DES - ECB Feedback Mode ............................................................................. 1047Figure 14-3. DES3DES - CBC Feedback Mode .................................................................... 1047



Figure 14-4. DES3DES-CFB Feedback Mode ....................................................................... 1048Figure 14-5. DES Polling Mode ............................................................................................ 1050Figure 14-6. DES Interrupt Service ...................................................................................... 1051Figure 14-7. DES Context Input Event Service ...................................................................... 1052Figure 15-1. SHA/MD5 Module Block Diagram ..................................................................... 1073Figure 15-2. SHA/MD5 Polling Mode .................................................................................... 1084Figure 15-3. SHA/MD5 Interrupt Subroutine ......................................................................... 1086Figure 16-1. GPTM Module Block Diagram ........................................................................... 1108Figure 16-2. Input Edge-Count Mode Example, Counting Down ............................................. 1116Figure 16-3. 16-Bit Input Edge-Time Mode Example ............................................................. 1118Figure 16-4. 16-Bit PWM Mode Example .............................................................................. 1120Figure 16-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................. 1120Figure 16-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................. 1121Figure 16-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................. 1121Figure 16-8. Timer Daisy Chain ........................................................................................... 1122Figure 17-1. WDT Module Block Diagram ............................................................................. 1182Figure 18-1. Implementation of Two ADC Blocks .................................................................. 1207Figure 18-2. ADC Module Block Diagram ............................................................................. 1208Figure 18-3. ADC Sample Phases ....................................................................................... 1213Figure 18-4. Doubling the ADC Sample Rate ........................................................................ 1214Figure 18-5. Skewed Sampling ............................................................................................ 1215Figure 18-6. Sample Averaging Example .............................................................................. 1216Figure 18-7. ADC Input Equivalency .................................................................................... 1217Figure 18-8. ADC Voltage Reference ................................................................................... 1217Figure 18-9. ADC Conversion Result ................................................................................... 1218Figure 18-10. Differential Voltage Representation ................................................................... 1220Figure 18-11. Internal Temperature Sensor Characteristic ....................................................... 1221Figure 18-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1224Figure 18-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1225Figure 18-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1226Figure 19-1. UART Module Block Diagram ........................................................................... 1316Figure 19-2. UART Character Frame .................................................................................... 1319Figure 19-3. IrDA Data Modulation ....................................................................................... 1321Figure 20-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1382Figure 20-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1389Figure 20-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1390Figure 20-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1391Figure 20-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1391Figure 20-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1392Figure 20-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1393Figure 20-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1393Figure 20-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1394Figure 21-1. I2C Block Diagram ........................................................................................... 1431Figure 21-2. I2C Bus Configuration ....................................................................................... 1433Figure 21-3. START and STOP Conditions ........................................................................... 1434Figure 21-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1435Figure 21-5. R/S Bit in First Byte .......................................................................................... 1435Figure 21-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1435


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Figure 21-7. High-Speed Data Format .................................................................................. 1441Figure 21-8. Master Single TRANSMIT ................................................................................ 1445Figure 21-9. Master Single RECEIVE ................................................................................... 1446Figure 21-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1447Figure 21-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1448Figure 21-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1449Figure 21-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1450Figure 21-14. Standard High Speed Mode Master Transmit ..................................................... 1451Figure 21-15. Slave Command Sequence .............................................................................. 1452Figure 22-1. 1-Wire Block Diagram ...................................................................................... 1511Figure 22-2. 1-Wire Reset Protocol ...................................................................................... 1513Figure 22-3. 1-Wire Master Transmitting a 1 ......................................................................... 1514Figure 22-4. 1-Wire Master Transmitting a 0' ........................................................................ 1514Figure 22-5. 1-Wire Master Receiving a 1 Signal from a Slave ............................................... 1515Figure 22-6. 1-Wire Master Receiving a 0 Signal from a Slave ............................................... 1515Figure 23-1. CAN Controller Block Diagram .......................................................................... 1541Figure 23-2. CAN Data/Remote Frame ................................................................................. 1542Figure 23-3. Message Objects in a FIFO Buffer .................................................................... 1551Figure 23-4. CAN Bit Time ................................................................................................... 1555Figure 24-1. Ethernet MAC with Integrated PHY Interface ..................................................... 1592Figure 24-2. Ethernet MAC and PHY Clock Structure ............................................................ 1595Figure 24-3. MII Clock Structure .......................................................................................... 1596Figure 24-4. RMII Clock Structure ........................................................................................ 1597Figure 24-5. Enhanced Transmit Descriptor Structure ........................................................... 1602Figure 24-6. Enhanced Receive Descriptor Structure ............................................................ 1607Figure 24-7. TX DMA Default Operation Using Descriptors .................................................... 1614Figure 24-8. TX DMA OSF Mode Operation Using Descriptors .............................................. 1616Figure 24-9. RX DMA Operation Flow .................................................................................. 1619Figure 24-10. Networked Time Synchronization ...................................................................... 1629Figure 24-11. System Time Update Using Fine Correction Method .......................................... 1631Figure 24-12. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path

Correction ....................................................................................................... 1634Figure 24-13. Wake-Up Frame