Title Goes Here Byline/Subtitle Goes Here · Daniel Gitlin Confidential InformationDaniel Gitlin For entire logic cores or blocks 3D packaging is enough to provide the interconnect

Daniel Gitlin*

Independent Consultant

CoolCubeTM Technology

A cost effective solution to 3D-IC

July 2016

*Work done as a consultant to CEA-Leti

Daniel Gitlin Confidential InformationDaniel Gitlin

Contents

Introduction to CoolCubeTM

Technology and partitioning

Yield, Cost Model and Moore’s Law


CoolCubeTM is a technology to stack active layers of

transistors and interconnect

True monolithic geometries

3D contact pitch <100nm, MIV density > 108/mm2

CoolCubeTM Structure


Hi quality Si

layer

formation to

form new

layers of

transistors and

interconnects

Leveraging

mature

process steps

from FDSOI

manufacturing

technology

CoolCubeTM Key Enabler


CoolCubeTM 3D Contact


For entire logic cores or blocks 3D packaging is enough to

provide the interconnect density required

For gate (cell based) or transistor level connectivity

Monolithic 3D is needed

3D partitioning and

technology


IC speed and power gains obtained by decreasing wirelength

~50% area reduction

Optimal results pending 3D P&R, but demonstrators exist with

modified 2D P&R

Partitioning levels


IC speed and power gains obtained by

Boosting FET performance and decreasing wirelength

Area reduction target of 50% is more challenging

2D P&R can be used

Partitioning levels


Thermal Budget management


150 300 450 600 750 900 105010

-10

10-9

10-8

10-7

10-6

nMOS

W=170 nm, Vdd=0.8 V

I OF

F (

A/µ

m)

ION

(A/m)

POR HT

No Implant

No PAI

Medium PAI

High PAI

100 %90 %

0 150 300 450 600 750 90010

-9

10-8

10-7

10-6

10-5

pMOS

W=170 nm, Vdd=0.8 V

I OF

F (

A/µ

m)

ION

(A/m)

POR HT

No Implant

No PAI

Medium PAI

High PAI

100 %

95 %95%

High performance transistor optimization work continues and low

temperature transistors are close to state of the art high

temperature transistors with modest number of development

wafers*

* L. Pasini et. al., 2016 Symposium on VLSI Technology

CoolCubeTM Transistors


Monolithic 3D will reduce interconnect wirelength and

therefore performance and power

What about cost?

Chip area is reduced, but complexity is increased

Front end complexity doubles (2-tier transistor structure)

Modest increase of number of metal layers

Modest increase of 3D specific steps

This talk will focus on this question

The CoolCubeTM advantages


The so called Bose Einstein yield model has been used

extensibly by the foundries and fabless companies.

It was proposed by Okabe* et. al. (1972) and takes into

account the process complexity

The Model and it's parameters are

Yield=1/(1+DoA)N

Where:

Do is the defect density per layer and unit area,

N is the Process complexity number

* Okabe, T., Nagata, M., & Shimada, S. (1972) Analysis on yield of integrated circuits and a new

expression for the yield. Electrical Engineering in Japan, 92, 135-141

Yield Model


The Bose-Einstein yield model for 3D wafers have the

additional factor Y3D. Namely, Y = Y2D * Y3D

Y = 1/(1 + DoA)N * 1/(1 + D3DA)N3D

Defining relative parameters d and n we have:

The yield is

Y = 1/(1 + DoA)N * 1/(1+ dDoA)nN

With

d=D3D/Do

n=N3D/N

CoolCubeTM Yield Model


The number of good die per wafer (NGD) is given by

NGD = Yield * GDW

Where GDW is the number of gross die per wafer

The cost for the 3D dice is

Cost per die = 3D wafer cost / NGD or,

Cost per 3D die = 3D wafers cost / (Yield * GDW)

The 3D wafer cost relative to the 2D wafers is proportional to the

relative complexity ~ (N + N3D)/N or (n+1)

CoolCubeTM Cost Model


The cost of 3D/2D chips has three factors, the relative

wafer manufacturing cost (n+1), the gross die per wafer

ratio, and the yield ratio

The area reduction ratio a and the relative complexity n

are

Cell/Cell a~2, n~0.4-0.6

CoolCubeTM Cost model


Observations

The target for CoolCubeTM is to meet d=1 (if tier1 transistors=tier2)

a is expected to be around 2 and (n+1) between 1 and 2

Do nothing case: n=0 and a=1, Cost 3D/2D = 1 as expected

The cost strongly depends on relative complexity and area

Relative complexity impacts both yield and wafer price

Relative area impacts yield and number of gross die per

wafer

It is likely that area and process complexity can be traded off in

both design (partitioning choices) and process architecture

FEOL vs. BEOL complexity etc

CoolCubeTM Cost Model


Example

N=24, Do=0.1 defects per in2

a=2

The relative (3D/2D) Number of good die per wafer will be

calculated as a function of area (A) and the defect density d

for n = ½

The Cost of 3D/2D will be calculated as a function of area

(A) and process complexity (n) for d=1

Sensitivity to N and Do

Example


Area (A) of 3D wafers in mm2

Re

lati

ve

go

od

die

pe

r w

afe

r

Co

olC

ub

eT

Mvs

. tr

ad

itio

na

l p

roc

es

s Do = 0.1, N=24, n=0.5, a=2

•NGD is # of good die per wfr

•a is the area reduction factor

•n is the normalized complexity # relative to 2D (N)

•d is the normalized defect density relative to 2D (Do)

Example 1, NGD



Re

lati

ve

die

co

st

Co

olC

ub

eT

M

vs

. tr

ad

itio

na

l p

roc

es

s

Do = 0.1, N=24, a=2, d=1

•NGD is # of good die per wfr

•a is the area reduction factor

•n is the normalized complexity # relative to 2D (N)

•d is the normalized defect density relative to 2D (Do)

Cost vs. Complexity


Finer geometry

nodes have

increasing

complexity N

The cost

reduction ratio

improves slowly

for advanced

nodes

Rela

tive d

ie c

ost

Co

olC

ub

eT

M

vs.

trad

itio

nal

pro

cess

Do = 0.1, N=24, a=2, d=1

Do = 0.1, N=34, a=2, d=1


Sensitivity to N


Rela

tive d

ie c

ost

Co

olC

ub

eT

M

vs.

trad

itio

nal

pro

cess

Do = 0.2, N=24, a=2, d=1

Do = 0.1, N=24, a=2, d=1Do = 0.07, N=24, a=2, d=1


Relatively modest

sensitivity to baseline

defect density Do. The

highest Do is, the most

impact CoolCubeTM

technology has on relative

cost

Sensitivity to Do

Do = 0.1, N=24, a=2, d=1


Both Moore’s Law and CoolCubeTM transform a technology in a

similar fashion

28nm

28nm CC 22nm CC 14nm CC 10nm CC

22nm 14nm 10nm

Go G1 G2 G3m1,s1 m2,s2 m3,s3

n1,r1 n2,r2 n3,r3 n4,r4

m, s are the complexity number and area reduction factor for Moore’s law

n, r are the complexity number and area reduction factor for CoolCubeTM

3D effect and Moore’s Law


Moore’s complexity rate increases continuously, balance between

FEOL and BEOL (note the CC complexity number is constant at 1.5)

28nm

28nm CC 22nm CC 14nm CC 10nm CC

22nm 14nm 10nm

Go G1 G2 G31.15,.55 1.2,.65 1.25,.7

1.5,.51.5,.5 1.5,.5

1.5,.5

Example analyzed


Moore’s Law in

advanced technology


0

0

1

1

2

2

3

3

Relative number of components

Rela

tive c

ost

per

co

mp

on

en

t3D effect on Moore’s

Law


0 1 2 3

Generations

Relative cost per component at

fixed component count

3D effect on Moore’s

Law, case 1


Moore’s Generations

3D effect on Moore’s

Law, case 1


CoolCubeTM can reduce cost by ~50% and improves

interconnect delay and capacitive load

Improved performance and reduced total power

In contrast to Moore’s law migrations, the area reduction for

node n does not depend on n+1 manufacturing tools and

processes

The benefits of CoolCubeTM migrations are not eroded by

lack of adequate litho tools

Concluding Remarks


Many degrees of freedom and use modes for this

technology

Example: Easier way to optimize FET performance

Path to other materials III-V and Ge co-integration

Co-integration of Heterogeneous functions and

technologies

Concluding Remarks (2)

© 2013 Tabula, Inc. 30

CoolCubeTM

Thank you

for your attention!

Documents

Title Goes Here Byline/Subtitle Goes Here · Daniel Gitlin Confidential InformationDaniel Gitlin For entire logic cores or blocks 3D packaging is enough to provide the interconnect