Timing Faults in VLSI circuits Elzbieta Piwowarska Institute of Microelectronics and Optoelectronics Warsaw University of Technology Reason Tutorial, Tomsk,

Timing Faults in VLSI circuits

Elzbieta Piwowarska

Institute of Microelectronics and Optoelectronics

Warsaw University of Technology

Reason Tutorial, Tomsk, September 06, 2004

Reason Tutorial, Tomsk, September 06, 2004 Elzbieta Piwowarska, IMiO 2

Agenda

• Timing analysis of integrated circuits– timing designing

– timing spreadsheet

– worst-case timing spreadsheet

– statistical spreadsheet

• Timing faults– propagation effects

– interference effects

– power noise

– clock skew and jitter

• conclusions


What is timing (analysis)?• Timing means coordinating the system so that the data reach

components at the correct time for the required frequency – clock signals activate the latches/registers so that the hold and

setup times are not violated

D D

clk

combinational logic

tcomb

D2 (fault)

D2 (correct)

tcomb

clk

D1

Q1


Timing strategies• common-clock timing

• source synchronous timing– the clock (strobe) is sent from the driver chip instead of

separate clock source. The data are transmitted to the receiver, and the short time later, the strobe is sent to latch the data into the receiver - speed of a system depends on the delay between the data and the strobe only.

data output to core

Busclock

D Q D Q

strobe input from core

Busclock

DQ

DQ

Delay

data input from core

driver

receiver

strobe

data

example solution for source synchronization:

• strobe is two times bus clock cycle

• each data transaction requires two clock pulses

data

time

strobe


Timing designing

• define the initial system timings– estimate the values of max and min setup and hold

times for each component of the system

– estimate the values of max and min skew and jitter

– estimate the delays of components and interconnects

• use the spreadsheet to implement timing equations and get the starting point for the design– assume the certain amount of margin for interconnect

delays

• improve the design after post-layout analysis


Timing spreadsheet

• It allows the components designing team (silicon designers) and system design team to coordinate working on a system.

• It is updated periodically, it shows the progress of the design, set design targets, perform timing trade-offs.


Worst-case timing spreadsheet

• It assumes that all components meet the worst possible performance (the greatest delays, skew, jitter etc.).

• This assumptions guaranties that the product will be reliable and robust.

• For systems with very high speed the worst-case assumption might make impossible to design the system - the calculations show the negative margin for the required frequency.


Source synchronous setup timing equations

• Tvb - time valid before

Tvb Tco_data (Tco_strobe Tdelay )

Tskew Tflt_data Tflt_strobe

Tsetup_m arg in Tvb Tsetup Tskew

Tdata Tco _ data Tflt _ data

Tstrobe Tco_ strobe Tflt _ strobe TdelayTsetup _m arg in Tstrobe Tdata Tsetup

Tdelay

Bus clock

Strobe at driver

Tco_strobe

Data at driver

Strobe at receiver

Tflt_strobe

Data at receiver

Tsetup

Setup Margin

Tco_data

Tflt_data


Source synchronous setup timing - example

Setup -Tvb,min-Tskew,max-Tsetup-Tguard = Tsetup_marginTvb Tskew Tsetup Tguard Tmargin

target [ns] -1,25 0,55 0,50 0,20 0,00predicted [ns] -1,25 0,65 0,50 0,20 -0,10difference [ns] 0,00 -0,10 0,00 0,00 0,10

Source synchronous Agent1 driving Agent2

Tguard -tester guard band - the accuracy to which the component can be tested


Statistical spreadsheet

• existing in conjunction with the worst-case spreadsheet

• the probability of the negative margin is calculated. If it is acceptable small the design will proceed.

• the mean and a standard deviation are obtained for each component

• It assumes approximately normal (Gaussian) distributions and that the components are completely independent on each other - this works good as a next iteration of the design.


Statistical spreadsheet (cont)

– timing margins are calculated on the base of mean values and

standard deviations

– the most important obstacle - the necessity of knowledge of

correct and values

– k is the number of standard deviations (i.e., k = 3 refers to a

3spread

– the risk of failure is estimated on the base of value k for each

the margin starts becoming positive

• k = 1 -> p = 68.26%

• k = 3.09 (3 -> p = 99.8%

Tm arg in _ setup vb setup skew Tguard k vb2 setup

2 skew2


• Now the additional effects affecting timing values must be taken into account.

• These additional effects are noises caused by the influence of many working components on each other.

• The performance metrics should be captured, defined and calculated.


Design optimization• performed after the initial timings and the metrics have been defined

• begins with the determination of all the signal categories within the

design

– common-clock signals

– source-synchronous signals

– controls

– clock

– other categories

• determination the estimates of all the system variables i.e.:

– I/O capacitance

– interconnect parameters

– buffer strengths and edge rates

– termination values


Design methodologySpreadsheets & metrics

Signal categories

Topology options

Simulation of design

Reference design

Sensitivity analysis

Routing guidelines Buffer guidelines

Design check

Takeout

Pass Fail

Fix


Sensitivity analysis

• It ranks the variables as to how strongly they affect the

system and highlight which variables affect the solution

most and in what way they affect the system.

• During the sensitivity analysis every variable is varied in

simulation and the performance metrics are observed while

each variable is swept.

• The result is a solution space that will place strict limits on

the variables under control of the designer (interconnect

lengths, spacing etc.).

• Monte Carlo analysis is still the most common method of

the sensitivity analysis.


Monte Carlo analysis– Initial MC analysis determines the corner conditions, set

solution space - puts limits on all the variables under control.

– The ordered parameter sweeps is used to sweep one or two

variables at the time so that the behavior of the system can be

understood and parameter limits can be chosen.

by Dominik Kasprowicz

clock skew as a function of buffer location


Propagation effects - delay

• propagation delay - time the signal needs to

travel along the line from driver to receiver

• it depends on the RLC interconnect parameters

driver receiver

interconnect

digital signal

TD1.047 LC 1.4RC

LC x LC

RC 0.37RCx 2


Propagation effects - reflections

Vs

Zs

ZLZ 0

TD = x /v

t=2 TD , V=V i + sV i + sLV i

t=0 , V=V i

t=TD , V=V i + LV i

reflection

• They are unwanted signals propagated on the signaling paths due to improper (unmatched) termination.

• The signal reaches steady state after several bounces.

• Impedance mismatches can occur wherever there is a

discontinuity (connection) in the circuit.

time, ps

0.5

1.0

1.5

2.0

2.5

source end

load end


Simulation Reference Loads• The numbers entered into the timing spreadsheet are

calculated on the base of standard load.

• If the simulated loads differ significantly from these the

outputs buffers will see when driving the system, the

simulation will not represent the actual system timings

• To avoid the problems Tco values remain based on

standard loads and Tflt is calculated so that the total delay

is correct.

Ttotal Tco Tflt

Ttotal Tco_ actual Tpd _ wire

driver

interconnect

tco

tflt

ttot

driver receiver

receiver


Interference effects - crosstalk• Crosstalk is unwanted signal generated on a nearby victim

line as a result of transmitting line (aggressor).

• crosstalk simulation (1 cm long Met1 wires with min spacing in CMOS 0.7 m technology - Vnoise >1/2 Vdd)

Vin

agressor line

victim line


Interference effects - crosstalk

• caused by electric and magnetic fields, represented by mutual capacitance and inductance respectively

• Crosstalk effects are functions of rise and fall times of the aggressor, distance between the lines and the presence of the reference plane.

Vinductive noise Lm

dIdriverdt

Icapacitance noise CmdVdriverdt

odd mode even mode


crosstalk - line configuration

• Crosstalk can cause the glitches in a victim line or change

the shape (delay) of signal propagating in it.

• Crosstalk is reduced when reference planes or additional

shielding wires are added.

• These techniques pair a signal trace with the shielding

plane (line). The current loop is smaller what decreases the

magnetic field in signal wires.

signal microstrip

signal microstrip

signal striplinesignal stripline

ground/power

ground/power

dielectric

metal tracemetal plane


Timing analysis with crosstalk

• The crosstalk model considering transition times and driver

strength is needed

– there are some models (i. e. Chen model)

– they need many calculations to find the desired components of

timing equations

• The simplest gate delay models are not correct in crosstalk

existence.

• In the combinational logic, existence of crosstalk sites can

cause cyclic dependency between the delays of lines.


Substrate coupling• Current is injected into the substrate through various

mechanisms:

– large passive elements inject displacement current,

– active devices inject current directly and capacitively.

• These currents flow to points of low potential such as

substrate taps and couple to other elements.

• These phenomena change the propagating signals.

Memory Core

groundcoupling current

injection


Power noise - digital core noise

• called also power supply noise, simultaneous switching

noise (SSN), delta I noise

• the greatest contributors to this noise are clock trees and

memory structures

• these elements generate large spikes of current when

switching

• thousands of flops transitioning through the switching

zone simultaneously can draw enough current to

momentarily pull the core Vdd significantly down


Digital core noise

• The greatest component of this noise is inductive

noise.

• Inductance of chip package and lead frame

influence the chip performance.

V NLtotdI

dt

C1

C2

C3

C4

T1

T2 T4

T3Vdd

L ext

I1

I2

I3I4

I1 I4+


Digital core noise - example

VDD VSS

2000

RS

Vdd

Vss

set

reset

Q

power supply wire length = 6 mm

power supply wire width= 6.5 m

clock rise/fall time = 200 ps


Simultaneously Switching Outputs SSO

• When the I/O buffers switch, they will all inject current into the

package ground plane and chip substrate.

• Because of the inherent inductance and resistance in package

ground plane and the chip substrate, the ground potential can

actually rise up.

• The I/O power supply will also be pulled down as the buffers

switch.

• The reduced voltage on a buffer cell can cause a reduction in

drive current, which increases propagation delay, increases rise

and fall time.

• This effect can look like jitter which reduces the timing margin.


Power noise - power delivery resonance

• LC ladder power delivery network at the board level

interacts with the equivalent parameters of the chip

• resonance available for frequency

L ext

Cchip

Rchip Z(j)

Z j 0 Lext

CtotRchip f0

1

2 LextCtot

IF:

•Lext = 10 nH (typical value)

•system frequency @ 1 GHz

•THEN

•Cchip = 100 pf (1000-10 000 gates)


Clock skew

Clock skew is the difference between actual and nominal

interarrival times of a pair of clock signals.

– types of clock distribution architectures

– H tree - example of distortions

H tree grid combined - grid + tree

nominal actual

A

B

5 ns

5 ns

skew = 1 ns


Clock skew - reasons

• RANDOM - manufacturing process dependent

space distribution of:

– transistor parameters:

• gate length L,

• threshold voltage VTH

– wire parameters of tree branches

• SYSTEMATIC - architecture dependent space

distribution of:

– load of the branches CL,

– power supply ,

– temperature

metal and dielectric thickness


Clock skew - how to account for in timing analysis?

1. Common clock:• The slowest and the quickest branch are recognized. The

worst-case clock skew T clock_skew is assumed as the difference between them.

• T clock_skew is added to setup time of each latch/flip-flop.

2. Other synchronization techniques:• Hierarchy of clock domains with the same clock skew is

introduced.• Global and local skews are added to the same domain latches

setup times.slow branch

quick branch


Clock jitter

• Jitter means the fluctuations in the clock frequency generated usually by PLL circuits.

• The greater jitter the smaller timing margin for data signals.

• Jitter is caused by different noises:– switching (dI/dt) noise,

– power supply noises,

– substrate coupling,

– random noises.

• It can be taken into account in the timing analysis in the similar way as clock skew, but its values are even more difficult to predict.


Conclusions

• Manufacturing process, architecture and layout dependent reasons result in differences of nominal and actual values for rising/falling edges and propagation times.

• These effects create the loss of timing margin in timing analysis.

• Unfortunately not every effect is predictable and countable - these effects must be avoided in design.

• Careful timing analysis and design techniques avoiding the timing faults are the best way to ensure better yield.

• There are many efforts (publications) related to timing analysis methods.


References• S. H. Hall, G. W. Hall, J. A. McCall,”High_Speed Digital System

Design,” J. Wiley & Sons, Inc. 2000.

• A. M. Niknejad, R. G. Meyer,”Design, Simulatio and Applications of Inductors and Transformers for Si RF Ics,” Kluwer Ac. P. 2003.

• D. Chase “Achieving signal integrity for ASICs, PCBs and packages,” Eedesign, Dec. 19, 2003.

• D. Harris, M. Horowitz „Timing Analysis Including Clock Skew”, IEEE Trans. on CAD, vol. 18, no. 11, Nov. 1999, pp 1608-1618

• I-De Huang, S. K. Gupta, M. Breuer,”Accurate and Efficient Static Timing Analisys with Crosstalk,” Proc. of ICCD’2002.

• Dominik Kasprowicz private materials, PhD thesis in preparation.

• Elzbieta Piwowarska - simulation results and examples - taken from different works.


Thanks for your attention!

Documents

Timing Faults in VLSI circuits Elzbieta Piwowarska Institute of Microelectronics and Optoelectronics Warsaw University of Technology Reason Tutorial, Tomsk,