TILEPROCESSOR

AND I/ODEVICE GUIDE

FOR THE TILE-GX FAMILY OF PROCESSORSRELEASE 1.12

DOC. NO. UG404OCTOBER 2014

TILERA CORPORATION

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Document number: UG404

Release 1.12

Date 15 October 2014

Tilera Corporation

Information info@tilera.comWeb Site http://www.tilera.com

http://www.beanshell.org/developer.html

Tile Processor and I/O Device Guide for the TILE-Gx Family of Processors iii

Contents

PREFACE

About this Manual .................................................................................................................................. xxi

Intended Audience ................................................................................................................................. xxi

Manual Contents Description .............................................................................................................. xxi

Related Documents .............................................................................................................................. xxiii

Technical or Customer Support ........................................................................................................ xxiii

Product Information ............................................................................................................................ xxiii

Notation Conventions ......................................................................................................................... xxiii

Conventions for Register Descriptions .............................................................................................xxivConventions for Processor Families .............................................................................................................xxiv

Byte and Bit Order ..........................................................................................................................................xxiv

Reserved Fields ................................................................................................................................................. xxv

Numbering ........................................................................................................................................................ xxv

CHAPTER 1 I/O DEVICE INTRODUCTION1.1 Overview ................................................................................................................................................ 1

1.1.1 Tile-to-Device Communication ................................................................................................................. 11.1.2 Coherent Shared Memory .......................................................................................................................... 21.1.3 Device Protection ........................................................................................................................................ 21.1.4 Interrupts ...................................................................................................................................................... 21.1.5 Device Discovery ......................................................................................................................................... 31.1.6 Common Registers ...................................................................................................................................... 3

CHAPTER 2 TILE PROCESSOR2.1 System Architecture Overview .......................................................................................................... 72.2 Memory Architecture .......................................................................................................................... 82.3 Memory Addressing ............................................................................................................................ 9

2.3.1 TLB Management ........................................................................................................................................ 92.3.1.1 TLB Miss Handling ....................................................................................................................... 24

2.4 Memory Consistency Model ............................................................................................................ 262.4.1 Overview .................................................................................................................................................... 26

2.5 TILE-Gx Page Attribute Transitions and Cache Flushes ........................................................... 282.6 Protection ............................................................................................................................................. 29

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2.6.1 Levels of Protection ................................................................................................................................... 292.6.2 Protected Resources .................................................................................................................................. 29

2.7 Interrupt Model ...................................................................................................................................292.7.1 Introduction ................................................................................................................................................ 29

2.7.1.1 Interrupt/Exception State ............................................................................................................ 302.7.1.2 Nested Interrupts/Exceptions ..................................................................................................... 312.7.1.3 Interrupt Traits ............................................................................................................................... 312.7.1.4 Interrupt Masks .............................................................................................................................. 322.7.1.5 INTCTRL and Protection of Interrupt Masks ............................................................................ 322.7.1.6 VLIW and Interrupts ..................................................................................................................... 33

2.7.2 Interrupt and Exception List .................................................................................................................... 342.7.3 Interrupt State, Control Registers, Double Faults, and IRET .............................................................. 35

2.7.3.1 Interrupt State and Control Registers ......................................................................................... 352.7.3.2 Double Faults ................................................................................................................................. 392.7.3.3 IRET ................................................................................................................................................. 40

2.7.4 Interprocessor Interrupt (IPI) .................................................................................................................. 402.7.5 Distributed Interrupt Processing ............................................................................................................ 402.7.6 Proxying Interrupts ................................................................................................................................... 412.7.7 Lower Protection Level Interrupts .......................................................................................................... 412.7.8 Downcalls ................................................................................................................................................... 41

2.8 Software-Visible Dynamic Networks ............................................................................................442.8.1 Overview .................................................................................................................................................... 44

2.8.1.1 Register Mapping and Interlock .................................................................................................. 442.8.1.2 Routing ............................................................................................................................................ 452.8.1.3 Demultiplexing .............................................................................................................................. 462.8.1.4 Receive-Side Buffering .................................................................................................................. 47

2.8.2 Ordering ...................................................................................................................................................... 472.8.2.1 Packet Format ................................................................................................................................. 47

2.8.3 Network Hardwall .................................................................................................................................... 482.8.4 Interrupts .................................................................................................................................................... 482.8.5 Deadlocks ................................................................................................................................................... 48

2.9 Special Purpose Registers (SPRs) ....................................................................................................492.10 Performance Counters / System Diagnostics ..............................................................................49

2.10.1 In-Tile System Devices ............................................................................................................................ 492.10.1.1 Tile Timer and AUX_TILE_TIMER ........................................................................................... 492.10.1.2 Cycle Counter ............................................................................................................................... 49

2.10.2 Events ........................................................................................................................................................ 492.10.3 Counters .................................................................................................................................................... 502.10.4 Watch Registers ....................................................................................................................................... 502.10.5 Pass SPR .................................................................................................................................................... 502.10.6 Broadcast Networks ................................................................................................................................ 502.10.7 System Software Debug .......................................................................................................................... 51

2.10.7.1 Tile Debug Port ............................................................................................................................ 512.10.7.2 Quiesce .......................................................................................................................................... 56

2.11 Boot Processes and Data Format ....................................................................................................56

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Contents

2.11.1 Boot Flow .................................................................................................................................................. 562.11.2 Chip Modes and Reset Behavior ........................................................................................................... 572.11.3 Boot FIFO .................................................................................................................................................. 58

CHAPTER 3 DOUBLE DATA RATE SDRAM (DDR3) INTERFACE3.1 Overview .............................................................................................................................................. 593.2 Interfaces .............................................................................................................................................. 60

3.2.1 DDR3 Interface .......................................................................................................................................... 603.2.2 Network Interface ..................................................................................................................................... 60

3.3 Data Flows ........................................................................................................................................... 603.3.1 QDN Memory Read Request Flow ......................................................................................................... 613.3.2 RDN Memory Read Response Flow ....................................................................................................... 613.3.3 QDN Memory Write Request Flow ........................................................................................................ 613.3.4 RDN Memory Write Response Flow ...................................................................................................... 613.3.5 Non-Cacheline Write Flow and Masked Write Flow ........................................................................... 61

3.4 Ordering ............................................................................................................................................... 623.4.1 Out of Order Dispatch .............................................................................................................................. 623.4.2 Out of Order Response ............................................................................................................................. 62

3.5 Addressing ........................................................................................................................................... 623.5.1 Memory Controller Striping .................................................................................................................... 633.5.2 DDR Address Mapping (from Memory Address Mapping) .............................................................. 633.5.3 Memory Rank/Bank Hashing ................................................................................................................. 643.5.4 Logical Rank and Physical Rank Mapping ........................................................................................... 64

3.6 Scheduler ............................................................................................................................................. 643.6.1 Memory Page Management Policy ......................................................................................................... 643.6.2 Memory Request Reordering .................................................................................................................. 653.6.3 Memory Command Reordering .............................................................................................................. 65

3.7 DIMM Support ................................................................................................................................... 653.7.1 Serial Presence-Detect EEPROM Support ............................................................................................. 663.7.2 Temperature Sensor .................................................................................................................................. 663.7.3 Address/Command Parity ...................................................................................................................... 663.7.4 RDIMM Control Word Access ................................................................................................................ 663.7.5 Memory PHY Training ............................................................................................................................ 66

CHAPTER 4 PCIE CONTROLLER ARCHITECTURE (TRIO)4.1 Overview .............................................................................................................................................. 67

4.1.1 Communication and Data Transfer ........................................................................................................ 684.1.2 PHY Sharing ............................................................................................................................................... 68

4.2 MMIO Interface .................................................................................................................................. 694.3 PIO Communication .......................................................................................................................... 70

4.3.1 Memoryless Operation ............................................................................................................................. 704.3.2 Ordering ..................................................................................................................................................... 71

4.4 Push DMA ........................................................................................................................................... 714.4.1 Descriptors ................................................................................................................................................. 714.4.2 Request Partitioning ................................................................................................................................. 73

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4.4.3 Notification and Flow Control ................................................................................................................ 734.4.3.1 Descriptor Rings Slot Available Notification ............................................................................. 734.4.3.2 Transaction Complete Notification ............................................................................................. 734.4.3.3 PCI System Notification ................................................................................................................ 73

4.4.4 Flush/Fence ................................................................................................................................................ 734.5 Pull-DMA .............................................................................................................................................74

4.5.1 Pull DMA Notifications and Flow Control ............................................................................................ 754.5.2 Descriptor Rings Slot Available Notification ........................................................................................ 754.5.3 Transaction Complete Notification ......................................................................................................... 754.5.4 Request Tracker ......................................................................................................................................... 75

4.6 Flush/Fence ..........................................................................................................................................754.7 Address Translation ...........................................................................................................................75

4.7.1 I/O MMU ................................................................................................................................................... 764.8 Ingress Mapping Regions .................................................................................................................77

4.8.1 Tile Map Memory Regions ....................................................................................................................... 784.8.1.1 MAP-MEM Interrupts ................................................................................................................... 784.8.1.2 Map-Region Ordering ................................................................................................................... 79

4.8.2 Scatter Queue Regions .............................................................................................................................. 804.8.3 Boot and Rshim Regions .......................................................................................................................... 814.8.4 Map Fence ................................................................................................................................................... 81

4.9 Panic Mode ...........................................................................................................................................824.10 Connection to mPIPE .......................................................................................................................824.11 Deadlock .............................................................................................................................................84

CHAPTER 5 PCIE MAC INTERFACE5.1 Introduction .........................................................................................................................................855.2 Register Spaces ....................................................................................................................................86

5.2.1 Type-0/1 and Virtual Function Configuration Space .......................................................................... 875.3 Port Configuration ..............................................................................................................................885.4 IO Address Mapping .........................................................................................................................88

5.4.1 Boot and Diagnostics Access ................................................................................................................... 885.5 Interrupts ..............................................................................................................................................885.6 Power Management ............................................................................................................................885.7 Link Down Handling .........................................................................................................................895.8 SERDES Configuration .....................................................................................................................895.9 Streaming Interface ............................................................................................................................89

5.9.1 Packetization .............................................................................................................................................. 905.9.2 Interrupts .................................................................................................................................................... 905.9.3 Flow Control .............................................................................................................................................. 90

CHAPTER 6 MPIPE ARCHITECTURE6.1 Overview ..............................................................................................................................................91

6.1.1 Glossary ...................................................................................................................................................... 916.1.2 PHY and DMA Sharing ............................................................................................................................ 926.1.3 Channelization ........................................................................................................................................... 92

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Contents

6.1.4 Channels vs. Ports ..................................................................................................................................... 936.1.5 Priority Queues .......................................................................................................................................... 936.1.6 Communication Model ............................................................................................................................ 93

6.2 Ingress Services .................................................................................................................................. 936.2.1 Typical Ingress Flow ................................................................................................................................. 936.2.2 Buffers ......................................................................................................................................................... 94

6.2.2.1 Buffer Stacks ................................................................................................................................... 956.2.2.2 Buffer Chaining .............................................................................................................................. 966.2.2.3 Buffer Release ................................................................................................................................. 986.2.2.4 Buffer Stack Engine ....................................................................................................................... 99

6.2.3 iDMA Packet Descriptors ....................................................................................................................... 1006.2.4 Notification Rings ................................................................................................................................... 1026.2.5 Store-and-Forward vs. Cut-Through .................................................................................................... 1036.2.6 Classifier ................................................................................................................................................... 103

6.2.6.1 Parallel Processing ....................................................................................................................... 1046.2.6.2 Cycle Budget ................................................................................................................................ 104

6.2.7 Processor Architecture ............................................................................................................................ 1056.2.7.1 Header and Descriptor ............................................................................................................... 1066.2.7.2 Table Lookup ............................................................................................................................... 1066.2.7.3 Special Registers .......................................................................................................................... 1066.2.7.4 Hash Accumulator ...................................................................................................................... 1076.2.7.5 Endianness .................................................................................................................................... 1076.2.7.6 Header/Descriptor Valid Indicators ........................................................................................ 1076.2.7.7 Classifier Pipeline ........................................................................................................................ 1086.2.7.8 Stalls ............................................................................................................................................... 1086.2.7.9 Persistent State ............................................................................................................................. 1096.2.7.10 Exceptions ................................................................................................................................... 1106.2.7.11 Classifier Configuration ........................................................................................................... 1106.2.7.12 Classifier Blast Re/Programming ....................................................................................... 1106.2.7.13 SPRs ............................................................................................................................................. 1126.2.7.14 Classifier Tools ........................................................................................................................... 112

6.2.8 iDMA Engine ........................................................................................................................................... 1126.2.8.1 Temporal Hints for iDMA Writes ............................................................................................. 113

6.2.9 Load Balancer .......................................................................................................................................... 1146.2.9.1 BucketSTS ..................................................................................................................................... 1146.2.9.2 Notification Groups ..................................................................................................................... 1146.2.9.3 Notification Ring Arbitration ..................................................................................................... 1156.2.9.4 Load Balance Override Flows .................................................................................................... 117

6.2.10 Checksum ............................................................................................................................................... 1186.2.11 Notification ............................................................................................................................................ 118

6.2.11.1 Tail Pointer Updates Polling Model .................................................................................... 1196.2.11.2 Notification Interrupts .............................................................................................................. 1196.2.11.3 Timestamp and Sequence Number Information .................................................................. 120

6.2.12 Counters ................................................................................................................................................. 1206.2.13 Software Override Flows ..................................................................................................................... 120

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viii Tile Processor and I/O Device Guide for the TILE-Gx Family of Processors

6.2.13.1 Software Classification .............................................................................................................. 1206.2.13.2 Software Load Balancing .......................................................................................................... 1216.2.13.3 Software Buffer Management .................................................................................................. 121

6.3 Ingress Channel Flow Control .......................................................................................................1216.4 Packet Drops ......................................................................................................................................122

6.4.1 Drop/Truncate: iPkt Full ....................................................................................................................... 1226.4.2 Drop: Classifier Cycle-Budget ............................................................................................................... 1226.4.3 Drop: Classifier Program ........................................................................................................................ 1226.4.4 Drop: NotifRing Full ............................................................................................................................... 1226.4.5 Drop: Bucket Count Full ......................................................................................................................... 1226.4.6 Drop/Truncate: Out of Buffers ............................................................................................................. 123

6.5 Egress Services ..................................................................................................................................1236.5.1 Typical Egress Flow ................................................................................................................................ 1236.5.2 eDMA Packet Descriptors ...................................................................................................................... 124

6.5.2.1 eDMA Descriptor Fetch .............................................................................................................. 1256.5.2.2 eDMA Descriptor Hunt Mode ................................................................................................... 1256.5.2.3 Explicit eDMA Descriptor Post .................................................................................................. 1266.5.2.4 eDMA Descriptor Ring Reordering .......................................................................................... 1266.5.2.5 Descriptor Prefetch and Memory Ordering ............................................................................. 1276.5.2.6 Descriptor-Write and Descriptor-Post Ordering .................................................................... 1276.5.2.7 Ring to Channel Mapping .......................................................................................................... 1276.5.2.8 Descriptor Errors .......................................................................................................................... 128

6.5.3 Buffers ....................................................................................................................................................... 1286.5.3.1 Chaining ........................................................................................................................................ 1286.5.3.2 Descriptor-Based Gather ............................................................................................................. 1286.5.3.3 Transaction Sizing and Buffer Offsets ...................................................................................... 1296.5.3.4 Buffer Release ............................................................................................................................... 1296.5.3.5 Egress VA Translations ............................................................................................................... 130

6.5.4 eDMA Engine ........................................................................................................................................... 1306.5.5 ePkt Buffering .......................................................................................................................................... 1306.5.6 Notifications ............................................................................................................................................. 130

6.5.6.1 Descriptor Ring Head .................................................................................................................. 1306.5.6.2 Descriptor Complete Interrupt and Counter ........................................................................... 131

6.5.7 Checksum ................................................................................................................................................. 1316.5.7.1 eDMA Checksum Buffer Limitations ....................................................................................... 131

6.5.8 Egress Picker ............................................................................................................................................ 1326.5.8.1 Egress Priority Arbitration ......................................................................................................... 1326.5.8.2 Egress Priority Flow Control ...................................................................................................... 132

6.5.9 Special Flows ............................................................................................................................................ 1336.5.9.1 NoSend Option ............................................................................................................................ 1336.5.9.2 Size=0 Option ............................................................................................................................... 1336.5.9.3 eDMA Loopback .......................................................................................................................... 133

6.6 Virtual Memory .................................................................................................................................1336.6.1 I/O TLB Details ....................................................................................................................................... 134

6.7 PA Distribution .................................................................................................................................135

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Contents

6.7.1 Locality Hints ........................................................................................................................................... 1356.7.2 Pinning ...................................................................................................................................................... 136

6.8 MMIO ................................................................................................................................................. 1366.8.1 MAC Configuration Registers ............................................................................................................... 1366.8.2 Service Domains ...................................................................................................................................... 137

6.9 Interrupts ........................................................................................................................................... 1386.10 UserIO .............................................................................................................................................. 1396.11 Flush Mechanisms ......................................................................................................................... 139

6.11.1 MMIO Access Drain .............................................................................................................................. 1396.11.2 NotifRing Drain ..................................................................................................................................... 1396.11.3 Ingress Channel Drain .......................................................................................................................... 1406.11.4 EDMA Ring Drain ................................................................................................................................. 140

CHAPTER 7 XAUI MAC INTERFACE7.1 Introduction ....................................................................................................................................... 143

7.1.1 Features ..................................................................................................................................................... 1437.2 Register Spaces ................................................................................................................................. 1437.3 MAC and Channel Mapping ......................................................................................................... 1447.4 Port Configuration ........................................................................................................................... 144

7.4.1 Lane Sharing with SGMII ....................................................................................................................... 1457.5 Flow Control ...................................................................................................................................... 145

7.5.1 Priority-Based Flow Control .................................................................................................................. 1457.6 Interrupts ........................................................................................................................................... 1457.7 Timestamping and IEEE 1588 ........................................................................................................ 1457.8 MDIO ................................................................................................................................................. 1517.9 Statistics ............................................................................................................................................. 1517.10 Filtering ............................................................................................................................................ 151

7.10.1 Type ID Checking ................................................................................................................................. 1527.10.2 Broadcast Address ................................................................................................................................ 1527.10.3 Hash Addressing ................................................................................................................................... 153

7.11 Special Modes ................................................................................................................................. 1537.11.1 Pass All Frames Mode .......................................................................................................................... 1537.11.2 Custom Preamble .................................................................................................................................. 1537.11.3 Short IPG ................................................................................................................................................ 153

7.12 SERDES Control ............................................................................................................................. 1547.13 LEDs .................................................................................................................................................. 154

CHAPTER 8 SGMII MAC INTERFACE8.1 Introduction ....................................................................................................................................... 155

8.1.1 Features ..................................................................................................................................................... 1558.2 Register Spaces ................................................................................................................................. 1558.3 MAC and Channel Mapping ......................................................................................................... 1568.4 Port Configuration ........................................................................................................................... 156

8.4.1 Lane Sharing with XAUI ........................................................................................................................ 1568.5 Flow Control ...................................................................................................................................... 157

8.5.1 Priority-Based Flow Control .................................................................................................................. 157

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8.6 Interrupts ............................................................................................................................................1578.7 Timestamping and IEEE 1588 .........................................................................................................1578.8 MDIO ..................................................................................................................................................1588.9 10/100Mbps Support .........................................................................................................................1588.10 Half-Duplex Support .....................................................................................................................1588.11 Energy Efficient Ethernet Support (IEEE 802.3az) ....................................................................158

8.11.1 802.3az Operation .................................................................................................................................. 1588.11.2 LPI Operation in the MAC ................................................................................................................... 159

8.12 PCS Auto-Negotiation ...................................................................................................................1598.12.1 PCS Collision Detect and Carrier Sense ............................................................................................. 1608.12.2 Link Status .............................................................................................................................................. 160

8.13 Statistics ............................................................................................................................................1608.14 Filtering ............................................................................................................................................160

8.14.1 Type ID Checking .................................................................................................................................. 1618.14.2 Broadcast Address ................................................................................................................................. 1628.14.3 Hash Addressing ................................................................................................................................... 162

CHAPTER 9 TILE-GX INTERLAKEN INTERFACE9.1 Overview ............................................................................................................................................163

9.1.1 Channel Mapping .................................................................................................................................... 1639.2 TX Interface ........................................................................................................................................163

9.2.1 Burst Scheduler ........................................................................................................................................ 1649.2.2 Packet vs. Burst ........................................................................................................................................ 164

9.3 RX Interface .......................................................................................................................................1649.4 Flow Control ......................................................................................................................................164

9.4.1 Link Level TX Flow Control .................................................................................................................. 1659.4.2 Channel-Based Flow Control ................................................................................................................. 1659.4.3 Link Level RX Flow Control .................................................................................................................. 1659.4.4 Out-of-Band Flow Control ..................................................................................................................... 165

9.5 Statistics ..............................................................................................................................................1659.6 Initialization ......................................................................................................................................1669.7 Error Handling ..................................................................................................................................166

CHAPTER 10 USB INTERFACE10.1 Overview ..........................................................................................................................................16710.2 External I/O Interface .....................................................................................................................16810.3 Mesh Interface .................................................................................................................................168

10.3.1 MMIO Interface ..................................................................................................................................... 16810.3.2 Memory Access ...................................................................................................................................... 16910.3.3 Interrupt Interface ................................................................................................................................. 170

10.4 Host Controller ................................................................................................................................17010.5 Device Endpoint .............................................................................................................................170

10.5.1 Configuration ......................................................................................................................................... 17010.5.2 MAC Design ........................................................................................................................................... 17010.5.3 MAC Interrupts ..................................................................................................................................... 171

10.5.3.1 Device Interrupts ....................................................................................................................... 171

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10.5.3.2 Endpoint Interrupts ................................................................................................................... 17110.6 Standalone Device Operation ...................................................................................................... 171

10.6.1 Interface and Endpoint Configuration ............................................................................................... 17210.6.2 Boot/Debug Interface ........................................................................................................................... 17210.6.3 Tile-Monitor Interface ........................................................................................................................... 173

CHAPTER 11 COMMON ACCELERATOR INTERFACE (MICA)11.1 Introduction ..................................................................................................................................... 17511.2 Overview and Major Functional Blocks .................................................................................... 176

11.2.1 Major Blocks ........................................................................................................................................... 17711.2.1.1 Mesh Interface ............................................................................................................................ 17711.2.1.2 MMIO Registers and Context State ......................................................................................... 17711.2.1.3 Operand Data Specification ..................................................................................................... 18111.2.1.4 TLB (Translation Lookaside Buffer) ........................................................................................ 18311.2.1.5 Engine Scheduler ....................................................................................................................... 18411.2.1.6 Function Specific Engines ......................................................................................................... 18411.2.1.7 DMA Channels .......................................................................................................................... 18411.2.1.8 PA to Header Generation ......................................................................................................... 184

11.3 Operation Flow ............................................................................................................................... 18411.3.1 General Flow .......................................................................................................................................... 18411.3.2 Tile Interrupts ........................................................................................................................................ 18511.3.3 Specific Use Examples .......................................................................................................................... 186

11.3.3.1 General Use ................................................................................................................................ 18611.3.3.2 TLB Miss ..................................................................................................................................... 18611.3.3.3 Deferred Interrupts ................................................................................................................... 18711.3.3.4 Pause Context ............................................................................................................................. 18711.3.3.5 TLB Probe ................................................................................................................................... 18811.3.3.6 TLB Shootdown ......................................................................................................................... 18811.3.3.7 Terminate Operation for a Specific Context .......................................................................... 188

CHAPTER 12 CRYPTOGRAPHIC ACCELERATOR INTERFACE12.1 Engines ............................................................................................................................................. 19112.2 Schedulers ....................................................................................................................................... 19112.3 Contexts ............................................................................................................................................ 19112.4 Engine-Specific Details ................................................................................................................. 191

12.4.1 Memory-to-Memory Copy Engine ..................................................................................................... 19112.4.1.1 Usage Constraints for the Engine ............................................................................................ 191

12.4.2 Crypto Packet Processor ....................................................................................................................... 19212.4.2.1 Usage Constraints for the Crypto Packet Processor Engine ............................................... 192

12.4.3 KASUMI and SNOW-3G Engine ........................................................................................................ 19312.4.3.1 KASUMI Engine ........................................................................................................................ 19312.4.3.2 SNOW-3G Engine ...................................................................................................................... 19412.4.3.3 Usage Constraints for the Engine ............................................................................................ 195

12.4.4 Public Key Accelerator Engine ............................................................................................................ 19512.4.4.1 Descriptor Ring Management .................................................................................................. 196

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12.4.4.2 Command Descriptor Contents ............................................................................................... 19712.4.4.3 Result Descriptor Contents ....................................................................................................... 19712.4.4.4 Interrupts .................................................................................................................................... 197

CHAPTER 13 COMPRESSION ACCELERATOR INTERFACE13.1 Overview ..........................................................................................................................................19913.2 Data Flows ........................................................................................................................................199

13.2.1 Typical Compression Flow .................................................................................................................. 19913.2.2 Typical Decompression Flow .............................................................................................................. 200

13.3 Compression Engine ......................................................................................................................20013.3.1 Engine Configuration ........................................................................................................................... 20013.3.2 GZIP Handling ...................................................................................................................................... 201

13.4 Decompression Engine ..................................................................................................................20113.4.1 GZIP Handling ...................................................................................................................................... 201

13.5 Memory-to-Memory Copy ............................................................................................................20113.6 API .....................................................................................................................................................201

13.6.1 Context Registers ................................................................................................................................... 20213.6.2 Compression/Decompression Engine Registers .............................................................................. 20213.6.3 Status Registers ...................................................................................................................................... 20313.6.4 Transaction Size ..................................................................................................................................... 20313.6.5 Data Expansion Handling .................................................................................................................... 20313.6.6 Performance Counter ............................................................................................................................ 204

CHAPTER 14 FLEXIBLE I/O INTERFACE14.1 Overview ..........................................................................................................................................20514.2 Virtualization and Protection Support .......................................................................................20514.3 MMIO Register Map ......................................................................................................................20614.4 Interrupts ..........................................................................................................................................20614.5 I/O Pin Driver Configuration .......................................................................................................20614.6 I/O Pin Clocking Control ..............................................................................................................20614.7 Pin Control and Data Accesses ....................................................................................................20714.8 Reset/Initialization .........................................................................................................................20714.9 Performance .....................................................................................................................................207

CHAPTER 15 RSHIM INTERFACES15.1 Level-1 Boot .....................................................................................................................................20915.2 I/O Discovery ...................................................................................................................................20915.3 tile-monitor FIFOs ..........................................................................................................................20915.4 Down-Counters and Watchdog ....................................................................................................21015.5 Rshim JTAG .....................................................................................................................................21015.6 Reset Control ...................................................................................................................................21015.7 Byte Access Interface ......................................................................................................................21015.8 Remote Interface Access and Device Protection .......................................................................210

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CHAPTER 16 UART INTERFACES16.1 UART Interface ............................................................................................................................... 211

16.1.1 Overview ................................................................................................................................................ 21116.1.1.1 Protocol Mode ............................................................................................................................ 211

16.1.2 Data Flows .............................................................................................................................................. 21316.1.2.1 Receiving Data ........................................................................................................................... 21316.1.2.2 Transmitting Data ...................................................................................................................... 213

16.1.3 Flow Control .......................................................................................................................................... 21316.1.4 Master Arbitration ................................................................................................................................. 21316.1.5 8/64 Bits Handling ................................................................................................................................ 214

16.1.5.1 Remote UART Writes ................................................................................................................ 21416.1.5.2 Remote UART Reads ................................................................................................................ 214

16.1.6 Error Handling and Interrupts ............................................................................................................ 21416.1.7 UART Controller Registers .................................................................................................................. 214

CHAPTER 17 I2C MASTER INTERFACE17.1 Overview .......................................................................................................................................... 215

17.1.1 I2C Master Boot Options ...................................................................................................................... 21517.1.2 Boot ROM Format ................................................................................................................................. 21617.1.3 Boot Operations ..................................................................................................................................... 217

17.2 Usage Model .................................................................................................................................... 21717.2.1 Generic Operation ................................................................................................................................. 21717.2.2 Software Instructions ............................................................................................................................ 220

17.2.3 I2C EEPROM Page Mode ..................................................................................................................... 22217.2.4 Error Handling and Interrupts ............................................................................................................ 222

17.3 Registers ........................................................................................................................................... 222

CHAPTER 18 I2C SLAVE INTERFACE18.1 Overview .......................................................................................................................................... 22318.2 Usage Model .................................................................................................................................... 223

18.2.1 Data Flows .............................................................................................................................................. 22318.2.2 Direct-Addressing ................................................................................................................................. 22418.2.3 No-Address Access ............................................................................................................................... 22418.2.4 8 Bits / 64 Bits Handling ...................................................................................................................... 22418.2.5 Acknowledge Control ........................................................................................................................... 22518.2.6 Access Arbitration ................................................................................................................................. 22518.2.7 Error Handling and Interrupts ............................................................................................................ 225

CHAPTER 19 SPI INTERFACE19.1 Overview .......................................................................................................................................... 227

19.1.1 Boot Options .......................................................................................................................................... 22719.1.2 Boot ROM Format ................................................................................................................................. 227

19.2 Usage Model .................................................................................................................................... 22919.2.1 Boot Operation ....................................................................................................................................... 229

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19.2.2 SPI Flash Operations ............................................................................................................................. 22919.2.2.1 SPI Flash Instructions ................................................................................................................ 22919.2.2.2 SPI Configurable Instruction Sets ............................................................................................ 23019.2.2.3 SPI Flash Unknown Instruction ............................................................................................... 23019.2.2.4 SPI Flash Deep Power-Down ................................................................................................... 23019.2.2.5 SPI Flash Write In-Progress ...................................................................................................... 23019.2.2.6 SPI Flash Write Protection ........................................................................................................ 23019.2.2.7 SPI Flash Page Mode ................................................................................................................. 23119.2.2.8 SPI Flash Interface ...................................................................................................................... 23119.2.2.9 Software Command Sequences to Execute an SPI Flash Instruction ................................. 23119.2.2.10 Interface Timing ....................................................................................................................... 233

19.2.3 Rshim Interface ...................................................................................................................................... 23419.2.3.1 Rshim Register Interface ........................................................................................................... 23419.2.3.2 Rshim Host Interface ................................................................................................................. 23419.2.3.3 Error Handling and Interrupts ................................................................................................ 234

APPENDIX A JTAG INTERFACE

APPENDIX B CLASSIFIER INSTRUCTIONS AND SPRSB.1 Classifier Instructions .....................................................................................................................237

B.1.1 Arithmetic Instructions .......................................................................................................................... 238B.1.2 Comparison Instructions ....................................................................................................................... 240B.1.3 Control Instructions ................................................................................................................................ 242B.1.4 Logical Instructions ................................................................................................................................ 243B.1.5 Miscellaneous Instructions .................................................................................................................... 245

B.2 Registers .............................................................................................................................................246B.2.1 Register Summary ................................................................................................................................... 246B.2.2 Register Definitions ................................................................................................................................ 247

APPENDIX C MISCELLANEOUS ACCELERATOR SPECIFICATIONSC.1 SNOW-3G Engines ..........................................................................................................................255

C.1.1 Specification Summary .......................................................................................................................... 255C.1.2 Performance ............................................................................................................................................. 256

C.1.2.1 Introduction ................................................................................................................................. 256C.1.3 Functional Description ........................................................................................................................... 257

C.1.3.1 SNOW Key Stream Generator ................................................................................................... 257C.1.4 Feedback Logic and XOR ...................................................................................................................... 258C.1.5 Examples .................................................................................................................................................. 259C.1.6 Operations ............................................................................................................................................... 260

C.1.6.1 General Operations ..................................................................................................................... 260C.1.6.2 Encryption Modes: UEA2 / 128-EEA1 .................................................................................... 260

C.2 KASUMI Engines ............................................................................................................................261C.2.1 Introduction ............................................................................................................................................. 261

C.2.1.1 Specification Summary .............................................................................................................. 261C.2.2 KASUMI Engine Functional Description ............................................................................................ 261

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C.2.2.1 General Processing ..................................................................................................................... 261C.2.2.2 Examples ...................................................................................................................................... 262

C.3 Packet Processor Programming ............................................................................................... 264C.3.1 Introduction ............................................................................................................................................. 264

C.3.1.1 Purpose ......................................................................................................................................... 264C.3.1.2 Scope ............................................................................................................................................. 264C.3.1.3 Abbreviation and Definitions ................................................................................................... 264C.3.1.4 Data Flow Table .......................................................................................................................... 264

C.3.2 ARC4 Algorithm ..................................................................................................................................... 265C.3.3 AES-CCM for Basic Operations and IPSec Protocols ........................................................................ 266

C.3.3.1 Introduction ................................................................................................................................. 266C.3.3.2 Authentication ............................................................................................................................. 267C.3.3.3 Encryption .................................................................................................................................... 268C.3.3.4 Implementation ........................................................................................................................... 269C.3.3.5 Basic Operation ........................................................................................................................... 270C.3.3.6 ESP ................................................................................................................................................ 276

C.3.4 AES-GMAC/AES-GCM for Basic Operations and IPSec Protocols ............................................... 279C.3.4.1 Introduction ................................................................................................................................. 279C.3.4.2 Basic Operation ........................................................................................................................... 279C.3.4.3 IPSec .............................................................................................................................................. 281

C.3.5 SRTP/SRTCP Protocols ......................................................................................................................... 289C.3.5.1 Introduction ................................................................................................................................. 289C.3.5.2 Packet Format .............................................................................................................................. 289

C.4 Context Control Words ................................................................................................................... 290C.4.0.1 Outbound Processing ................................................................................................................. 292C.4.0.2 Inbound Processing .................................................................................................................... 293

C.4.1 MACsec Protocol .................................................................................................................................... 295C.4.1.1 Introduction ................................................................................................................................. 295C.4.1.2 Packet Format .............................................................................................................................. 296C.4.1.3 Context Control Words .............................................................................................................. 297C.4.1.4 Outbound Processing ................................................................................................................. 299C.4.1.5 Inbound Processing .................................................................................................................... 301

C.4.2 DTLS Protocol ......................................................................................................................................... 303C.4.2.1 Introduction ................................................................................................................................. 303C.4.2.2 Supported Features .................................................................................................................... 303C.4.2.3 Packet Format .............................................................................................................................. 304C.4.2.4 Context Control Words .............................................................................................................. 304C.4.2.5 Outbound Processing ................................................................................................................. 306C.4.2.6 Inbound Processing .................................................................................................................... 309

C.4.3 SSL/TLS Protocol ................................................................................................................................... 312C.4.3.1 Introduction ................................................................................................................................. 312C.4.3.2 Supported Features .................................................................................................................... 313C.4.3.3 Packet Format .............................................................................................................................. 313C.4.3.4 Context Control Words .............................................................................................................. 314C.4.3.5 SSL MAC ...................................................................................................................................... 315

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C.4.3.6 Outbound Processing ................................................................................................................. 316C.4.3.7 Inbound Processing .................................................................................................................... 319

C.5 Public Key Accelerator (PKA) .......................................................................................................322C.5.1 PKA Firmware Architecture Overview ............................................................................................... 322C.5.2 Command and Vector Copy and Zeroization .................................................................................... 324C.5.3 PKI Command Interface ........................................................................................................................ 326C.5.4 Main PKI Command Interface .............................................................................................................. 326

C.5.4.1 Descriptor Ring Management ................................................................................................... 326C.5.4.2 Descriptor Ring Control/Status Words ................................................................................... 326

C.5.5 PKI Command and Result Descriptors ............................................................................................... 332C.5.5.1 Command Descriptor Contents ................................................................................................ 332C.5.5.2 Result Descriptor Contents........................................................................................................ 334C.5.5.3 PKI Command/Result Specifics (Firmware Dependent) ..................................................... 337C.5.5.4 Restrictions on PKA Operations ............................................................................................... 353

C.5.6 PKI Key Decrypt Key Management Interface .................................................................................... 359C.5.6.1 AES Byte Order Example ........................................................................................................... 361C.5.6.2 PKI Key Decrypt Keys Storage (PKI_KDK_0_[0:7] _3_[0:7]) ........................................... 362C.5.6.3 PKI Key Decrypt IVs Storage (PKI_KD_IV_0_[0:3] _3_[0:3]) .......................................... 364C.5.6.4 PKI Key Decrypt CTR Mode Increment Storage (PKI_KD_INCR_0 _3) ....................... 366C.5.6.5 PKI Key Decrypt Key Control Words ...................................................................................... 368

C.5.7 PKI Engine Boot-Up and Internal Error Reporting ........................................................................... 369C.6 Conventions Used in this Manual ................................................................................................370

C.6.1 Register Information .............................................................................................................................. 370

APPENDIX D INLINE PACKET ENGINED.1 Crypto Packet Processor Processing Overview .........................................................................371

D.1.1 Crypto Packet Processor Terms