Tiger Quick Reference - Digital

12/02/02 1

Tiger Quick Reference - Digital

Enhanced signals diagrams and pin maps/layouts

12/02/02 2

• This package is a compilation of detailed information on the Tiger Digital System for diagnosing faults.

• It contains overall and detailed digital diagrams, signal paths, cabling and pin maps.

• It is an addendum to the Tiger Signals Service Documentation CD.

12/02/02 3

Table of Contents

1. Overall Diagram 42. Tester/Testhead Type Definitions 53. TCIO and State Bus Path 94. Clocks 105. Matrix path 116. Calibration path 227. HSD Calibration 248. Digital Power 429. Board-installed Signal Flow 44

10. TJA inputs from HSD 4611. Digital cable diagram 4812. Digital and AC signal card pin outs 5013. THADS Bus 93

Page #

12/02/02 4

Tester ComputerBIF

PCI Slot 3CSB Board949-920-60CSB Slot 1

Splitter Board949-866-00CSB Slot 2

CSB Backplane

TCIO/State Bus

807-425-00

J2 J7 J8 J6

804-257-00

100 MHz Clock

807-426-00

807-426-00

807-426-00

807-426-00

Sync In

807-427-00

807-428-00

To PACS BP #1Slot 8

807-425-00

807-425-00

807-425-00

TJA

807-433-00

807-433-00

807-433-00

807-433-00

To SCSSlot 22TMB #1

DC Measurement System807-442-00

QSB #1949-873-xx

Slot 49

PE32s949-870-xx

Slots 44-48, 50-53

QSB #4949-873-xx

Slot 58

PE32s949-870-xx

Slots 54-57, 59-62

Digital Backplane A 949-881-00

To QSB1, Dig BP A, J1

To QSB2, Dig BP B, J2

To QSB3 Dig BP B, J3











From Analog BPJ16 and J17

J1 J49

TC

IO/S

tate

Bus

100

MH

z C

lock

Sync

In

TJA

HSD

Syn

c O

ut

800

MH

z C

lk

Cal

tree

I/O

Cal

tree

Cal

tree

807-425-00

807-426-00

807-427-00

807-433-00

To TH Control Panel

To Dig BP A, J5 and J8Digital BP B, J6 and J7

807-430-00

807-429-00

807-436-00

J44-J48J50-J53

J11 J13 J4

Mat

rix,

Cal

, DG

S

Mat

rix,

Cal

, DG

S

TC

IO/S

tate

Bus

807-437-00807-434-00

J58

Cal

tree

Cal

tree

I/O

100

MH

z C

lock TJA

Cal

tree

807-430-00

J54-J57J59-J62

ACISB-A949-886-01

Slot 1

Analog BP

J16, J17 J23

807-432-00

807-442-00To DC Measurement System

To DIB Cable807-444-00

To Digital BP BJ12

807-429-00

807-436-00 To Digital BP BJ30 and J39

{807-425-00

807-426-00

807-433-00

From CSB BP, J6

From CSB BP, J2

QSB #2949-873-xx

Slot 39

PE32s949-870-xx

Slots 35-38, 40-43

QSB #3949-873-xx

Slot 30

PE32s949-870-xx

Slots 25-29, 31-34

Digital Backplane B 949-882-00

J2 J39 J35-J38J40-J43

J12 J3 J30 J25-J29J31-J34

TC

IO/S

tate

Bus

807-425-0010

0 M

Hz

Clo

ck807-426-00

TJA

807-433-00{C

altr

ee I

/O807-436-00

Cal

tree

807-429-00

Cal

tree

807-430-00

Mat

rix,

Cal

, DG

S

807-432-00 To Digital BP A J11

807-425-00From CSB BP, J8

TC

IO/S

tate

Bus

Cal

tree

I/O

Cal

tree

807-429-00

807-436-00To Digital BP A

J49 and J58

Cal

tree

807-430-00

100

MH

z C

lock

{ 807-426-00From CSB BP, J2

TJA

807-433-00

10/100 MHzRef. Mod

804-336-00

PPC

LK

100

J14

J2

SUPPORT CABINET

Test Head Digital Backplane A (Quadrants 1 & 4)

Test Head Digital Backplane B (Quadrants 2 & 3)

807-431-00

Overall Diagram

12/02/02 5

Tester/Testhead Type Definitions

During Tiger System power up, the hardware is interrogated in order to determine the “type” of system. A hardware malfunction or cabling problem can cause the system type to be reported as something other than a TIGER.

12/02/02 6

Tester/Testhead Type Definitions:

TESTER:

1. Power is off Tester Empty

2. AD802-02 UB Interface Present Tester A565

3. AD934 MFS HSD50 Tester A5zz

4. LA621 CSB HSD100 Tester Beta (CAT)

5. AD731 VB Cage Interfaceif present: Tester A500if NOT present Tester A520

6. LA866 TIGER Splitter Tester TIGER

7. None of the above (2-6) Tester A510

TESTHEAD:

1. Power is off Testhead Empty

2. AD834 Data Buffer in slot 53 Testhead A500

3. AD667-01 Cal Strobe Buffer Testhead PATH II

4. AD834 Data Buffer in slot 13 Testhead ADV LINEAR

5. AD936 HSD50 Support Board Testhead ADV MIXSIG

6. LA873 QSB in slot 49or

LA886 ACISB in slot 1 Testhead TIGER

7. A510 or A520 - remaining unmapped Testhead A510

TBA

949-824

DIGITAL I/F879-802

Slot 1 UBJ4

J3Terminator

Plug807-358-00 TERMINATOR

879-701-01

J3

800-321-00804-256-00

5V

Messages

1. SYSTEM POWER IS OFF or TERABUS NOT TERMINATED:

If TBA Present:Check that the 5V on the AD701 is present.

(The LED on the AD701 does not mean that the 5V is within spec.) Check the 800-321 & 804-256 Cables.Check the AD701 Terminator Board (879-701

TIGER TEST SYSTEM

2. SYSTEM Registers as A565

Reason: No Digital; “Sees” the AD802, but not the LA866 Splitter.TCIO cable 804-257 problem or the CSB (TCIO Bus A/B to CSB).

Note:Check cable(s) and CSB; review the detailed system configurationand observe what hardware is not recognized.

3. SYSTEM Registers as EMPTY: (May show as a Simulator)

TCIO Problem.Check both TCIO Cables - 807-257 & 807-258.Check the clock cable connecting the LA703 10/100 MHz Ref to the BIF.

See diagram above.

10/100 MHzReference

949-703-00

BIF949-823-01

CSB949-920-xx

J13 J2 J2 J2

804-257-00804-258-00

J3SPLITTER949-866-00

J7 J6

807-428-00

12/02/02 7

4. System is: Failing raw DC power supply and temperature checks; Unable to map the AC channel cards; Mapped as empty.

The TERABUS is cabled incorrectly or the cable is faulty.

Verify the connections of the TERABUS cable and that there is an807-358-00 terminator on J3 of the TBA.

Check the 804-256-00 cable and the 800-321-03 cable.

5. TESTHEAD IS EMPTY

Neither the LA873 QSB in slot 49 or the LA886 ACISB in slot 1 of the testhead can be found.

Check the paths below for the signal path to readback the QSB and ACISB.

Note: Only one of the paths below is needed to recognize the testhead as a “TIGER”.

5V

TBA949-824-xx

TH I/F879-726-00Slot 3 SCS

ACISB-B949-886-00

DIGITAL I/F879-802-00Slot 1 UB

J4

J3Terminator

Plug807-358-00

TERMINATOR879-701-00

J3

800-321-00J4

804-305-00TestheadAnalog

BPJ11

804-256-00

5V

TBA949-824-xx

J4

J3Terminator

Plug807-358-00

TERMINATOR879-701-00

800-321-00804-256-00

5V

10/100 MHzReference

949-703-00

BIF949-823-01

CSB949-920-xx

J13 J2 J2 J2

804-257-00804-258-00

J3SPLITTER949-866-00

J7 J6

807-428-00QSB #1

949-873-xxJ49

TestheadDigitalBP A

J1

807-425-00

12/02/02 8

Paths used to interrogate the Tiger System Configuration

10/100 MHzReference949-703

BIF949-823

CSB949-920

SPLITTER949-866

QSB #1949-873

J49

PE32 orDPE32805-870805-902

J13 J2 J2 J2 J7 J6

807-425-00

807-430-00

807-428-00804-257-00804-258-00

J3

TestheadDigitalBP A

J1

PSB949-671J1

PACS Card Cage

J4B804-305-00

UB Card Cage

J4A804-306-00

800-321-01

TBA

949-824

TH I/F879-726

Slot 3 SCS

ACISB-B949-886

J11

DIGITAL I/F879-802

Slot 1 UB

J4

J3

TerminatorPlug

807-358-00

TERMINATOR879-701

J3

800-321-00 TestheadAnalog

BP

804-256-00

5V

879-791SBE

Analog Test HeadJ19

J20

879-289Data Station

879-289Data Station

TATS Card Cage

SCS Card CageJ3 J4

J1

J1

12/02/02 9

TCIO

Test ComputerBIF

PCI Slot 3J2 J1

TC0STC0DTC1STC1DTC2STC2DTC0RTCIR0TCIR1TC2R0TC2R1DKDK*RCLKRCLK*

804-257-00 Cable

Rows67-72 CSB

State_A (0..14)State_B (0..14)TCIO (0..2)TCIO_R (0..2)TSET_A/BSDAT (A/B)STB (A/B)QUAL (A/B)GMASK (A/B)CLK_100MHZ (A/B)RCLK_100MHZ (A/B)FAIL (A/B)CLRFL (A/B)COND (A/B)ADSS (0..5) (A/B)PWRCL

J6

J8

807-425-00 Cable (x4)

BKPLN

Splitter

Slot 1 Slot 2

State (A/B)(TCIO)

CSB BACKPLANEDigital

Backplane A

Digital Backplane A

Digital Backplane B

Digital Backplane B

1

26

1

26

J1

J4

J2

J3

QSB #1Slot 49

PE32s/AUXSlots 44-48Slots 50-53

QSB #4Slot 58

PE32sSlots 54-57Slots 59-62

QSB #3Slot 30


QSB #2Slot 39


TCIO and STATE BUS to DIGITAL SUBSYSTEM

TESTHEAD

12/02/02 10

CLOCKS

10/100 MHZReferenceModule

J14

804-336-00 Cable

CLKCLK*

CSBSlot 1

807-426-00 Cables

14J2

15

16

17

18

C_CLK_100MHZC_CLK_100MHZ*

J49

J39

J30

J58

QSB #1DigitalBP A

QSB #2DigitalBP B

QSB #3DigitalBP B

QSB #4DigitalBP A





100 MHz 800 MHz

100 MHzQSB #1Slot 49

J49Rows33-34

807-437-00 Cable

DigitalBP A

DigitalBP B

DigitalBP A

DigitalBP B

J5

J8

J6

J7

QSB #1Slot 49

QSB #2Slot 39

QSB #3Slot 30

QSB #4Slot 58





CLK_800MHZ (1..4)

12/02/02 11

Matrix Paths

12/02/02 12

Matrix Pins 2, 46, 47 & 48 to Digital Subsystem

UB BP Slot 2 J3

517-301-xx

Xpt 2 S

Xpt 2 F

Xpt 2 G

Xpt 46 S

Xpt 46 F

Xpt 46 G

Xpt 47 S

Xpt 47 F

Xpt 47 G

Xpt 48 S

Xpt 48 F

Xpt 48 G

UB BP Slot 13 J3517-301-xx

P6

P13

P/O 807-441-00 Cable

P1

P2

P/O 807-442-00 Cable

16

4

5, 17

11B

11A

11C

16

4

5, 17

19

7

8, 20

22

10

11, 23

22B

22A

22C

24B

24A

24C

26B

26A

26C

Support Cabinet Test HeadAnalog BP

J13

J17

J23

P1

16

15

18

22

21

17

20

19

24

23

26

25

P/O 807-431-00 Cable

P2

16

15

18

22

21

17

20

19

24

23

26

25

J13 J11

Test HeadDigital BP A

Xpt 2 S

Xpt 2 F

Xpt 2 G

Xpt 46 S

Xpt 46 F

Xpt 46 G

Xpt 47 S

Xpt 47 F

Xpt 47 G

Xpt 48 S

Xpt 48 F

Xpt 48 G

16

15

18

22

21

17

20

19

24

23

26

25

16

15

18

22

21

17

20

19

24

23

26

25

Xpt 2 S

Xpt 2 F

Xpt 2 G

Xpt 46 S

Xpt 46 F

Xpt 46 G

Xpt 47 S

Xpt 47 F

Xpt 47 G

Xpt 48 S

Xpt 48 F

Xpt 48 G

Backplane Connections

16

15

18

22

21

17

20

19

24

23

26

25

16

15

18

22

21

17

20

19

24

23

26

25

Xpt 2 S

Xpt 2 F

Xpt 2 G

Xpt 46 S

Xpt 46 F

Xpt 46 G

Xpt 47 S

Xpt 47 F

Xpt 47 G

Xpt 48 S

Xpt 48 F

Xpt 48 G

P2

P/O 807-432-00 Cable

J12


Test HeadDigital BP B

16

15

18

17

20

19

22

21

24

23

26

25

16

15

18

17

20

19

22

21

24

23

26

25

P1

16

15

18

17

20

19

22

21

24

23

26

25

TOQSBsPE32sAUX

Xpt 2 S

Xpt 2 F

Xpt 2 G

A9

B-H 9

AA-GG 9; AA-GG 10

Xpt 46 S

Xpt 46 F

Xpt 46 G

A7

B-H 7

AA-GG 7AA-GG 8

QSB (Jxx_P6) *

Xpt 2 S

Xpt 2 F

Xpt 2 G

Xpt 46 S

Xpt 46 F

Xpt 46 G

Xpt 47 S

Xpt 47 F

Xpt 47 G

Xpt 48 S

Xpt 48 F

Xpt 48 G

A13

B-F 13

AA-EE 13AA-EE 14

A11

B-F 11

AA-EE 11AA-EE 12

A15

B-F 15

AA-EE 15AA-EE 16

A17

B-F 17

AA-EE 17AA-EE 18

PE 32 (Jxx_P6) *AUX (Jxx_P6) *

xx = Slot Number

N/Uon

TIGER

12/02/02 13

MATRIX/CALBUS CONNECTIONS BETWEEN TEST HEAD ANALOG BACKPANE AND DIGITAL BACKPLANES

ANALOG BP DIGITAL BP A DIGITAL BP A DIGITAL BP B J23 J13 J11 J12

807-431-00 Cable Backplane 807-432-0 0 CablePin Signal ------------------- Pin Signal Connections Pin Signal ------- Pin Signal1 Alarm ------------------- 1 Alarm ----------------- 1 ALARM* ------- 1 ALARM*2 Alarm Enable ------------------- 2 Alarm Enable ----------------- 2 ALARM_ENABLE* ------- 2 ALARM_ENABLE*3 Bsafety ------------------- 3 Bsafety ----------------- 3 BSAFETY* ------- 3 BSAFETY*4 Shutdown ------------------- 4 Shutdown ----------------- 4 SHUTDOWN* ------- 4 SHUTDOWN*5 ------------------- 5 ----------------- 5 BRD_INSTALLED ------- 5 BRD_INSTALLED6 ------------------- 6 ----------------- 6 ------- 67 System DGS ------------------- 7 System DGS ----------------- 7 DGS ------- 7 DGS8 DGS Shield ------------------- 8 DGS Shield ----------------- 8 AGND ------- 8 AGND9 ------------------- 9 ----------------- 9 DC_CALBUS_HI_F ------- 9 DC_CALBUS_HI_F

10 ------------------- 10 ----------------- 10 DC_CALBUS_HI_S ------- 10 DC_CALBUS_HI_S11 Dig. Cal HS ------------------- 11 Dig. Cal HS ----------------- 11 DC_CALBUS_LO_S ------- 11 DC_CALBUS_LO_S12 Dig. Cal HG ------------------- 12 Dig. Cal HG ----------------- 12 DC_CALBUS_HI_G ------- 12 DC_CALBUS_HI_G13 Dig. Cal HF ------------------- 13 Dig. Cal HF ----------------- 13 DC_CALBUS_LO_G ------- 13 DC_CALBUS_LO_G14 ------------------- 14 ----------------- 14 DC_CALBUS_LO_F ------- 14 DC_CALBUS_LO_F15 Dig. Xpt 2 F ------------------- 15 Dig. Xpt 2 F ----------------- 15 DC_MATRIX_2_F ------- 15 DC_MATRIX_2_F16 Dig. Xpt 2 S ------------------- 16 Dig. Xpt 2 S ----------------- 16 DC_MATRIX_2_S ------- 16 DC_MATRIX_2_S17 Dig. Xpt 46 S ------------------- 17 Dig. Xpt 46 S ----------------- 17 DC_MATRIX_46_S ------- 17 DC_MATRIX_46_S18 Xpt 2 G ------------------- 18 Xpt 2 G ----------------- 18 DC_MATRIX_2_G ------- 18 DC_MATRIX_2_G19 Xpt 46 G ------------------- 19 Xpt 46 G ----------------- 19 DC_MATRIX_46_G ------- 19 DC_MATRIX_46_G20 Dig. Xpt 46 F ------------------- 20 Dig. Xpt 46 F ----------------- 20 DC_MATRIX_46_F ------- 20 DC_MATRIX_46_F21 Dig. Xpt 47 F ------------------- 21 Dig. Xpt 47 F ----------------- 21 DC_MATRIX_47_F ------- 21 DC_MATRIX_47_F22 Dig. Xpt 47 S ------------------- 22 Dig. Xpt 47 S ----------------- 22 DC_MATRIX_47_S ------- 22 DC_MATRIX_47_S23 Dig. Xpt 48 S ------------------- 23 Dig. Xpt 48 S ----------------- 23 DC_MATRIX_48_S ------- 23 DC_MATRIX_48_S24 Xpt 47 G ------------------- 24 Xpt 47 G ----------------- 24 DC_MATRIX_47_G ------- 24 DC_MATRIX_47_G25 Xpt 48 G ------------------- 25 Xpt 48 G ----------------- 25 DC_MATRIX_48_G ------- 25 DC_MATRIX_48_G26 Dig. Xpt 48 F ------------------- 26 Dig. Xpt 48 F ----------------- 26 DC_MATRIX_48_F ------- 26 DC_MATRIX_48_F

12/02/02 14

Matrix Crosspoints Mappingand

Pin Block/Channel Correlation

12/02/02 15

DC Matrix XPT Map (Analog Channel Cards)

Test Head Slot Card Port A Port B DIB Position

1 ACISB-B None None 262 Analog Channel Card XPT 23 XPT 24 273 Analog Channel Card XPT 21 XPT 22 274 Analog Channel Card XPT 19 XPT 20 285 Analog Channel Card XPT 17 XPT 18 286 Analog Channel Card XPT 15 XPT 16 297 Analog Channel Card XPT 13 XPT 14 298 Analog Channel Card XPT 11 XPT 12 309 Analog Channel Card XPT 9 XPT 10 3010 Analog Channel Card XPT 7 XPT 8 3111 Analog Channel Card XPT 5 XPT 6 3114 Analog Channel Card XPT 25 XPT 26 215 Analog Channel Card XPT 27 XPT 28 216 Analog Channel Card XPT 29 XPT 30 317 Analog Channel Card XPT 31 XPT 32 318 Analog Channel Card XPT 33 XPT 34 419 Analog Channel Card XPT 35 XPT 36 420 Analog Channel Card XPT 37 XPT 38 521 Analog Channel Card XPT 39 XPT 40 522 Analog Channel Card XPT 41 XPT 42 623 Analog Channel Card XPT 43 XPT 44 624 ACISB-A None None 1

Digital Crosspoint Connections

Crosspoint Digital Channels2 1-8, 33-40, 65-72,97-104, 129-136, 161-168, 193-200

224-232, 257-264, 289-296, 321-328, 353-360, ……..46 9-16, 41-48, 73-80, 105-112, 137-144, 169-176

201-208, 232-240, 265-272, 297-304, 329-336, 361-368, …..47 17-24, 49-56, 81-88, 113-120, 145-152, 177-184

209-216, 241-248, 273-280, 305-312, 337-344, 369-376, …..48 25-32, 57-64, 89-96, 121-128, 153-160, 185-192

217-224, 249-256, 281-288, 313-320, 345-352, 377-384, …..

12/02/02 16

DIB Header and ChannelCorrelation

Channel Card or Digital ChannelNumber(s)

DIBHeaderCable

DIBHeaderCable

Channel Card or Digital ChannelNumber(s)

ACISB-A J1 J26 ACISB-BChannel Cards 14, 15 J2 J27 Channel Cards 10, 11Channel Cards 16, 17 J3 J28 Channel Cards 8, 9Channel Cards 18, 19 J4 J29 Channel Cards 6, 7Channel Cards 20, 21 J5 J30 Channel Cards 4, 5Channel Cards 22, 23 J6 J31 Channel Cards 2, 3

HCPS 1 J7 J32 HCPS 2QSB 1 J8 J33 QSB 3

129-144 145-160 161-176 J9 J34 545-560 529-544 513-528193-208 209-224 177-192 J10 J35 561-576 593-608 577-592225-240 241-256 1-16 J11 J36 641-656 625-640 609-624

33-48 49-64 17-32 J12 J37 657-672 689-704 673-68865-80 81-96 97-112 J13 J38 737-752 721-736 705-720

897-912 913-928 113-128 J14 J39 753-768 273-288 257-272929-944 945-960 961-976 J15 J40 321-336 305-320 289-304993-1008 1009-1024 977-992 J16 J41 337-352 369-384 353-368769-784 785-800 801-816 J17 J42 417-432 401-416 385-400833-848 849-864 817-832 J18 J43 433-448 465-480 449-464865-880 881-896 J19 J44 497-512 481-496

QSB 4 J20 J45 QSB 2J21 J46J22 J47J23 J48J24 J49

HCPS 3 J25 J50 HCPS 4

12/02/02 17

Test Head Slot and DIB Correlation, Digital and Support BoardSection

THSlot#

Digital Channel orSupport Card

DIBHeaderCable

DIBHeaderCable

Digital Channel orSupport Card

THSlot #

44 HCPS 1 J7 J32 2545 129-144 145-160 J9 J34 529-544 513-528 2646 161-176 177-192 J9 & J10 J34 & J35 561-576 545-560 2747 193-208 209-224 J10 J35 593-608 577-592 2848 225-240 241-256 J11 J36 625-640 609-624 2949 QSB 1 J8 J33 QSB 3 3050 1-16 17-32 J11 & J12 J36 & J37 657-672 641-656 3151 33-48 49-64 J12 J37 689-704 673-688 3252 65-80 81-96 J13 J38 721-736 705-720 3353 97-112 113-128 J13 & J14 J38 & J39 753-768 737-752 3454 897-912 913-928 J14 J39 273-288 257-272 3555 929-944 945-960 J15 J40 305-320 289-304 3656 961-976 977-992 J15 & J16 J40 & J41 337-352 321-336 3757 993-1008 1009-1024 J16 J41 369-384 353-368 3858 QSB 4 J20 J45 QSB 2 3959 769-784 785-800 J17 J42 401-416 385-400 4060 801-816 817-832 J17 & J18 J42 & J43 433-448 417-432 4161 833-848 881-896 J18 J43 465-480 449-464 42

865-880 881-896 J19 J44 497-512 481-49662HCPS 3 J25 J50 HCPS 4

43

12/02/02 18

ABCD

38 35 25 23 13 11 1

J11

J12

J13

CABLEPE32 Card 48(Channels 225-256)

PE32 Card 50(Channels 1-32)



PE32 Card 53(Channels 97-128,up to 112 shown)

Arrangement of digital channels, by DIB Header (DIB left, view from DUT side)

12/02/02 19

Signal and DGS on Left in Blocks (view from DUT side)

DigitalChannel

THSlot

DIBConn

PogoPad

1 50 J11 A92 50 J11 C93 50 J11 B84 50 J11 D85 50 J11 A76 50 J11 C77 50 J11 B68 50 J11 D69 50 J11 A510 50 J11 C511 50 J11 B412 50 J11 D413 50 J11 A314 50 J11 C315 50 J11 B216 50 J11 D2

Digital Channels (1-16) Locations on the DIB

ABCD

38 35 25 23 13 11 1

Signal

DGS (DUT_DGS)

38 35 25 23 13 11 1

12/02/02 20

ACISB-A ACISB-BA B C D

1 DGnd DGnd DGnd User +12V2 DGnd DGnd DGnd User –30V3 DGnd DGnd DGnd User +30V4 DGnd DGnd DGnd User –15V5 DGnd DGnd DGnd User –5V6 DGnd DGnd DGnd User -5V7 DGnd DGnd DGnd User +15V8 DGnd DGnd DGnd User +5V9 DGnd DGnd DGnd User +5V10 DGnd DGnd DGnd11 DGnd DGnd DGnd DGnd12 Pass Thru 4 Pass Thru 3 Pass Thru 2 Pass Thru 113 Matrix 28G SDB 37 SDB 25 Matrix 32G14 Matrix 28S SDB 38 SDB 26 Matrix 32S15 Matrix 28F SDB 39 SDB 27 Matrix 32F16 Matrix 27G SDB 40 SDB 28 Matrix 31G17 Matrix 27S SDB 41 SDB 29 Matrix 31S18 Matrix 27F SDB 42 SDB 30 Matrix 31F19 Matrix 26G SDB 43 SDB 31 Matrix 30G20 Matrix 26S SDB 44 SDB 32 Matrix 30S21 Matrix 26F SDB 45 SDB 33 Matrix 30F22 Matrix 25G SDB 46 SDB 34 Matrix 29G23 Matrix 25S SDB 47 SDB 35 Matrix 29S24 Matrix 25F SDB 48 SDB 36 Matrix 29F25 Matrix 44F Matrix 44S Matrix 36S Matrix 36F26 Matrix 43F Matrix 43S Matrix 35S Matrix 35F27 Matrix 42F Matrix 42S Matrix 34S Matrix 34F28 Matrix 41F Matrix 41S Matrix 33S Matrix 33F29 Matrix 48F Matrix 48S Matrix 40S Matrix 40F30 Matrix 47F Matrix 47S Matrix 39S Matrix 39F31 Matrix 46F Matrix 46S Matrix 38S Matrix 38F32 Matrix 45F Matrix 45S Matrix 37S Matrix 37F33 DUT Src 5G DUT Src 6G DUT Src 7G DUT Src 8G34 DUT Src 5S DUT Src 6S DUT Src 7S DUT Src 8S35 DUT Src 5F DUT Src 6F DUT Src 7F DUT Src 8F36

A B C D1 User +12V2 DGnd DGnd DGnd User –30V3 DGnd DGnd DGnd User +30V4 DGnd DGnd DGnd User –15V5 DGnd DGnd DGnd User –5V6 DGnd DGnd DGnd User -5V7 Pass Thru 3 Pass Thru 2 Pass Thru 1 User +15V8 SDB 1 SDB 2 SDB 3 User +5V9 SDB4 SDB5 SDB6 User +5V10 Matrix 4G SDB7 SDB8 Matrix 8G11 Matrix 4S SDB9 SDB10 Matrix 8S12 Matrix 4F SDB11 SDB12 Matrix 8F13 Matrix 3G SDB13 SDB14 Matrix 7G14 Matrix 3S SDB15 SDB16 Matrix 7S15 Matrix 3F SDB17 SDB18 Matrix 7F16 Matrix 2G SDB19 SDB20 Matrix 6G17 Matrix 2S SDB21 Ser 23 Matrix 6S18 Matrix 2F SDB22 Ser 22 Matrix 6F19 Matrix 1G SDB23 Ser 21 Matrix 5G20 Matrix 1 S SDB24 Ser 20 Matrix 5S21 Matrix 1F PROM data PROM clk Matrix 5F22 Matrix 20F Matrix 20S Matrix 12S Matrix 12F23 Matrix 19F Matrix 19S Matrix 11S Matrix 11F24 Matrix 18F Matrix 18S Matrix 10S Matrix 10F25 Matrix 17F Matrix 17S Matrix 9S Matrix 9F26 Matrix 24F Matrix 24S Matrix 16S Matrix 16F27 Matrix 23F Matrix 23S Matrix 15S Matrix 15F28 Matrix 22F Matrix 22S Matrix 14S Matrix 14F29 Matrix 21F Matrix 21S Matrix 13S Matrix 13F30 DUT Src 3G ID +5V User Alarm In DUT Src 4G31 DUT Src 3S Appsdata Shutdown* DUT Src 4S32 DUT Src 3F Reldata DGS 1 DUT Src 4F33 DUT Src 1G Relclk DGS 1 Shld DUT Src 2G34 DUT Src 1F DUT Src 1S DUT Src 2S DUT Src 2F35 Safety* Wave Hi Wave Lo Wave G

(gnd36 Tip Shld User Clk Sh Trig Out Shld Trig In shld37 Tip* User Clk Trig Out Trig In

ABCD

38 1

J1ACISB-A

J26ACISB-B

1 38

DCBA

12/02/02 21

DIGITAL TEST HEAD BOARD/SLOT/ID/SMC NODE CHART.

DIGITAL BACKPLANE B DIGITAL BACKPLANE ASLOT BOARD TYPE BSID SMC

NODESLOT BOARD TYPE BSID SMC NODE

25 AUX 81 (101 0001) 82 44 AUX 69 (100 0101) 7026 PE32: Ch. 513-544 16 (001 0000) 17 45 PE32: Ch. 129-160 4 (000 0100) 527 PE32: Ch. 545-576 17 (001 0001) 18 46 PE32: Ch. 161-192 5 (000 0101) 628 PE32: Ch. 577-608 18 (001 0010) 19 47 PE32: Ch. 193-224 6 (000 0110) 729 PE32: Ch. 609-640 19 (001 0011) 20 48 PE32: Ch. 225-256 7 (000 0111) 830 QSB #3 80 (101 0000) 81 49 QSB #1 64 (100 0000) 6531 PE32: Ch. 641-672 20 (001 0100) 21 50 PE32: Ch. 1-32 0 (000 0000) 132 PE32: Ch. 673-704 21 (001 0101) 22 51 PE32: Ch. 33-64 1 (000 0001) 233 PE32: Ch. 705-736 22 (001 0110) 23 52 PE32: Ch. 65-96 2 (000 0010) 334 PE32: Ch. 737-768 23 (001 0111) 24 53 PE32: Ch. 97-128 3 (000 0011) 435 PE32: Ch. 257-288 8 (000 1000) 9 54 PE32: Ch. 897-928 28 (001 1100) 2936 PE32: Ch. 289-320 9 (000 1001) 10 55 PE32: Ch. 929-960 29 (001 1101) 3037 PE32: Ch. 321-352 10 (000 1010) 11 56 PE32: Ch. 961-992 30 (001 1110) 3138 PE32: Ch. 353-384 11 (000 1011) 12 57 PE32: Ch. 993-1024 31 (001 1111) 3239 QSB #2 72 (100 1000) 73 58 QSB #4 88 (101 1000) 8940 PE32: Ch. 385-416 12 (000 1100) 13 59 PE32: Ch. 769-800 24 (001 1000) 2541 PE32: Ch. 417-448 13 (000 1101) 14 60 PE32: Ch. 801-832 25 (001 1001) 2642 PE32: Ch. 449-480 14 (000 1110) 15 61 PE32: Ch. 833-864 26 (001 1010) 2743 PE32: Ch. 481-512 15 (000 1111) 16 62 PE32: Ch. 865-896 27 (001 1011) 28

12/02/02 22

Calibration Paths

12/02/02 23

Mainframe UB Backplane

CAL LGCAL LSCAL LFCAL HGCAL HSCAL HF

J23

Dig. Cal. HSenseDig. Cal. HGuardDig. Cal. HForce

Testhead Digital Backplane AJ13

807-441-00 Cable

807-431-00 Cable

QSB #1Slot 49

QSB #4Slot 58

Testhead Digital Backplane B

QSB #2Slot 39

QSB #3Slot 30

J11J12

DC_CALBUS_HI_FDC_CALBUS_HI_SDC_CALBUS_LO_SDC_CALBUS_HI_GDC_CALBUS_LO_GDC_CALBUS_LO_F

807-432-00 Cable

J49J58J39J30

Q_C

AL

TR

EE

_IN

(1)

Q_C

AL

TR

EE

_IN

(4)

Q_C

AL

TR

EE

_IN

(2)

Q_C

AL

TR

EE

_IN

(3)

Row

s 38

-40

Row

s 38

-40

Row

s 38

-40

Row

s 38

-40

807-429-00 Cable

Row

26

807-436-00 Cable

Row

26

Row

26

Row

26

Q_C

AL

RT

N_I

N(3

)

Q_C

AL

RT

N_I

N(2

)

Q_C

AL

RT

N_I

N(4

)

Q_C

AL

RT

N_I

N(1

)

PE32Slot 48

PE32Slot 47

PE32Slot 52

PE32Slot 51

PE32Slot 45

AUXSlot 44

PE32Slot 46

PE32Slot 53

PE32Slot 50

Row

s 41

-45

807-430-00 CablesSignals: P_CAL_TREE(1…9)PE32

Slot 59

PE32Slot 60

PE32Slot 55

PE32Slot 56

PE32Slot 62

PE32Slot 61

PE32Slot 54

PE32Slot 57

PE32Slot 40

PE32Slot 41

PE32Slot 36

PE32Slot 37

PE32Slot 43

PE32Slot 42

PE32Slot 35

PE32Slot 38

PE32Slot 29

PE32Slot 28

PE32Slot 33

PE32Slot 32

PE32Slot 26

AUXSlot 25

PE32Slot 27

PE32Slot 34

PE32Slot 31

Row

s 41

-45

Row

s 41

-45

Row

s 41

-45

1

1

1

11

1

1

11

1

1

1

1

1

1

1

1 1

1

1

11

1

1

1 1

1

1

11

1

1

1

1

UB ASYSlot 21 J3 J13

Tes

thea

d A

nalo

g B

ackp

lane

CALIBRATION SIGNALS

12/02/02 24

Tiger HSD Calibration

12/02/02 25

REF_DRV_EDGE

REF_DRV_EDGE*QSB TG GENERATOR

REFERENCE DRIVERAND COMPARATOR

REF_DRV_OUT

REF_DRV_OUT*

REF_CMP_OUT

REF_CMP_OUT*

REF_CMP_IN

QSB CALTREE

(DRIVER/COMPARATORINTERFACE)

REF_CMP_IN

REF_CMP_OUT

REF_CMP_OUT*

Levels for ReferenceComparator

ICAL_IN_OUT

Q_CALTREE_IN<4..1>

ACISB1_CALTREE_IN

ACISB2_CALTREE_IN

TDR_VMEAS

CALTREE_DUT

(QSB 1 SECTION)

Q_CALTREE_OUTP_CALTREE<9..1>

(QSB SECTION)

(CONTROL SECTION)

QSB - REFERENCE DRIVER/COMPARATOR & CALTREE

DC_MATRIX_46_F

DC_MATRIX_46_S

DC_MATRIX_46_G

ACISB_CALBUS_HI_F

ACISB_CALBUS_HI_S

ACISB_CALBUS_HI_G

V_ICAL_OUT

THALOG

VBIAS

QSB PPMUSUPPORT

TDR_VMEAS ICAL_IN_OUT(BOARD

CONTROLAND

CONNECTIONS)

QSB THI

(PPMUSUPPORT)

P_PPMU_OUT<8..1> (PE32 Input)

P_PPMU_REF<8..1> (PE32 Input)

QSB - THI & PPMU SUPPORT

REF_DRV_OUT

REF_DRV_OUT*

ICAL_IN_OUT

REF_CMP_IN

CALTREE_DUT

DRV_CMP_ICAL_CALTREE

CALTREE_DUT_OUT

DRV_CMP_CALTREE

12/02/02 26


Q_CALTREE_1_4

Q_CALTREE_MISC

Q_CALTREE_1_2

Q_CALTREE_3_4

CALTREE_ACISB_1_2

CALTREE_TDRVMEAS

Q_CALTREE_IN<1>

Q_CALTREE_IN<2>

Q_CALTREE_IN<3>

Q_CALTREE_IN<4>

ACISB1_CALTREE_IN

ACISB2_CALTREE_IN

TDR_VMEAS

CALTREE - QUADRANT RELAYS (QSB)

CALTREE_OUT

P_CALTREE_LOW

P_CALTREE_HIGH

P_CALTREE_1_4

P_CALTREE_5_8

P_CALTREE_9_12

P_CALTREE_1_2

P_CALTREE_3_4

P_CALTREE_5_6

P_CALTREE_7_8

P_CALTREE_9_OPEN

P_CALTREE_50_GND

P_CALTREE<1>

P_CALTREE<2>

P_CALTREE<3>

P_CALTREE<4>

P_CALTREE<5>

P_CALTREE<6>

P_CALTREE<7>

P_CALTREE<8>

P_CALTREE<9>

TP101

R49.9

CALTREE - PE RELAYS (QSB)

12/02/02 27

CAL<0>

CAL<1>

CAL<2>

CAL<3>

CAL<4>

CAL<5>

CAL<6>

CAL<7>

CAL<8>

CAL<9>

CAL<10>

CAL<11>

CAL<12>

CAL<13>

CAL<14>

CAL<15>

CAL<16>

CAL<17>

CAL<18>

CAL<19>

CAL<20>

CAL<21>

CAL<22>

CAL<23>

CAL<24>

CAL<25>

CAL<26>

CAL<27>

CAL<28>

CAL<29>

CAL<30>

CAL<31>

CAL_1_0

CAL_3_2

CAL_5_4

CAL_7_6

CAL_9_8

CAL_11_10

CAL_13_12

CAL_15_14

CAL_17_16

CAL_19_18

CAL_21_20

CAL_23_22

CAL_25_24

CAL_27_26

CAL_29_28

CAL_31_30

CAL_3_0

CAL_7_4

CAL_11_8

CAL_15_12

CAL_19_16

CAL_23_20

CAL_27_24

CAL_31_28

CAL_7_0

CAL_15_8

CAL_23_16

CAL_31_24

CALTREE_OUT

CAL_15_0

CAL_31_16

QSB_CALTREE_COAX(from QSB)

CALTREE RELAYS (PE32)

12/02/02 28

V_ICAL_OUT

THALOG

VBIAS

SYSTEM_DGS

P_PPMU_OUT<4>

P_PPMU_OUT<3>

P_PPMU_OUT<2>

P_PPMU_OUT<1>

Q_DGS

Q_DGS

Q_DGS

P_PPMU_REF<4>

P_PPMU_REF<3>

P_PPMU_REF<2>

P_PPMU_REF<1>

QSB_DUT_DGS

P_PPMU_OUT<8>

P_PPMU_OUT<7>

P_PPMU_OUT<6>

P_PPMU_OUT<5>

Q_DGS

Q_DGS

Q_DGS

P_PPMU_REF<8>

P_PPMU_REF<7>

P_PPMU_REF<6>

P_PPMU_REF<5>

S8

S7

S6

S5

S4

S3

S2

S1

S8

S7

S6

S5

S4

S3

S2

S1

S8

S7

S6

S5

S4

S3

S2

S1

S8

S7

S6

S5

S4

S3

S2

S1 A0 A1 A2

A0 A1 A2

A0 A1 A2

A0 A1 A2

+

-

+

-

-+

ADC_SIG1

ADC_REF1

THI1_ADC_IN

+

-

+

-

-+

ADC_SIG2

ADC_REF2

THI2_ADC_IN THI2 ADC SDATA

THI1 ADC SDATA

THI1_ADC_MUX_SEL<0>

THI1_ADC_MUX_SEL<1>

THI1_ADC_MUX_SEL<2>

THI2_ADC_MUX_SEL<0>

THI2_ADC_MUX_SEL<1>

THI2_ADC_MUX_SEL<2>

A/D

A/D

P15VA

10VREG

10V A/D REFERENCE

P10VREF

10VREG

P10VREF

THI1_ADC_BUSY

THI1_ADC_SCLK

THI2_ADC_BUSY

THI2_ADC_SCLK

To THI1

To THI2

QSB THI CONNECTIONS - ANALOG MUXES - ADC

12/02/02 29

CAL_IND < >

KP

DCL_OUT < > CHOUT

KDUT

DOUT < >

CAL < >CHAN_TEE < >

Vih

Vil

Voh

Vol

KF

KA

DOUT_ALARM < >

ALARM < >

KPPMU

PPMU_CH < >

KMF

DC_MTX_F <3..0>

R301K

Vppmu

PPMU Meas Out FALCON DCL AND CHANNEL RELAYS (PE32)

LOAD CTRL

Iol

Ioh

VCP

Comp Out

Comp Out

FAILLOGIC

Vclh

Vcll

12/02/02 30

Vih

Vil

Voh

Vol

LOAD CTRL

Iol

Ioh

VCP

Comp Out

Comp Out

KF KDUT

(clo

sed)

301K

PPMU Calibration Path (PE32)

CAL

PPMU

DC MTX FORCE

ALARM

KPPMU

KMF

KA

CH. DATA INPUT

12/02/02 31

40

1K

10K

100K

40

1K

10K

100K

TDR_VMEAS

V_ICAL_OUT

DC_MATRIX_46_F

DC_MATRIX_46_S

ICAL_IN_OUT

ACISB_CALBUS_HI_F

ACISB_CALBUS_HI_S

VBIAS

THALOG

-15VA +15VA

-15VA +15VA

PPMU - CURENT CALIBRATION CIRCUIT (QSB)

LJC MATRIX

12/02/02 32

Vih

Vil

Driver

Vclh

Vcll

Voh

Vol

RALARM

DYNAMICLOAD

Ioh Iol

Vcp

PPMU

CAL

DUT_ALARM

FUNCTIONAL DUT

PARAMETRIC

PPMU

DC_FORCE

DC_SENSE

PE Board QSB

MUX MATRIX

DC SUBSYSTEM

Vih, Vil, Voh, Vol Calibration, PPMU Calibration

DCMS

12/02/02 33

KfKdut

Kp

Kppmu1

Vppmu

PPMU 1

PPMU 2

PPMU 32

System Voltmeter

PPMU MEAS OUT

MUX SEL

1

32

Kppmu2

Kppmu32

DGS

DGS Oct 1

DGS Oct 2

PPMU Meas 1

PPMU Meas 2

MUX

Oct & Bd SELECT

Gain andLevel Shift

DATA OUTA/D

QSB A/D Calibration - Voltmeter

949-873QSB

CALTREE

949-873QSB


J12

J11


807-432-00 J13


J23

Test HeadAnalog BP

807-431-00J13

J17

Xpt 2

Xpt 46 - 48

807-441-00

807-442-00

UB BPSlot 2

517-301

UB BPSlot 13517-301

DGSTATS Card Cage

A/D

PE32

Kmf

Kms

DRV

Kmd

V/I SourceS1

(UBVI)

F

S

XPT depends uponDigital Channel(2,46,47 or 48)

CMP

CMP

12/02/02 34

KfKdut

Kp

Kms

Matrix Sense

Kppmu1

Vppmu

PPMU 1

PPMU 2

PPMU 32

System Voltmeter

PPMU MEAS OUT

MUX SEL

1

32

Kppmu2

Kppmu32

DGS

DGS Oct 1

DGS Oct 2

PPMU Meas 1

PPMU Meas 2

MUX

Oct & Bd SELECT

Gain andLevel Shift

DATA OUTA/D

Vih/Vil Calibration

949-873QSB

CALTREE

949-873QSB

Matrix Sense


J12

J11


807-432-00 J13


J23

Test HeadAnalog BP

807-431-00J13

J17

Xpt 2

Xpt 46 - 48

807-441-00

807-442-00

UB BPSlot 2

517-301

UB BPSlot 13517-301

DGSTATS Card Cage

A/D

Kmf

PE32

DRV

Vih

Vil

CMP

CMP

12/02/02 35

KfKdut

Kp

Kms

Matrix Sense

Kppmu1

Vppmu

PPMU 1

PPMU 2

PPMU 32

System Voltmeter

PPMU MEAS OUT

MUX SEL

1

32

Kppmu2

Kppmu32

DGS

DGS Oct 1

DGS Oct 2

PPMU Meas 1

PPMU Meas 2

MUX

Oct & Bd SELECT

Gain andLevel Shift

DATA OUTA/D

Voh/Vol Calibration

949-873QSB

CALTREE

949-873QSB

Matrix Sense


J12

J11


807-432-00J13


J23

Test HeadAnalog BP

807-431-00J13

J17

Xpt 2

Xpt 46 - 48

807-441-00

807-442-00

UB BPSlot 2

517-301

UB BPSlot 13517-301

DGSTATS Card Cage

A/D

Kmf

PE32

DRV

Vih

Vil

Voh

VolCMP

CMP

12/02/02 36

KfKdut

Kp

Kms

Matrix Sense

Kppmu1

Vppmu

PPMU 1

PPMU 2

PPMU 32

System Voltmeter

PPMU MEAS OUT

MUX SEL

1

32

Kppmu2

Kppmu32

DGS

DGS Oct 1

DGS Oct 2

PPMU Meas 1

PPMU Meas 2

MUX

Oct & Bd SELECT

Gain andLevel Shift

DATA OUTA/D

Vclh/Vcll Calibration

949-873QSB

CALTREE

949-873QSB

Matrix Sense


J12

J11


807-432-00 J13


J23

Test HeadAnalog BP

807-431-00J13

J17

Xpt 2

Xpt 46 - 48

807-441-00

807-442-00

UB BPSlot 2

517-301

UB BPSlot 13517-301

DGSTATS Card Cage

A/D

Kmf

PE32

DRV

Vclh

Vcll

I=+/-

CMP

CMP

12/02/02 37

KfKdut

Kp

Kms

Matrix Sense

Kppmu1

Vppmu

PPMU 1

PPMU 2

PPMU 32

System Voltmeter

PPMU MEAS OUT

MUX SEL

1

32

Kppmu2

Kppmu32

DGS

DGS Oct 1

DGS Oct 2

PPMU Meas 1

PPMU Meas 2

MUX

Oct & Bd SELECT

Gain andLevel Shift

DATA OUTA/D

Vcp Calibration

949-873QSB

CALTREE

949-873QSB

Matrix Sense


J12

J11


807-432-00 J13


J23

Test HeadAnalog BP

807-431-00J13

J17

Xpt 2

Xpt 46 - 48

807-441-00

807-442-00

UB BPSlot 2

517-301

UB BPSlot 13517-301

DGSTATS Card Cage

A/D

Kmf

PE32

DRV

I=0mA

Vcp

Iol=xmA

Ioh=xmA

CMP

CMP

12/02/02 38

Kf Kp

Ioh/Iol Calibration

PE32

DRV

VcpIol

Ioh

PE CALTREE

OtherChannels

PERELAYSOther

PE32s

QSBRELAYS

OtherQSBs

40

1K

10K

100K

40

1K

10K

100K

DGS

DGS+2.5V

+

-MUX A/D

QSB #1

CMP

CMP

12/02/02 39

DRV_TG

Reference Driver Edge

TRIG

TRIG

Measure Me

TCMU Enable

STB

TREF

TREF

Comp Latch

EXT_DRV_TG

HSD_SYNC_OUT

Griffinand

ARKand

Logic

SDAT

Cal Return

Other Cal

Returns

Vector

Data

QSB1

Front

End

MPC

MissingEdgeLatch

TCMUand

ADC

TMS

ACISB

ADC

Control

Data

Cntrl

DIB

PPMU

ReferenceComparator

ReferenceDriver

Misc.

ACISB1

ACISB2

PPMU(Cal Resistors)

R R

QSBSelect(x2)

PESelect(x4)

PE9

Open

Short

50 OhmLoad

R

PECaltreeRelays

PPMURelay

MConRelay

DUT ConRelay

FunConRelay

User Scope Sync

VIH

VIL

VOH

VOL

Driver

Z ClampsVCH

VCL

FromQSB

throughDACs

VT

DE

DP

GVOH

LVOL

CH

CL

Fixed NegProt Clamp

Fixed PosProt Clamp

DataFormatter

GVOH

LVOL

DIBExternal

Instruments

Trim

EDGE PLACEMENT CALIBRATION

DrivePolarityLogic

DH/DLVerniers

DH/DL

MUXLogic

GVOH/LVOLPulse Width

Adjust

Compare DataCal Return

Format

DH/DLa/b

LinearizationRAM

DH/DLPrecondition

EventSteering

Logic

DH a/b

EventCells

EventCellData

Edge Type

Edge TimingPer PinDeskew

I/OFormat

IOL

IOH

PE32

QSB

DH Edge being compared by the GVOH comparator and the comparesignal measured by the TCMU (Timing Calibration Measurement Unit).The path starts at the Per Pin Deskew adjustment, running thru the Event Logic, Precondition, and Linearization RAM. Then it goes into the EG4,thru the DH verniers, Drive Polarity, and out the Data Formatter as DP.Next is the FALCON, where DP goes into the Driver, swinging back thruthe comparator in to the Mux Logic on the EG4. Then the Pulse Width Adjustment is applied and the Compare Data path is taken onto the Cal Return,which brings us to QSB1, into the ARK and many muxes. The path proceedsthru Measure ME to the Front End and finally into the TCMU.

12/02/02 40

Per PinAdj.

EventLogic

DH/DLPrecondition

LinearizationRAM

EdgeTiming

EventData DH a/b

DH/DLVerniers

DrivePolarityLogic

DataFormatter

DH/DLa/b

DH/DLDP

EG4 (QSB)

MUXLogic

GVOH/LVOLPulse Width

Adjust

CAL ReturnFormat

IOL

IOH

Vcp

DE

DP

VIH

VIL

GVOH

LVOL

VOH

VOL

Trim

FunConRelay

DUT ConRelay

MConRelay

PPMURelay

PE CaltreeRelays

PE32

R RADCCTRL

MPC

MissingEdgeLatch

TCMU&

ADC

Data

CNTRL

FrontEnd

DRV_TG

Reference Driver Edge

TRIG

TRIG

Measure ME

TCMU Enable

STB

TREF

TREF

Comp Latch

EXT_DRV_TG

HSD_SYNC_OUT

Griffinand

ARKand

Logic

User Scope Sync

FromQSBthruDACs

FromQSBthruDACs

SDAT

Vector Data

CAL RETURN

Other Cal Returns

QSB 1

DIBExternal

Instruments

TMS

ACISB

DIB

PPMU

ACISB1

ACISB2

PE9

Open

50 OhmLoad

Short

QSB

R

PESelect(x4)

QSBSelect(x2)

Misc.

ReferenceDriver

ReferenceComparator

DH EDGECalibration

12/02/02 41

REF_DRV_OUT

REF_DRV_OUT*

ICAL_IN_OUT

REF_CMP_IN

CALTREE_DUT


Q_CALTREE_1_4

Q_CLATREE_MISC

Q_CALTREE_1_2

Q_CALTREE_3_4

CALTREE_ACISB_1_2

CALTREE_TDRMEAS

Q_CALTREE_IN<1>

Q_CALTREE_IN<2>

Q_CALTREE_IN<3>

Q_CALTREE_IN<4>

ACISB1_CALTREE_IN

ACISB2_CALTREE_IN

TDR_VMEAS

To OtherQSBs via

807-429-00QSB to QSB,

Cal. Cable CALTREE_OUT

P_CALTREE_LOW

P_CALTREE_HIGH

P_CALTREE_1_4

P_CALTREE_5_8

P_CALTREE_9_12

P_CALTREE_1_2

P_CALTREE_3_4

P_CALTREE_5_6

P_CALTREE_7_8

P_CALTREE_9_OPEN

P_CALTREE_50_GND

P_CALTREE<1>

P_CALTREE<2>

P_CALTREE<3>

P_CALTREE<4>

P_CALTREE<5>

P_CALTREE<6>

P_CALTREE<7>

P_CALTREE<8>

P_CALTREE<9>

TP101

49.9Ohms

To PE32svia

807-430-00QSB to PE32CALTREE

Cable

QSB_CALTREE_COAX

CALTREE_OUT

CAL<0>

CAL<1>

CAL<2>

CAL<3>

CAL<4>

CAL<5>

CAL<6>

CAL<7>

CAL<8>

CAL<9>

CAL<10>

CAL<12>

CAL<13>

CAL<14>

CAL<15>

CAL<16>

CAL<17>

CAL<18>

CAL<19>

CAL<20>

CAL<21>

CAL<22>

CAL<23>

CAL<24>

CAL<25>

CAL<26>

CAL<27>

CAL<28>

CAL<29>

CAL<30>

CAL<11>

CAL<31>

CAL_15_0

CAL_31_16

CAL_7_0

CAL_15_8

CAL_23_16

CAL_31_24

CAL_3_0

CAL_7_4

CAL_11_8

CAL_15_12

CAL_19_16

CAL_23_20

CAL_27_24

CAL_31_28

CAL_1_0

CAL_3_2

CAL_5_4

CAL_7_6

CAL_9_8

CAL_11_10

CAL_13_12

CAL_15_14

CAL_17_16

CAL_19_18

CAL_21_20

CAL_23_22

CAL_25_24

CAL_27_26

CAL_29_28

CAL_31_30

KF KDUT

KP

CAL

Matrix Sense

KMF

KPPMU1

Vppmu

PPMU 1

PPMU 2

PPMU 32

KPPMU2

KPPMU32

PPMU MEAS OUT 1

32

MUX SEL

DGS

J12

J11

J13

J23

J13

J17

807-432-00 807-431-00 807-441-00

807-442-00

UB BPSlot 2

517-301

UB BPSlot 13

517-301




Test HeadAnalog BP

A/D

DGS

PPMU Meas 1

DGS Oct 1

MUX

PPMU Meas 2

DGS Oct 2

Gain andLevel Shifter

A/D

Oct & Bd Select 949-873QSB

TATS Card Cage

QSB

PE32

12/02/02 42

Digital Power

12/02/02 43

* The 0.8v is developed as 3.3 - 2.5V

DigitalPowerSupplies

-2.0V+0.8V**-2.5V**-3.6V-5.2V3.3V**

AnalogPowerSupplies

+5.0V+10V-5.0V

DPE32

** The 3.3V is developed as -2.5V + 0.8V

+15V

-10V

FRMQSB

TestheadDigital

Backplane BJ20

PE32s(SMC Node)

TestheadDigital

Backplane A

P5J19

QSBs(SMC Node)

PE32s(SMC Node)

P4

QSBs(SMC Node)

SMC PWR SUPPLY(On top of PDU)

405-223-00+24V

807-477-00 CableSupportCabinet

Node

J24

P/O807-440-01

CableP1

+/- 5V & +/- 5V RTNJ20+24V

P2

MAP-110Power Supply

405-376-00+ 5V

P/O807-476-00

CableP2

SYSNODEP3

+5V SYS NODEJ-PWR

(Located in top BAY 1)

866-156-00CableP1 P2 J10

System NodeFront Panel

J10 804-182-00Cable JC-

LON24V / LON

CDUNODE

CDU CABINET

P1 P2

48VDC

807-423-00

807-423-00

807-423-00

807-423-00

PDUSide

PanelDC1-DC4

TestheadDigital

BackplaneA & BBusbar

48VDC Busbar


-2.5V*+0.8V*-5.2V-2.0V+5.0V-3.6V3.3V*

AnalogPowerSupplies

+15V-15V-10V+15V

QSB


-2.0V+0.8V*-2.5V*-3.6V-5.2V3.3V*

AnalogPowerSupplies

+5.0V+10V-5.0V

PE32

+15V

-10V

DC VOLTAGES TO THE TESTHEAD DIGITAL BACKPLANE AND DIGITAL BOARDS

12/02/02 44

Board Installed Signal Flow

12/02/02 45

ONCDU

P6

P7

BD_INST_I

P3

4

5

BDS_IN_C

BDS_IN_M

3

3

JC-TH

P/O807-440-01

Cable

3

3

J10

J9

BD_INST_I

J26…J27...J28 J31...J32...J33 J36..J37..J38 J40..J41..J42

1

2

3

4

5

6

7

8

J25_PFILL

J25

AUX

1

2

3

4

5

6

7

8

J29_PFILL

J29

PE32

1

2

3

4

5

6

7

8

J30_PFILL

J30

QSB #3

1

2

3

4

5

6

7

8

J34_PFILL

J34

PE32

1

2

3

4

5

6

7

8

J35_PFILL

J35

PE32

1

2

3

4

5

6

7

8

J39_PFILL

J39

QSB #2

1

2

3

4

5

6

7

8

J43_PFILL

J43

PE32

J46...J47...J48 J50...J51...J52 J55...J56...J57 J59...J60...J61

1

2

3

4

5

6

7

8

J44_PFILL

J44

AUX

1

2

3

4

5

6

7

8

J45_PFILL

J45

PE32

1

2

3

4

5

6

7

8

J49_PFILL

J49

QSB #1

1

2

3

4

5

6

7

8

J53_PFILL

J53

PE32

1

2

3

4

5

6

7

8

J54_PFILL

J54

PE32

1

2

3

4

5

6

7

8

J58_PFILL

J58

QSB #4

1

2

3

4

5

6

7

8

J62_PFILL

J62

PE32

J12

J11

5

5

Test Head Digital Backplane B 949-882-00

Test Head Digital Backplane A 949-881-00

Jxx_PFILLConnector

P3

1 4

34 37

P6, P7

12

10 9

807-440-01 Cable“P” connector layouts

807-432-00

Cable

Notes:1. When board is installed in slot, a 0 ohm resistor is connected between the input and output.

2. The total resistance measured between J9-3 and J10-3 is xxxx ohms when all boards are installed.

5

5

P1

P2

Board_Installed Signal Flow

12/02/02 46

TJA Inputs from HSD

12/02/02 47

TJA Inputs from High Speed Digital

PE32

Slot 45

Slot 53

Slot 46

Slot 47

Slot 48

Slot 50

Slot 51

Slot 52

PE32

Slot 35

Slot 43

Slot 36

Slot 37

Slot 38

Slot 40

Slot 41

Slot 42

PE #1

PE #8

PE #2

PE #3

PE #4

PE #7

PE #6

PE #5

PE #9

PE #16

PE #10

PE #11

PE #12

PE #13

PE #14

PE #15

PE32

Slot 26

Slot 34

Slot 27

Slot 28

Slot 29

Slot 31

Slot 32

Slot 33

PE32

Slot 54

Slot 62

Slot 55

Slot 56

Slot 57

Slot 59

Slot 60

Slot 61

PE #21

PE #20

PE #22

PE #23

PE #24

PE #19PE #18PE #17

PE #29

PE #28

PE #30

PE #31

PE #32

PE #25

PE #26

PE #27

TMS ATMS BTMS E

TMS ATMS BTMS E

TMS ATMS BTMS E

TMS ATMS BTMS E

TMS ATMS BTMS E

TMS ATMS BTMS E

TMS ATMS BTMS E

TMS ATMS BTMS E

QSB #1

Slot 49

QSB #2

Slot 39

QSB #3

Slot 30

QSB #4

Slot 58

TMS A

TMS B

TMS E

807-433-00 Cable

TMS A

TMS B

TMS E

TMS A

TMS B

TMS E

TMS A

TMS B

TMS E

807-433-00 Cable

807-433-00 Cable

807-433-00 Cable

Row 45

Row 48

Row 51

Row 59

TMB 1SCS CAGE

Slot 22

P1 P2

P1 P2

P1 P2

P1 P2

949-782-00

Rows 28-30(J49-P10)

Rows 28-30(J39-P10)

Rows 28-30(J30-P10)

Rows 28-30(J58-P10)

A

B

E

P1

Rows 62-64

866-107-00 CableP2

TJAPACS CAGE

949-861-00

TMB #2SCS CAGE

Slot 20

949-782-00

807-320-01 Cable

P1

P2 P3 P4

Row 38 40 43

Rows 75-79

J2

12/02/02 48

Digital Cable Diagram

12/02/02 49

Test ComputerBIF PCI Slot 3 J2

CSB BP Slot 1Row 67-72

804-257-00TCIO

10/100 MHz RefJ14

CSB Slot 1Row 14

804-336-00PPCLK100

CSB BP Slot 1Row 23

PACS II804-337-00

CLK100

CSB BP Slot 1Row 145

Linear BB +15V

Linear BB -15V807-202-00

CSB BP Slot 2J6 Row 1


CSB BP Slot 2J8 Row1

CSB BP Slot 2J8 Row26

TH DIG BP A J1

TH DIG BP B J2

TH DIG BP B J3

TH DIG BP A J4

807-425-00

807-425-00

807-425-00

807-425-00STATE A/B

TCIOCLK





TH DIG BP A J49

TH DIG BP A J58

TH DIG BP B J30

TH DIG BP B J39

807-426-00

CLK100

807-426-00

807-426-00

807-426-00


TH DIG BP A J49Row 31

SCS BP Slot 20TMB 2 or

Slot 22 TMB 1Row 40

807-427-00

HSD SYNC

TMS Start

CSB BP Slot 1J2 Row 52 or

Row 163PACS BP #1

Slot 8 row40 or row 98

CSB BP Slot 2J7 Row 1 or Row 4

807-428-00

STATEA/B

RCLK/FFAIL

TH DIG BP A J49Rows 38-40


TH DIG BP B J39Rows 38-40

TH DIG BP B J30Rows 38-40

807-429-00

CALTREE

TH DIG BP A J49 (QSB 1)J58 (QSB 4)Rows 41-45

TH DIG BP BJ39 (QSB 2)J30 (QSB 3)Rows 41-45

807-430-00(x4) TH DIG BP A or B

J53 J54 (A) J35 J34 (B)Row 1

TH DIG BP A or BJ52 J55 (A) J36 J33 (B)

Row 1TH DIG BP A or B

J51 J56 (A) J37 J32 (B)Row 1



J48 J59 (A) J40 J29 (B)Row 1



J46 J61 (A) J42 J27 (B)Row 1


Row 1TH DIG BP A/B

J44(A) J43 J25(B)Row 1

CAL TREE

TH ANA BP J23 TH DIG BP A J13807-431-00Matrix (xpt 2,46,47,48)

CAL; DGS; Safety;Shutdown

TH DIG BP A J11 TH DIG BP B J12807-432-00DC_CALBUS; DGS;Matrix (xpt 2,46,47,48)Safety; Shutdown

SCS BP Slot 22Row 45,48,51,59

TH DIG BP A/BJ30,J39,J49,J58

Rows 28-30

807-433-00(x4)

TMS A, B, E


CTRL PNL HSDSYNC

807-434-00


TH ANA BP J11Row 10

TH ANA BP J12Row 10

807-435-00

Cal Tree; THADS



TH DIG BP B J39Row 26

TH DIG BP B J30Row 26

807-436-00

CALRTN


TH DIG BP A J5

TH DIG BP B J6

TH DIG BP B J7

807-437-00

CLK_800 MHzTH DIG BP A J8

12/02/02 50

Digital and AC signal card pin outs

12/02/02 51

Digital Signal Cards (PE32)

• Digital Signal Cards (PE32)

• This section lists pin-outs for digital signal cards. The digital section of the Tiger test head can be loaded with 32 PE32 channel cards (providing 1024 digital signals) and four Quad Support Boards (QSBs).

• For all tables in this section, pin block column 1 is toward the center of the board.

• Some of the figures and tables in this section do not include listings or names for some pins. Unless otherwise noted, unlisted pins and those listed with blank entries are unused and carry no signal.

• Arrangement of Digital Channels

• Each DIB pin block includes space for 51 signals (48 digital, 3 DGS). However, Tiger digital channel cards (PE32s) contain 34 signals (32 digital, 2 DGS), so signals from adjacent cards are adjoined on the DIB. Therefore, some channel cards deliver signals to two pin blocks, as shown in figures 1-1 and 1-2.

12/02/02 52

Arrangement of Digital Channels

Figure 1-1. Correlation of PE32s to DIB Pin Blocks, DIB Left Figure 1-2. Correlation of PE32s to DIB Pin Blocks, DIB Right

12/02/02 53

Arrangements of Digital Channels

• Each pin block is divided into three sections (labeled A, B, and C). Each section contains 16 digital channels. Within each pin block:

Section A occupies Pogo pads A1 through D11

Section B occupies Pogo pads A13 through D23

Section C occupies Pogo pads A25 through D35

• Figure shows the locations of each section within a pin block. (This figure shows a pin block from the left side of the DIB with the DUT up. The section numbering for pin blocks on the right side of the DIB is reversed; refer to Figure for details.)

• Signals from three PE32s are brought out to the DIB in a specific pattern that crosses two pin blocks. This pattern repeats every 96 channels and proceeds in a U shape as follows (refer to figures, or to an example of how this applies to the first 96 channels):

12/02/02 54

Arrangements of Digital Channels

• All 32 channels from the first PE32 in the pattern are consecutive and appear on the outside

(away from the DUT) and middle sections of the first pin block (Section C and Section B).

• The 32 channels from the second PE32 in the pattern are split between two adjacent pin

blocks: the first 16 channels appear on the inside (toward the DUT) of the first pin block

(Section A). The second 16 channels appear on the inside of the second pin block (Section A).

• The last 32 channels in the series are also consecutive and appear on the outside and middle

sections of the second pin block (Section C and Section B).

Figure shows how the digital channels are arranged on the left side of the DIB, using pin

blocks J11 and J12. (The signals in pin block J13 are included to demonstrate the repetition of the

pattern.)

12/02/02 55

A

B

C

D

1111323253538

1 11 13 23 25 35 38

D

C

B

A

Digital Channel Signal Layout for PE32

Section C Section B Section A

Section A Section B Section C

DIB Left (Pin Blocks J9 through J19)

DIB Right (Pin Blocks J34 through J44)

Signal, Ground, and Empty Patterns on Left and Right Pin Blocks (view from DUT side)

Signal Ground DUT DGS No Signal

12/02/02 56

A

B

C

D

1111323253538

Section C Section B Section A

J11

J12

J13

Arrangement of digital channels, by pin block (DIB left, view from DUT side)

For example, the first 96 channels are arranged as follows:Channels 1 through 16 are located in DIB pin block J11, Section AChannels 17 through 32 are located in DIB pin block J12, Section AChannels 33 through 48 are located in DIB pin block J12, Section CChannels 49 through 64 are located in DIB pin block J12, Section BChannels 65 through 80n are located in DIB pin block J13, Section CChannels 81 through 96 are located in DIB pin block J13, Section B

This pattern repeats in blocks of 96 digital channels

Channels 1-16

Channels 17-32Channels 33-48 Channels 49-64

Channels 65-80 Channels 81-96 Channels 97-112

Channels 225-240 Channels 241-256

CABLE

12/02/02 57

1 11 13 23 25 35 38

D

C

B

A

Section A Section B Section C

1 11 13 23 25 35 38

D

C

B

A

1 11 13 23 25 35 38

D

C

B

A

J36

J37

J38




Arrangement of digital channels, by pin block (DIB right, view from DUT side)

CABLE

12/02/02 58

Table shows the mapping of PE32 channel cards to DIB pin blocks. (Table) shows the arrangement of signals and grounds for one digital DIB pin block.) This table is arranged in ascending order of digital channels (1 to 1024), regardless of position on the DIB.

Table 1-1. DIB Locations for All PE32 Channel Cards

12/02/02 59

Digital Channel Signal Layout for PE32Figure x-x shows the arrangement of signal, ground, and empty Pogo pads within pin blocks.

12/02/02 60

PE32 (Pin Electronics32) Channel Card• The PE32 provides per-pin functionality for 32 high-speed digital channels, including timing, source and measurement

of voltage and current, digital signals, and calibration.

• Table lists the signals and grounds for one digital pin block.

Table 1-2. DIB Pin Block Signal Arrangement for Digital Channels

B

12/02/02 61

Note: There are three DUT_DGS pins (10B, 22B, and 34B) in each pin block. To use the PE32 reference as the DUT reference, connect the PE32’s DGS signals to the DUT ground.

Table lists the location on the DIB of each digital channel. (Table provides a visual layout of the arrangement of digital and analog channels on the DIB.)

Table 1-3. Digital Channel Locations on the DIB Table 1-3. Digital Channel Locations on the DIB (Continued)

12/02/02 62

Digital Channel Locations on the DIB (Continued) Digital Channel Locations on the DIB (Continued)

12/02/02 63

Digital Channel Locations on the DIB (Continued)

12/02/02 64

Quad Support Board

12/02/02 65

AC SIGNAL CARDSAnalog Instrument Loading Rules

The Tiger AC card cage uses frame cards to hold two AC instruments, referred to as “upper” and “lower,” per pin block, and both instruments have access to the entire pin block. As a result, you can install instruments in the same frame card only if they do not have any signal pins in common.

Table details which cards can coexist under the same pin block.

The slots in the frame card are labeled as follows:

• The lower AC channel card is closer to the DIB and is even-numbered.

• The upper AC channel card is further from the DIB and is odd-numbered.

Placement of AC Instruments in Shared Frame Cards

12/02/02 66

Analog Channel-Card-to-DIB Pin Block Mapping

The Tiger test head allows two analog channel cards to be placed within one frame card and to share one pin block on the DIB. Table lists the mappings of analog slots to DIB pin blocks.

12/02/02 67

Mapping of Analog Slot Locations to DIB Pin Blocks (Continued)

1. ACISB-B replaces the Catalyst’s Left HAS in slot 1.

2. To maintain numbering compatibility with Catalyst test systems, instrument slot numbers 12 and 13 are not assigned to physical locations.

3. ACISB-A replaces the Catalyst’s Right HAS in slot 24.

12/02/02 68

AC Support Board Pin-outs

This section describes the pin-outs for support boards in the AC section of the test head.

AC Instrument Support Boards (ACISB-A, ACISB-B)

The ACISBs provide all the support needed for the instruments in the AC section of the test head.

This includes distributing THADS, timing, and calibration signals; bringing stored databits (SDBs) to the DIB; and providing power to the instruments as well as user power. User power can be provided in levels of 30V, +12V, 15V, and 5V. ACISB-B is also responsible for providing power and signals to the EEPROM, and other miscellaneous control voltages. ACISBs require the entire test head slot and do not use frame cards.

ACISB-A (also called “Right ACISB”) appears in pin block J1.

ACISB-A Channel Card Pinout

12/02/02 69

ACISB-A Channel Card Pinout (Continued)

12/02/02 70

ACISB-B Channel Card Pinout

ACISB-B (also called “Left ACISB”) appears in pin block J26.

ACISB-B Channel Card Pinout (continued)

12/02/02 71

Quad Voltage Source (QVS)

The Quad Voltage Source (QVS) is a programmable device power supply that can regulate output voltage within a small deviation over a wide and fast variation of current. It is designed to test devices that require higher current draw and reduced operating voltages. It provides current of up to 5.0A and voltages of up to 6V. Total power per channel is limited to 30W (DC), with a peak of 240W (DC) per board. Maximum metering frequency is 50KHz.

QVS Channel Card Pinout

12/02/02 72

High Current Power Supply (HCPS)

The HCPS provides a stable supply voltage on the DUT power supply pins and measures the current drawn. It is capable of providing 15A on each of two high-current channels, and 6A on each of four medium-current channels, in voltage ranges between 0V and 8V.

HCPS Channel Card Pinout

12/02/02 73

Low Frequency AC (LFAC)

The Low Frequency AC Source (LFACSRC) is designed to provide, and the Low Frequency AC Digitizer (LFACDIG) is designed to digitize, AC waveforms for applications such as audio and telecom device testing. Typical tests include gain vs. frequency, distortion, and signal-to-noise ratio.

The source instrument provides samples at frequencies ranging from DC to 1.2MHz at voltages ofup to +/-10.24V (....5.12V between 500KHz and 1.2MHz), with a current of < 65mA. The digitizer samples waveforms at frequencies of between DC and 1.2MHz, with voltages of up to 11.0V (....5.12V between 500KHz and 1.2MHz), with a current of < 65mA.

Both Low Frequency AC instruments reside on the same channel card.

LFAC Channel Card Pinout

12/02/02 74

Very High Frequency Arbitrary Waveform Generator 400 (VHFAWG400)

The VHFAWG is designed to generate waveforms for applications such as video, Ethernet, disk drives, and flash converters. The AWG400 is a single-ended instrument, with a differential option available allowing for driving differential devices without adding conversion circuitry on the DIB.

The source instrument operates in one of three modes: DC, sine wave, or AC. It provides samples at up to 400MHz in all modes. In DC and sine wave mode, it provides a maximum voltage of 8.0V for a single-ended open circuit connection, or 4.0V for an open circuit if the differential option is installed. In AC mode, it provides a maximum 4.0V for an open circuit in either single-ended or differential mode. In all modes, it can provide 40mA of current (typical). Operating frequencies range from DC to 80MHz for the single-ended instrument; with the differential option installed, frequencies range from 5MHz to 160MHz for AWG mode, or from 80MHz to 200MHz for sine wave mode.

VHFAWG400 Channel Card Pinout

12/02/02 75

Very High Frequency Digitizer 1GHz (1GVHFD)

The 1GVHFD can digitize single-ended and differential inputs from DC up to 1GHz waveforms using one of its three input modes: normal (digitizing), downconverting (optional), and undersampling. The 1GVHFD supports four differential input measurement paths: three Pogo pin and one RF connector. For the location of the RF signals, see “RF signal connectors”.

In Normal Digitizing mode, waveforms from DC to 50MHz with voltage ranges of up to 8.192V can be captured. In the compatible VHFDIG Undersampling mode, waveforms from DC to 300MHz with voltage ranges of 4.096V can be digitized. In the 1GHz Undersampling mode, waveforms from DC to 1GHz with differential voltage ranges of 4.096V peak. Also, the 1GHz VHFDIG Undersampling input can accept common mode voltages of 5V.

1GHz VHFD Channel Card Pinout

12/02/02 76

Very High Frequency Continuous Waveform Source (VHFCW)

The Very High Frequency Continuous Wave Source (VHFCW) is a programmable sinewave source. It provides a high-purity sinewave with programmable frequency (1MHz to 249.999999 MHz with 1Hz resolution), amplitude (-31dBm to 16.0dBm into a 50 ohm load), and DC offset (-2.0V to 2.0V). Applications for the VHFCW Source include disk driver amplifiers, opamps, and flash converters.

12/02/02 77

RF Signal Cards

This section discusses design considerations for DIBs that incorporate RF (1 GHz or higher) signals, and includes RF signal card pinouts.

RF signal connectors

RF signal path

RF connectors may be placed anywhere in the Applications Area (the large rectangular block in the middle of the DIB, also used for DUT placement,

12/02/02 78

Tiger DIB EEPROM

EEPROM Signals

12/02/02 79

12/02/02 80

12/02/02 81

12/02/02 82

DIB Interface Cables

Cable Part Number DIB Position

804-440-01 9/34804-440-02 10/35804-440-03 11/36804-440-04 12/37804-440-05 13/38804-440-06 14/39804-440-07 15/40804-440-08 16/41804-440-09 17/42804-440-10 18/43804-440-11* 19/44

*For -11 Cable assembly, J2 module is not needed.

PE32 DIB Header Cables

Cable Part Number DIB Position

866-318-01 9/34866-318-02 10/35866-318-03 11/36866-318-04 12/37866-318-05 13/38866-318-06 14/39866-318-07 15/40866-318-08 16/41866-318-09 17/42866-318-10 18/43866-318-11* 19/44

*For -11 Cable assembly, J2 module is not needed.

DPE32 DIB Header Cables

QSB DIB Header Interface Cable

807-914-00

12/02/02 83

High Speed Digital Channel by DIB Location

J9 J10 J11 J12Digital

ChannelPOGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin

161 A9 177 A9 1 A9 17 A9162 C9 178 C9 2 C9 18 C9163 B8 179 B8 3 B8 19 B8164 D8 180 D8 4 D8 20 D8165 A7 181 A7 5 A7 21 A7166 C7 182 C7 6 C7 22 C7167 B6 183 B6 7 B6 23 B6168 D6 184 D6 8 D6 24 D6169 A5 185 A5 9 A5 25 A5170 C5 186 C5 10 C5 26 C5171 B4 187 B4 11 B4 27 B4172 D4 188 D4 12 D4 28 D4173 A3 189 A3 13 A3 29 A3174 C3 190 C3 14 C3 30 C3175 B2 191 B2 15 B2 31 B2176 D2 192 D2 16 D2 32 D2



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High Speed Digital Channel by DIB Location (cont)


ChannelPOGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin




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ChannelPOGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin

801 A9 817 A9 513 A33802 C9 818 C9 514 C33803 B8 819 B8 515 B32804 D8 820 D8 516 D32805 A7 821 A7 517 A31806 C7 822 C7 518 C31807 B6 823 B6 519 B30808 D6 824 D6 520 D30809 A5 825 A5 521 A29810 C5 826 C5 522 C29811 B4 827 B4 523 B28812 D4 828 D4 524 D28813 A3 829 A3 525 A27814 C3 830 C3 526 C27815 B2 831 B2 527 B26816 D2 832 D2 528 D26



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ChannelPOGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin




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ChannelPOGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin

DigitalChannel

POGOPin




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J43 J44Digital

ChannelPOGOPin

DigitalChannel

POGOPin

449 A33 481 A33450 C33 482 C33451 B32 483 B32452 D32 484 D32453 A31 485 A31454 C31 486 C31455 B30 487 B30456 D30 488 D30457 A29 489 A29458 C29 490 C29459 B28 491 B28460 D28 492 D28461 A27 493 A27462 C27 494 C27463 B26 495 B26464 D26 496 D26

465 A21 497 A21466 C21 498 C21467 B20 499 B20468 D20 500 D20469 A19 501 A19470 C19 502 C19471 B18 503 B18472 D18 504 D18473 A17 505 A17474 C17 506 C17475 B16 507 B16476 D16 508 D16477 A15 509 A15478 C15 510 C15479 B14 511 B14480 D14 512 D14

433 A9434 C9435 B8436 D8437 A7438 C7439 B6440 D6441 A5442 C5443 B4444 D4445 A3446 C3447 B2448 D2

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The Tiger Differential Option is a DPE32 channel card with high speed digital differentialchannels. These channels are similar to the standard digital channels, but they can be usedtogether in pairs to drive or receive signals differentially. One channel, the odd channel of apair of channels, drives or receives a signal, while the other channel, the even channel,drives or receives a signal that is the inverse of the first. DPE32 differential channel cardsare used in the same test head slots as the standard high speed digital channel cards.

The differential channels:

- Can be used single ended- Are compatible with and interchangeable with standard Tiger HSD channels- Can be mixed in a Tiger test system- Use Tiger HSD channel programming statements, but with additional statements for the inverted channels and for the differential functions

Features include:

- Driver modes: single-ended, differential, combined, complementary, single-ended multiplex, and differential multiplex- Receiver modes: single-ended, single-ended multiplex, differential with common mode, differential multiplex, and common mode multiplex- Large or small swing drive- Large swing: 300 mV to 5 V swing- Small swing: up to 500 mV swing- Up to 1.6 Gbps differential data rate- Compatible with standard Tiger digital channels and IMAGE tools

Typical applications for digital differential channels include testing high speed low voltagedifferential devices such as transceivers, serializers, deserializers, and differential busses.

12/02/02 90

Glossary of “new” terms

vid The differential driver voltage. dvid0 The delta vid for a data “0”. Nominally 0.dvid1 The delta vid for a data “1”; Nominally 0.vicm The differential driver common-mode voltage in complementary or differential mode.vicmh The differential driver common-mode high voltage in combined mode.vicml The differential driver common-mode low voltage in combined modedvicm1 The delta vicm, vicmh, or vicm1 for a data “0”.dvicm1 The delta vicm, vicmh, or vicm1 for a data “1”.vod The differential comparator threshold. Usually set to equal the minimum acceptable

voltage difference between the two pins of a DUT output pair for data on the pair to be considered valid.dvod0 The delta vod for a data “0”. Nominally 0.dvod1 The delta vod for a data “1”. Nominally 0.vocmh The common-mode comparator high threshold.vocml The common-mode comparator low threshold.swing:large Large voltage swing mode. The drive and receive voltage can be a maximum of 5 V. This is the default.swing:small Small voltage swing mode. Drive and receive voltages are less than 50 mV.

Note the following:

vid and vod do not have “high and low”. Instead they have polarity: a “one” is positive and a “zero” is negative.They are always programmed in terms of their absolute values.

vicm is cached, not overwritten when a pin pair is put into combined mode.

12/02/02 91

DPE32 (Differential Pin Electronic32) Channel Card

The DPE32 for the TIGER provides high speed digital differential channels that are similar to the standard digital channels but can be used together in pairs to drive or receive differential signals.

The odd channel of a pair of channels drives or receives a signal, while the even channel drives or receives a signal that is the inverse of the first.

The DPE32 can be used in single-ended mode and can be mixed with the standard PE32 in a TIGER test system.

The table below lists the arrangement of signals and grounds for one differential digital pin block. Each row contains one digital differential pair.

The odd channels carry the normal signals; the next higher even channels carry the inverse signals.

Normal signals listed in column A pair with inverse signals in column C; normal signals listed in column B pair with inverse signasl in column D.

In row 2, for example, column B holds the normal signal and column D holds its inverse.

A B C D

1

2

3

Section

A B C

Gnd

Signal Signal

Gnd

Gnd Gnd

Signal Gnd Signal Gnd

SignalGndSignalGnd


SignalGndSignalGnd

4

5

6

7

8

9

10

11

12


SignalGndSignalGnd


Gnd DGS Gnd

Gnd

A B C D

13

14

15

Section

Gnd

Signal Signal

Gnd

Gnd Gnd


SignalGndSignalGnd


SignalGndSignalGnd

16

17

18

19

20

21

22

23

24


SignalGndSignalGnd


Gnd DGS Gnd

Gnd

A B C D

25

26

27

Section

Gnd

Signal Signal

Gnd

Gnd Gnd


SignalGndSignalGnd


SignalGndSignalGnd

28

29

30

31

32

33

34

35

24


SignalGndSignalGnd


Gnd DGS Gnd

Gnd

DIB Pin Block Signal Arrangement for DPE32 Digital Channels

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DP

DE

Vicmh

Vicml

Vcl

Vch

DP

DE

Vswing

R

R

R

Functional DUT

To DUT

DUT Alarm

Alarm R

Parametric

Vclh

Vcll

PPMU

PPMU

DC Sense

Sense

DC MatrixForce

DCR

R

Voh

Vol

Vod

Vol

Voh

Vocmh

Vocml

DP

DE

Vicmh

R

Vicml

DP

DE

Vswing

Vch

VclR

R

Functional DUT

To DUT

DUT Alarm

Alarm R

Parametric

PPMU

PPMU

Vclh

Vcll

DC Sense

Sense

DC MatrixForce

DC

TDRCalibration

Differential Channel (DPE32) Block Diagram

IolIoh

Vcp

IolIoh

Vcp

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THADS Bus

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THAD 1A A1

THAD 1B B1

THAD 2A C1

THAD 2B D1

THAD 3A A2

THAD 3B B2

THAD 4A C2

THAD 4B D2

THAD 5A A3

THAD 5B B3

THAD 6A C3

THAD 6B D3

THAD 7A A4

THAD 7B B4

THAD 8A C4

THAD 8B D4

THAD 9A A5

THAD 9B B5

THAD 10A C5

THAD 10B D5

SUBBUSA A6

SUBBUSB C6

LHAS A B7

LHAS B D7

RHAS A A8

RHAS B C8

HSD THAD D9

J11ACISB B

J5

J4

J3

J2

J1

Frame Card 4THAD 3A/B LowerTHAD 4A/B UpperVirtual Slots 4 & 5

CC 3 & 4


CC 1 & 2


CC 4 & 5


CC 7 & 8


CC 9 & 10

DIBBLOCK

27

DIBBLOCK

28

DIBBLOCK

29

DIBBLOCK

30

DIBBLOCK

31

J12ACISB A

C3

D3

A4

B4

C4

D4

A5

B5

C5

D5

A1

B1

C1

D1

A2

B2

C2

D2

A3

B3

A6

C6

A8

C8

B7

D7

D9

THAD 11A

THAD 11B

THAD 12A

THAD 12B

THAD 13A

THAD 13B

THAD 14A

THAD 14B

THAD 15A

THAD 15B

THAD 16A

THAD 16B

THAD 17A

THAD 17B

THAD 18A

THAD 18B

THAD 19A

THAD 19B

THAD 20A

THAD 20B

SUBBUSA

SUBBUSB

LHAS A

LHAS B

RHAS A

RHAS B

HSD THAD

J6

J7

J8

J9

J10


CC 11 & 12


CC 13 & 14

Frame Card 8THAD 15A/B LowerTHAD 16A/B UpperVirtual Slots18 & 19

CC 15 & 16


CC 17 & 18


CC 19 & 20

DIBBLOCK

2

DIBBLOCK

3

DIBBLOCK

4

DIBBLOCK

5

DIBBLOCK

6

B1

C1

B2

C2

B1

C1

B2

C2

B1

C1

B2

C2

B1

C1

B2

C2

B1

C1

B2

C2

B1

C1

B2

C2

B1

C1

B2

C2

B1

C1

B2

C2

B1

C1

B2

C2

B1

C1

B2

C2

THADS CC1A

THADS CC1B

THADS CC2A

THADS CC2B

THADS CC4A

THADS CC4B

THADS CC5A

THADS CC2B THADS CC5B

THADS CC2B

THADS CC6A

THADS CC6B

THADS CC7A

THADS CC8B

THADS CC9A

THADS CC9B

THADS CC10A

THADS CC7B THADS CC10B

THADS CC8A

Circuitry on one (1) ACISB

SUBBUS 1A

SUBBUS 1B

SUBBUS 2A

SUBBUS 2B

B10HSD_THAD_IN

807-435-00 CableTo

Digital BP AJ49

P2 P1

SUBBUS A

949-886-00/01 ACISB-B / ACISB-A

HSD

L/R_HAS_A

L/R_HAS_B

SUBBUS A

SUBBUS B

SUB 1A

SUB 1B

SUB 2A

SUB 2B

SUB 1A

SUB 1B

SUB 2A

SUB 2B

THADS

Documents

Tiger Quick Reference - Digital