Ti Jtag Seminar

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

AL 10Sept.-97 1149.1(JTAG)-Tut.I-1 1997 TI Test Symposium

JTAG(IEEE 1149.1/P1149.4)

TutorialIntroductory



Agenda■ What Is JTAG? (5 minutes)

■ The Increasing Problem of Test (5 minutes)

■ Conventional Methods of Test (10 minutes)

■ The Boundary-Scan Idea (15 minutes)

■ The Boundary-Scan Architecture (15 minutes)

■ Typical Applications (15 minutes)— Interconnect Testing

— Logic Cluster Testing

— Memory Testing

— System-Level Test

■ Real JTAG Applications (10 minutes)

■ For More Information (5 minutes)

■ Q & A (10 minutes)



What Is JTAG?



Standard Approach To Test

■ Developed by Joint Test Action Group (over 200 SC, test, andsystem vendors) starting in mid '80's

■ Sanctioned by IEEE as Std 1149.1 Test Access Port andBoundary-Scan Architecture in 1990

■ Solution: Build test facilities/test points into chips

■ Focus: Ensure compatibility between all compliant ICs

JTAG / IEEE 1149.1JTAG / IEEE 1149.1



Standard Test Access Port ...

■ 4/5-Wire Interface at Chip-Level

■ Serial Instruction/Serial Data Port

■ Extensible to Include

— user-defined instructions

— user-defined data registers

User Register

Bypass Register

Instruction Register

Decode LogicDR

TDI

IR

TDO

TMS

TCKTAP

Controller

TRST*



… and Boundary-ScanArchitecture

■ Scan effectively partitions digitallogic to facilitate control andobservation of its function

■ Chip-Internal Scan: Partitionschips at storage cells (latches/ flip-flops) to effectively partitionsequential logic into clusters ofcombinational logic

■ Boundary-Scan: Partitions boardsat chip I/Os for control andobservation of board-level nodes

CORE

peterc

Topic 8 - JTAG Boundary Scan



The IncreasingProblem of Test



The Incredible ShrinkingBoard

■ Miniaturization results in loss of test access

Yesterday Today Tom orrow ?



The Ever-Expanding Chip

■ Increasing integration at chip levelcomplicates controllability

Yesterday

1 0

Today

1DC1

1DC1

1 ?



Cost will increase by a factor often as fault finding movesfrom one level of complexityto the next. The result:

■ Reduced Profit Margins

■ Delayed ProductIntroduction

■ Dissatisfied Customers

Can’t Afford Not To Test

1. Device level 1 unit of cost2. Board level 10 units of cost3. System level 100 units of cost4. Field level 1,000 units of cost



ConventionalMethods of

Test



Conventional Methodsof Board Test

■ Based on board function,rather than structure

■ Test generation primarilymanual

■ Test access limited toprimary I/O only

Functional Test(‘Edge-Connector’ Test)




■ Based on board structure, butlimited by chip complexity

■ Expensive testers and fixturesrequired

■ Test access limited by:

— Fine pitch packages

— Double-sided boards

— Conformal coating

— MCMs

In-Circuit Test(‘Bed-of-Nails’ Test)




In-Circuit Test(‘Bed-of-Nails’ Test)

■ Chip function can beignored for shorts testing

■ Chip function must beconsidered for continuitytest

■ Test generation, thoughautomated, requires ICTmodels



TheBoundary-Scan

Idea



The Boundary Scan Idea

■ ‘In-Circuit’ test points movedonto the silicon, creating‘Virtual Nails’

■ Boundary scan cells boundeach net, providing forcontinuity testing

■ Observe/Control cells providefor test and normal function

CORE CORE



The Boundary Scan Idea

■ Scan provides a meansto arbitrarily observetest results and sourcetest stimulus

■ Scan method requiresminimal on chip/boardresources (pins/nets)

CORE CORE



Boundary Scan Methodof Board Test

■ Based on board structure;Not limited by chipfunction/ complexity

■ Test access is not limitedby board physical factors

CORECORE

CORECORE

CORECORE

JTAG



Boundary Scan Methodof Board Test

■ Chip function need not beconsidered for board test(shorted/open nets)

■ Test generation is highlyautomated; Simple‘In-Circuit Library’ models(BSDL) are vendor-supplied orEDA-generated



The Boundary Scan Cell

CORE

NO

(No

rmal O

utp

ut)

NI (

No

rmal

Inp

ut)

SI (Serial Input)

SO (Serial Output)

TEST/DATAMUX

UPDATELATCH/FLOP

SCANLATCH/FLOP

CAPTURE/SCAN MUX

OBSERVE CONTROL



The Control Architecture

■ Boundary scan and other testdata registers operate undercontrol of instructionregister

■ Data is scanned from TDI toTDO through selected testdata register or instructionregister under control of TestAccess Port (TAP) controller

■ TAP operates synchronouslyto TCK using TMS for stateselection

CORE

ID Register

Bypass Register


Decode LogicDR

TDI

IR

TDO

TMS

TCKTAP

Controller



The Test Access Port Controller

■ 16-state TAPprovides 4 majoroperations:

— RESET

— RUN-TEST

— SCAN-DR

— SCAN-IR

■ Scans consist of 3primary steps:

— CAPTURE

— SHIFT

— UPDATE

Select DR-Scan Select IR-Scan

statetransitions

occur onrising edge

of TCKbased on

the currentstate andthe TMS

input valueONLY

Test Logic Reset

Run Test/Idle

Capture-IR

Shift-IR

Exit 1-IR

Pause-IR

Exit 2-IR

Update-IR

0

1

0

1

1 1

1

0

0

0

0

1

1

1 0 1

0

1

10

0

10

0

1

1

0

0

1

Capture DR

Shift-DR

Exit 1-DR

Pause-DR

Update-DR

Exit 2-DR

0

0

1



The Extest Instruction(REQUIRED)

■ Provides for test external to chip,such as interconnect test

Output pins operate in test mode,driven from contents of BSCupdate latch

Input data captured in BSC scanlatches prior to shift operation

■ Shift operation allows testresponse to be observed at TDOwhile next test stimulus insertedat TDI

Following shift operation, newtest stimulus transferred to BSCupdate latches

TMS

TCK

ID Register

Bypass Register


Decode LogicDR

TDI

IR

TDO

TAPController

CORE



The Sample/Preload Instruction(REQUIRED)

■ Provides means to preloadboundary before entry to testmode

■ Output and input pins operatein normal mode

Input pin data and core logicoutput data captured in BSCscan latches

■ Shift operation allows testresponse to be observed whilenext test stimulus inserted atTDI

Following shift operation,new stimulus transferred toBSC update latches

ID Register

Bypass Register


Decode LogicDR

TDI

IR

TDO

TMS

TCKTAP

Controller

CORE



The Bypass Instruction(REQUIRED)

■ Provides for abbreviated scanpath through chip

■ Output and input pins operatein normal mode

■ The one-bit bypass register isselected for scans

■ Mandatory that an all-onesvalue updated into the IRdecodes to Bypass, as well asany opcodes which areotherwise undefined

CORE

ID Register

Bypass Register


Decode LogicDR

TDI

IR

TDO

TMS

TCK TAPController



Typical JTAGApplications



Interconnect Test

■ All nets bound by BSC'sand/or primary I/O requiringno physical access

■ Parallel access reducedto card edge only

■ Test generation andapplication fast and easy

Full B/S Board

JTAG



Interconnect Test

■ Not all nets are bound byboundary scan and/or primaryI/O, perhaps requiring some ICTaccess

■ Expense and complexity reducedfor test generation and testapplication for chips/nets withB/S access

■ Cluster testing may be used toaccess non-scan nets

Partial B/S Board

JTAG



Logic Cluster Test■ Random-logic cluster is

bound by boundary-scannable chips

■ Deterministic test stimulus(ATPG-generated) can bedriven to cluster from B/Soutputs

■ Test response can be capturedat B/S inputs

■ BIST methods (PRPG/PSA)can be used for increased testthroughput and near"At-speed" performance

LO

GIC

"CL

US

TE

R"



Logic Cluster Test

IEEE 1149.1

Buffer

Buffer

Buffer Latch

Buffer

Registered Transceiver

Mic

rop

roce

sso

r

ControlLogic

(Non-Scan)

Parallel Data In

MemoryArray

Address

Control

DataScan Path

‘LV

T18

502

‘LV

T18

502

‘LVT18502

‘AB

T18502

‘AB

T18502

‘LV

T18504

TM

S

TC

K

TD

O

TD

I



Memory Test

■ Memory array bound byboundary scan chips

■ Automatic test patterns can begenerated and driven from B/Soutputs

■ Test response can be captured atB/S inputs

■ Transceivers can test for netshorts w/o memory R/W

■ BIST methods (PRPG/PSA) canbe used for increased testthroughput

Latch

Buffer

Registered Transceiver

Address

Control

Data

MemoryArray

‘AB

T18

502

‘AB

T18

502

‘LV

T18

504



Memory Test

256ACCESSES

1,000,000ACCESSES

IEEE 1149.1EXTEST &SAMPLE)

IEEE 1149.1(with BISTcapability)

Time To ApplyScansPatterns

Time To ApplyScansPatterns

375.00 Minutes2,000,0002,000,000

< 0.01 Minutes28,000

2,000,000

MODE

5.625000 Seconds512512

0.000041 Seconds7

512

SN74BCT82451A11A21A31A42A12A22A32A4

TDITCK

1B11B21B31B42B12B22B32B4

DIR

TDOTMS

G

1Y11Y21Y31Y42Y12Y22Y32Y4

TDOTMS

SN74BCT82441A11A21A31A42A12A22A32A4

TDITCK

G2G1

256 x 8 RAM ArrayA0A1A2A3A4A5A6A7

D0D1D2D3D4D5D6D7

WE

CS

1Y11Y21Y31Y42Y12Y22Y32Y4

TDITCK

SN74BCT82441A11A21A31A42A12A22A32A4

TDOTMS

G2G1



System-Level Test

■ TAP-addressable interface unitextends JTAG access beyondboard-level

■ System-level test

■ System design verification

■ Sys integration (Mfg test)

■ Sys self-test (Field Svc)

■ Supports in place board test andboard-to-board test

■ Allows reuse of device/board test data

ASP TDO

TDITMS

TCK

ASP

ASP

✦ ASP-Addressable Scan Port Device



Real JTAGApplications



Real Applications of the TAP

■ Scan access to chips, boards,systems for:

— Design verification/debug

— Manufacturing test

— Hardware/software integration

— Field test/diagnostics

■ Access built-in self-test (BIST)

■ Access on-chip/in-circuitemulation (ONCE/ICE)

■ Access in-system programming(ISP) of PLDs/EEPROMs

■ Let your imagination run wild!!!TDI TCK TMS TDO

TAP

CORE

I N T E R N A L

S C A N

T E S T

BIST

Emulation

Programming



JTAG

Design Verification/Debug

■ Provides control and observation ofsystem under test without need forphysical access

— Ease of set-up for test

— Can be used in standard systemconfiguration (no need for cardextenders, etc.)

— Can be used in environmentalchambers

— Can access on-chip emulation forsoftware/debug

— Can access ISP for codedownload/offload/ changes



■ Provides test and diagnosticcapabilities of in-circuit testwithout need/expense ofphysical access

— Improved faultcoverage/diagnostic withoutlarge capital expense

— Highly automated testgeneration reduces testdevelopment time

Manufacturing Test

JTAG

ICT



System ConfigurationMaintenance

■ Provides low-level test accesswithin configured systems for:

— In-house system integration

— Fielded-system test anddiagnostics

— Built-in self-test

— In-field upgradabilityvia ISP, etc.

— Remote field test,diagnostic and upgrade

JTAG



TI’s JTAG Educational ProductsCall (214)-638-0333 to ORDER

■ Scan Educator

— PC-based tutorial with interactiveboundary-scan simulation.

— FREE download athttp://www.ti.com/sc/data/jtag/scanedu.exe

■ IEEE 1149.1 Testability videotapes

— Two-part video presenting an overview andinstructions for boundary scan.

— Item No. SATV001 (NTSC VHS) andSATV002 (PAL VHS), $149 each.

— In process of converting to MPEG on CD-ROM

IEEE 1149.1Boundary-Scan



IEEE StandardsCall (800) 678-IEEE to ORDER

■ IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993), IEEE StandardTest Access Port and Boundary-Scan Architecture, ISBN 1-55937-350-4,IEEE order number SH16626.

— The official document which specifies the international standard for a testaccess port and boundary-scan architecture. Informally known as the JTAGstandard, it was officially ratified by the IEEE in February 1990. Since, it hasbeen supplemented twice. The first supplement, ratified in June 1993, isincluded in the referenced document. The second supplement is currently aseparate document, as referenced below.

■ IEEE Std 1149.1b-1994, Supplement to IEEE Std 1149.1-1990, ISBN 1-55937-497-7, IEEE order number SH94256.

— The official document which specifies the international standard for aboundary-scan description language. This supplement to IEEE Std 1149.1-1990was ratified in September 1994.



Tutorials/Handbooks■ The Test Access Port and Boundary-Scan Architecture, Colin M. Maunder, Rodham

E. Tulloss, ed., IEEE CS Press, ISBN 0-8186-9070-4.

— Edited by two principal chairs of the IEEE 1149.1 working group, thisComputer Society tutorial compiles several of the seminal papers on boundary-scan along with several invited papers on various topics including applications,implementation, and others. It will primarily be of interest to the design and/ortest engineer.

■ The Boundary-Scan Handbook, Kenneth P. Parker, Kluwer Academic Publishers,ISBN 0-7923-9270-1.

— Authored by the principal force behind the Boundary-Scan DescriptionLanguage (BSDL) and an IEEE 1149.1 working group principal as well as along time manufacturing and design-for-test expert, this is truly consideredTHE indispensable handbook on boundary scan for the design and/or testengineer.

■ Boundary-Scan Test - A Practical Approach, Harry Bleeker, Peter van den Eijnden,Frans de Jong, Kluwer Academic Publishers, ISBN 0-792-9296-5.

— Authored by several JTAG and IEEE 1149.1 working group principals, thisbook is a ready reference to boundary-scan technology, its benefits, andconsiderations for design and test managers and engineers.



Abbreviations/AcronymsASIC Application-Specific Integrated Circuit

ASP Addressable Scan Port

ATE Automatic Test Equipment

ATPG Automatic Test Pattern Generation

BIST Built-In Self-Test

B/S Boundary-Scan

BSC Boundary-Scan Cell

BSDL Boundary-Scan Description Language

BSR Boundary-Scan Register

BST Boundary-Scan Test

CAE Computer-Aided Engineering

DFT Design-for-Test

DR Data Register

DSP Digital Signal Processing/Processor

EDA Electronic Design Automation

eTBC Embedded Test Bus Controller

FPGA Field-Programmable Gate Array

HSDL Hierarchical Scan Description Language

ICE In-Circuit Emulation

ICT In-Circuit Test

IEEE Institute of Electrical & Electronics Engineers IRInstruction Register

ISP In-System Programming

JTAG Joint Test Action Group

MCM Multi-Chip Module

Mfg Manufacturing

PCB Printed Circuit Board

PLD Programmable Logic Device

PRPG Pseudo-Random Pattern Generation

PSA Parallel Signature Analysis

PWB Printed Wiring Board

SPL Scan Path Linker

SVF Serial Vector Format

TAP Test Access Port

TBC Test Bus Controller

TCK Test Clock

TDI Test Data Input

TDO Test Data Output

TMS Test Mode Select

TRST Test Reset

UUT Unit Under Test

Documents

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