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GOMAC, March 25, 2010, Reno, NV.
THz Bipolar Transistors: Design and Process Technologiesg g
Mark Rodwell University of California, Santa Barbara
E L bi V J i A B k M S B J Thib ltE. Lobisser, V. Jain, A. Baraskar, M. Seo, B. J. Thibeault,University of California, Santa BarbaraM. Seo, Z. Griffith, J. Hacker, M. Urteaga, Richard Pierson, B. BrarT l d S i tifi CTeledyne Scientific Company
[email protected] 805-893-3244, 805-893-5705 fax
WhWhyTH T i ?THz Transistors ?
Why Build THz Transistors ?500 GHz digital logic→ fiber optics
THz amplifiers→ THz radios i i i → imaging, sensing,
communications
precision analog design at microwave frequencies→ high-performance receivers
Higher-Resolution Microwave ADCs, DACs, DDSs→ high-performance receivers DDSs
Why Bipolars for Fast Analog Applications ?
digital frequency synthesis mm-wave jammer on chipdigital frequency synthesis mm-wave phased arrays
jammer on chip
high resolution ADCs and DACs for 2-20, 38 GHzBJTs, particularly InP,h hi h b kdCMOS does not serve all ICs
low analog gainlow analog precision
high Cds /Cgs , high Cgd /Cgs→ less bandwidth
have high breakdown
g plow breakdown voltage
0.35 fF0.7 fF
→ less bandwidth than f suggests
0.7 fF
H M k How to Make TH T iTHz Transistors
Changes required to double transistor bandwidthHBT parameter changeHBT parameter changeemitter & collector junction widths decrease 4:1current density (mA/m2) increase 4:1current density (mA/m) constant
eW
cu e t de s ty ( / ) co s acollector depletion thickness decrease 2:1base thickness decrease 1.4:1emitter & base contact resistivities decrease 4:1 ELlength emitter
FET parameter change
Egnearly constant junction temperature → linewidths vary as (1 / bandwidth)2
gate length decrease 2:1current density (mA/m), gm (mS/m) increase 2:1channel 2DEG electron density increase 2:1
GL
gate-channel capacitance density increase 2:1dielectric equivalent thickness decrease 2:1channel thickness decrease 2:1channel densit of states increase 2 1 channel density of states increase 2:1
source & drain contact resistivities decrease 4:1 GW widthgate
constant voltage, constant velocity scaling fringing capacitance does not scale → linewidths scale as (1 / bandwidth )
256 nm GenerationInP HBT 8
10
m230
40
UH
150 nm thick collectorZ. Griffith
0
2
4
6
0 1 2 3 4 5
mA/
0
10
20dB
H21
f = 424 GHz
fmax
= 780 GHz340 GHz dynamic frequency dividerM. Seo, UCSB/TSC
30 109
1010
1011
1012
H21
0 1 2 3 4 5V
ce
0109 1010 1011 1012
Hz
20
70 nm thick collector
10
20
dBf = 560 GHz
fmax
= 560 GHz
U
5
10
15
mA
/m
2
340 GHz VCOVtuneVtune
E. LindM. Seo, UCSB/TSC
0109 1010 1011 1012
Hz
00 1 2 3 4
Vce
4030
60 nm thick collectorVout
VEE VBB
Vout
VEE VBB
20
30
dB
U
H21
f 218 GH 10
20
30
mA/m
2
324 GHz amplifier J. Hacker, TSCZ. Griffith
0
10
109 1010 1011 1012
Hz
ft = 660 GHz
fmax
= 218 GHz
0
10
0 1 2 3
m
Vce
InP Bipolar Transistor Scaling Roadmap
emitter 512 256 128 64 32 nm width16 8 4 2 1 2 16 8 4 2 1 m2 access
base 300 175 120 60 30 nm contact width, 20 10 5 2 5 1 25 m2 contact 20 10 5 2.5 1.25 m2 contact
collector 150 106 75 53 37.5 nm thick, 4.5 9 18 36 72 mA/m2 current density4.5 9 18 36 72 mA/m current density4.9 4 3.3 2.75 2-2.5 V, breakdown
f 370 520 730 1000 1400 GHz eWfmax 490 850 1300 2000 2800 GHz
power amplifiers 245 430 660 1000 1400 GHz digital 2:1 divider 150 240 330 480 660 GHz
e
bcWcTbT
Conventional ex-situ contacts are a messTHz transistor bandwidths: very low resistivity contacts are required
textbook contact with surface oxide with metal penetration
THz transistor bandwidths: very low-resistivity contacts are required
Interface barrier → resistanceInterface barrier resistanceFurther intermixing during high-current operation → degradation
In-Situ Refractory Ohmics on Regrown N-InGaAs
4
5
)
In-situ Mo on n-InAs In-situ Mo on n-InGaAs6
8
)
2
3
esis
tanc
e (
2
4
esis
tanc
e (
0
1
0 0.5 1 1.5 2 2.5 3 3.5
Re
ρc = 0.6 ± 0.4 Ω·µm2
n = 1×1020 cm-3
ρc = 1.0 ± 0.6 Ω·µm2
n = 5×1019 cm-3
0
2
0 0.5 1 1.5 2 2.5 3 3.5
Re
Gap Spacing (m)
In-situ emitter contacts good
Gap Spacing (m)HAADF-STEM*
InGaAsthIn situ emitter contacts good
enough for 64 nm node Interface
InGaAs
regrowth
2 nm
InGaAs
TEM by Dr. J. Cagnon, Stemmer Group, UCSB
A. Baraskar
Process Must Change Greatly for 128 / 64 / 32 nm Nodes
control undercut→ thinner emitter thinner emitter
→ thinner base metalthinner base metal→ excess base metal resistance
Undercutting of emitter endsg101A planes: fast
111A planes: slow
128 / 64 nm process: Dry-Etched Emitter Metal
In-situ MBE emitter contacts:refractory→ high Jlow contact : ~0.7 -m2
Refractory emitter contactdry-etched→ nm resolutionrefractory→ high currentW t/d t h d itt Wet/dry etched emitter dry-etched→ nm resolutionconventional base liftoffhigh penetration→ thick baseshigh penetration→ thick basesmoderate contact ~4-m2
yield issues ?
V. JainE. Lobisser
Dry-Etched W/TiW Emitter Contact Process
Sputtered W/ Ti0.1W0.9processpVertical ICP etch profileLow-stress filmLow stress filmGood adhesion between layersRefractory Refractory MetalsW/TiW bilayer:stress and etch bias compensation
V. JainE. Lobisser
Sub-100 nm devices: lifted-off base metal
After Sidewall EtchAfter Sidewall Etch Base Contact Post and Mesa EtchBase Contact Post and Mesa Etch
V. JainE. Lobisser
After Sidewall EtchAfter Sidewall Etch Base Contact, Post and Mesa EtchBase Contact, Post and Mesa Etch
Device Isolation EtchDevice Isolation Etch HBT before BCB processingHBT before BCB processing
Sub-100 nm devices: lifted-off base metal V. JainE. Lobisser
Sub-100 nm devices: lifted-off base metal V. JainE. Lobisser
15 MAG/MSG
10
15
dB)
UA
je= 0.11m x 3.5m
Ic = 9.1mA; V
ce = 1.75V
Je = 23.6mA/m2; V
cb = 0.7V
MAG/MSG
30
40
dB)
Aje
= 0.11m x 3.5m
U
H
MAG/MSGft = 400 GHz
f = 660 GHz
5Gai
n (d
H21
fmax
= 660 GHz10
20
Gai
n (d
Ic = 8.9mA; V
ce = 1.74V
H21
max
2
01011 1012
freq (Hz)
ft = 465 GHz
0109 1010 1011 1012
freq (Hz)
c ceJ
e = 23.1mA/m2; V
cb = 0.7V
40
50
60
m2 )
50 mW/m240 mW/m2
Aje = 0.11m x 3.5m
I = 0.2 mA600
750
600
750
Hz) ft
: Vcb
= 0 V: V
cb = 0.7 V
10
20
30
J e (mA
/um
Vcb
= 0 V
Ib,step
0.2 mA
300
450
300
450f m
ax (G
H
t (GH
z)
0
10
0 1 2 3V
ce (V)
Ib = 0.01 mA
Peak ft/f
max
1500 5 10 15 20 25 30 35
150
Je (mA/m2)
128 / 64 nm process: Sputtered Refractory Base
In-situ MBE emitter contacts:refractory→ high Jlow contact : ~0.7 -m2
Refractory emitter contactdry-etched→ nm resolutionrefractory→ high currentW t/d t h d itt Wet/dry etched emitter dry-etched→ nm resolutionRefractory base contactslow penetration→ thin baseslow penetration→ thin baseslow contact ~2.5 -m2
self-aligned/ liftoff-free
V. JainE. Lobisser
In-Situ Refractory Ohmics on P-InGaAs
Metal Contact ρc (Ω-µm2) ρh (Ω-µm)In-situ Ir 1.0 ± 0.7 11.5 ± 3.3
20Iridium
10
15ta
nce
()
WR
R ShCC
22
5Res
ist
W0
0 1 2 3 4Gap Spacing (m)
In-situ base contacts good enough for 32 nm nodeRemaining work: contacts on processed surfaces
contact thermal stability & reliability A. Baraskar
Benefits of refractory base contacts
100 nm InGaAs grown in MBE
15 nm Pd/Ti diffusion
30 nm Mo
After 250°C anneal, Pd/Ti/Pd/Au diffuses 15nm into semiconductordeposited Pd thickness 2 5nmdeposited Pd thickness: 2.5nmbase now 30 nm thick: observed to degrade with thinner bases
Refractory Mo contacts do not diffuse measurablyRefractory Mo contacts do not diffuse measurablyRefractory, non-diffusive metal contacts for thin base semiconductor
A.. Baraskar
Sputtered Process for in-situ base contacts
• Blanket ex-situ Pd/W contacts• Planarization and etch back 15
20
)
Iridium
• Low contact resistivity• Lift-off free and Au free base process• Self-aligned process for thin emitters
10
esis
tanc
e (
Self aligned process for thin emitters • Enables refractory, in-situ base contacts
0
5
0 1 2 3 4
Re
ρc =1.0 ± 0.7 Ω-µm2
0 1 2 3 4Gap Spacing (m)
Planarization boundary
SiNx Sidewall
V. JainE. Lobisser
Sub-100 nm HBTs : planarized base contact
Emitter projecting from PR forEmitter projecting from PR forplanarization planarization Planarized EmitterPlanarized Emitter
Base Contact, Post and Mesa EtchBase Contact, Post and Mesa Etch Contact Via EtchContact Via Etch
V. JainE. Lobisser
670 GHz Transceiver Simulations in 128 nm InP HBT transmitter exciter Simulations @ 670 GHz (128 nm HBT)transmitter exciter
5
10
15
20
LNA: 9.5 dB Fmin at 670 GHz
20
30
S(2,
1))
f(2)
f(2)
Simulations @ 670 GHz (128 nm HBT)PA: 9.1 dBm Pout at 670 GHz
receiver
128nm-8 -6 -4 -2 0 2 4 6 8-10 10
-5
0
5
-10640 660 680 700620 720
10
0
SP.freq, GHz
dB(S
freq GHz
nf n
128nm
VCO50
(1 H
z)
free-runningVCO:-50 dBc (1 Hz)@ 100 Hz offsetat 620 GHz (phase 1)
-150
-100
-50
0
101 102 103 104 105 106 107
PLL
sing
le-s
ideb
and
phas
e no
ise
spec
tral d
ensi
ty, d
Bc free running
VCO
closed-loop VCO noise
multiplied reference noise
Total PLLphase noise
3-layer thin-film THz interconnectsthick-substrate--> high-Q TMICthin -> high-density digital
10 10 10 10 10 10 10offset from carrier, Hz
-1.05
-1
-0.95
-0.9690 GHz Input
t , V
out_
bar
-1.05
-1
-0.95
-0.9
950 GHz Input
ut, V
out_
bar
Dynamic divider:novel design,simulates to 950 GHzg y g
-1.2
-1.15
-1.1
195 10-12 197.5 10-12 200 10-12
Vou
time, seconds
-1.2
-1.15
-1.1
195 10-12 197.5 10-12 200 10-12
Vou
time, seconds
simulates to 950 GHz
30
n (d
B)
Mixer:
-10.00 -5.000 0.0000 5.000 -15.00 10.00
0
5
10
15
20
25
-5
LO Power
Noi
se F
igur
e, C
onve
rsio
n G
ainMixer:
10.4 dB noise figure11.9 dB gain
InP HBT Fundamental Oscillators to > 340 GHzM. Seo UCSBM. Rodwell UCSBM. Urteaga TSCTSC HBT Technology
Differential Topology, Cascode output buffer, ECL outputsFixed frequency and voltage controlled designs
VVOUTOUT
Q3Q3 Q4Q4Q5Q5Q5Q5
RR11
RR33LLout1out1
LLout2out2
VtuneVtune
Q3Q QQ
Q1Q1 Q2Q2Q6Q6
RR22
RR44
LLBB
LLC1C1
LLC2C2LLC3C3
VEE VBBVEE VBB
RREE
LLE1E1
LLE2E2
CCVarVar CCVarVar
Vout
VEE VBB
Vout
VEE VBB
VVEEEE VVTUNETUNE VVBBBB
C1C1 C2C2 C3C3
EE
InP HBT 331 GHz Dynamic Frequency Dividers M. Seo UCSBM. Rodwell UCSBM. Urteaga TSC Z. Griffith TSCTSC HBT Technology
Topology: Double-balanced mixer with emitter follower feedback and resonant loading
Modified version of modern dynamic divider (H.M. Rein)
Circuit Schematic
y ( )
Inverted microstrip wiring Design variations with input for external clock
source and with integrated fixed frequency and voltage controlled oscillators for testing.
O t t t ith 331 2 GH l k i t Chi h t hOutput spectrum with 331.2 GHz clock input Chip photograph“Signal Identification” test at fIN= 331.2 GHz
THz 240 GHz PA DesignT. Reed UCSBM. Urteaga TSCZ. Griffith TSCTSC HBT Technology
Teledyne InP HBTs We=256nm, Tc=150nmTwo-finger design achieves S21 = 4.9dB @ 238GHz
TH T iTHz Transistors
THz Integrated Circuits
Device scaling (Moore's Law) is not yet over.
Scaling→ multi-THz transistors
Challenges in scaling:
Scaling→ multi-THz transistors.
g gcontacts, dielectrics, heat
M l i TH iMulti-THz transistors:for systems at very high frequenciesfor better performance at moderate frequenciesfor better performance at moderate frequencies
Vast #s of THz transistorscomplex systemsnew applications.... imaging, radio, and more
end
On-Wafer TRL Calibration Envirnoment
Ref Plane for TRL
Ref Plane for TRL
0.5-67GHz Data: Lumped Pads, Off Wafer LRRM Cal.
m7Ft_fit = 400GHz Fmax_fit = 660GHz
Standard Off Wafer OSLTOpen & Short Pad Cap Extraction
Open Short
THTHzBi l T i Bipolar Transistors
Sub-100 nm devices: lifted-off base metal V. JainE. Lobisser
15 MAG/MSG
10
15
dB)
UA
je= 0.11m x 3.5m
Ic = 9.1mA; V
ce = 1.75V
Je = 23.6mA/m2; V
cb = 0.7V
MAG/MSG
30
40
dB)
Aje
= 0.11m x 3.5m
U
H
MAG/MSGft = 400 GHz
f = 660 GHz
5Gai
n (d
H21
fmax
= 660 GHz10
20
Gai
n (d
Ic = 8.9mA; V
ce = 1.74V
H21
max
01011 1012
freq (Hz)
ft = 465 GHz
0109 1010 1011 1012
freq (Hz)
c ceJ
e = 23.1mA/m2; V
cb = 0.7V
600
750
600
750
Hz) ft
: Vcb
= 0 V: V
cb = 0.7 VS21/5
S12x5S21/5
S12x5
300
450
300
450f m
ax (G
H (GH
z)--- : Measured x : Simulated--- : Measured x : Simulated
1500 5 10 15 20 25 30 35
150
Je (mA/m2)
S11 S22S11 S22
Sub-100 nm devices: lifted-off base metal V. JainE. Lobisser
60 40 mW/m210-2
40
50
60
um2 )
50 mW/m240 mW/m
Aje = 0.11m x 3.5m
Ib,step
= 0.2 mA10-4
10
A)
Ic
Ib
Solid Line: Vcb
= 0 VDashed Line: V
cb = 0.7 V
10
20
30
J e (mA
/u
Vcb
= 0 V
, p
10-8
10-6
I b, Ic (A b
nc = 1.41
nb = 3.04
00 1 2 3
Vce
(V)
Ib
= 0.01 mA
Peak ft/f
max
10-10
0 0.2 0.4 0.6 0.8 1V
be (V)
8
6
7
8
F)
Vcb
= 0 V
4
5
6C
cb (f
F
Vcb
= 0.4 V
V 0 V3 0 5 10 15 20 25 30
Je (mA/m2)
Vcb
= 0.7 V
2008 UCSB Dry-Etched Ti/TiW Emitter Process
SiO23 4
BHF
Litho patternmetal
sidewall dry etch wet etch
TiW
I G A ++Ti
I G A InGaAs n++InGaAs n++
InGaAs p++ Base
InP n
InGaAs p++ Base InGaAs p++ Base InGaAs p++ Base InGaAs p++ Base
InP nInGaAs n++ InGaAs n++
InP n InP n
30 109
1010
1011
1012
U
H21 Worked well @ 200 nm
base contactby liftoff
10
20
dB
f = 560 GHz
fmax
= 560 GHz
U
Low yield @ 128 nm:stress→ poor adhesion
0109 1010 1011 1012
HzSubstantial revisionrequired