Upload
jillian-erickson
View
34
Download
0
Tags:
Embed Size (px)
DESCRIPTION
Threats and Challenges in FPGA Security. Ted Huffmire Naval Postgraduate School December 10, 2008. Overview. Problem Areas. Foundry Trust. Physical Attacks. Design Tools. Design Theft. System Assurance. Attacks. Trojan horse Backdoor Kill switch. Probing Sand and Scan - PowerPoint PPT Presentation
Citation preview
Threats and Challenges in FPGA Security
Ted Huffmire
Naval Postgraduate School
December 10, 2008
Overview
FoundryTrust
PhysicalAttacks
DesignTools
DesignTheft
Problem Areas
Attacks
Trojan horseBackdoorKill switch
ProbingSand and ScanSide Channels
Data Remanence
Covert channelsSide channels
Bypass
CloningReverse engineerReadback attack
SolutionsTrusted foundries
FPGAsX-Ray InspectionSand and Scan
Tamper sensingAdding noiseDegaussing
Logical isolationTracing wiresSanitization
Continuous powerEncrypt bitstream
WatermarkingAuthentication
Future Research
All of supply chainLessons from S/W
Red teamsSide channels
Trusted toolsVerificationLanguages
CM
High-assurancePartial reconfig
PUFs
High-assuranceCMPs
TaggingDynamic security
Reference monitorDefense in depth
User trainingSecurity usability
DoSAuthentication
Complex designs
SystemAssurance
Reconfigurable Hardware
FPGA Chip
SDRAM (off-chip)
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Re
feren
ceM
on
itor
Crypto Core
CPU Core
CPU Core
AES
μP
μP
Protection Alternatives
Separation Kernels
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
app1 app3app2
kernel
Separate Processors
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
gatekeeper
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
gatekeeper
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
gatekeeper
app1app3 app2
Reconfigurable Protection
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM app1
app2
app3
Reference
Monitor
Physical Software
Spatial Temporal
Design Flows
Intertwined Cores
Moats
FPGA Chip
SDRAM (off-chip)
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Re
feren
ceM
on
itor
Crypto Core
CPU Core
CPU Core
AESAES
Moats 1.0
Moats 2.0
Moats and Drawbridges
Interconnect Tracing
FPGA Chip
SDRAM (off-chip)
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Re
feren
ceM
on
itor
Crypto Core
CPU Core
CPU Core
AES
μP
μP
XX
Communication Architecture
FPGA Chip
SDRAM (off-chip)
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Arb
iter/R
efere
nce M
onitor Crypto Core
CPU Core
CPU Core
AES
μP
μP
Memory Protection
FPGA Chip
SDRAM (off-chip)
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Crypto Core
CPU Core
CPU Core
AESAES
Re
feren
ce M
on
itor
X
XR
eference Monitor
Policy Compiler
SoC Application
Questions?
http://faculty.nps.edu/tdhuffmi