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Authorization for Reproduction of Master4s Thesis

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without further authori6ation from me.

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iv

A"stract

An artificial neural network is a computing technique that allows problems to be solved

that would otherwise require an overly complex procedural algorithm. <y designing a

large network of computing nodes based on the artificial neuron model, new solutions

can be developed to problems relating fields such as image and speech recognition.

This thesis presents the ?@ABI? algorithm as a computing technique that is capable of

supporting an artificial neural network in programmable hardware such as DEFAs. The

algorithm is presented in depth, including a derivation and precision analysis. The

designs of a parallel and bitGserial implementation are analyHed with respect to their

ability to support a large neural network. Simulations demonstrating the operation of the

unit follow a breakdown of the subcomponents in each design. It is shown that the small

resource requirements of the ?@ABI? algorithm allow for many instances in an DEFA,

allowing the parallelism inherent to an artificial neural network to be maintained.

! ! "

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vii

List of Tables

Table 4.1—CORDIC growth factors for each computation domain................................................................ 38 Table 4.2—Functions that can be computed using the CORDIC algorithm. .................................................. 39 Table 4.3—Domains of convergence for the CORDIC algorithm................................................................... 41 Table 5.1—Overall device utilization for the parallel design........................................................................... 48 Table 5.2—Unconditional control unit outputs for each state in the parallel design. ..................................... 50 Table 5.3—Device utilization for the parallel control unit. .............................................................................. 52 Table 5.4—Device utilization for the parallel shift register. ............................................................................ 53 Table 5.5—Device utilization for the parallel lookup table.............................................................................. 54 Table 6.1—Overall device utilization for the serial design. ............................................................................. 61 Table 6.2—State outputs for the serial control unit........................................................................................... 64 Table 6.3—Device utilization for the serial control unit. ................................................................................. 64 Table 6.4—Device utilization for a single serial shift register (including 32:1 multiplexer)......................... 66 Table 6.5—Device utilization for the serial lookup table. ................................................................................ 66 Table 6.6—Device utilization for the serial and parallel adders. ..................................................................... 68 Table 7.1—Device resource requirements for the artificial neuron designs using both the parallel and serial

CORDIC units............................................................................................................................................ 81

viii

List of Figures

Figure 2.1—Components that comprise an artificial neuron, the basic building blocks of artificial neural

networks. ...................................................................................................................................................... 5 Figure 2.2—A basic artificial neural network. .................................................................................................... 9 Figure 3.1—Internal structure of a Xilinx Spartan-3 FPGA [8]....................................................................... 20 Figure 3.2—Block diagram of a slice in a Spartan-3. ....................................................................................... 23 Figure 3.3—Block diagram of a Complex Logic Block (CLB) in a Spartan-3. .............................................. 24 Figure 4.1—Step i in the CORDIC algorithm. .................................................................................................. 28 Figure 4.2—The CORDIC Rotation mode. ....................................................................................................... 32 Figure 4.3—CORDIC Vectoring Mode ............................................................................................................. 34 Figure 5.1—Block-level diagram of the complete parallel CORDIC unit. ..................................................... 47 Figure 5.2—State diagram for the parallel CORDIC unit. ............................................................................... 49 Figure 5.3—State transition logic for the parallel CORDIC unit. .................................................................... 50 Figure 5.4—Logic behind the state-independent outputs of the parallel control unit..................................... 51 Figure 5.5—Design of the variable shift register. ............................................................................................. 53 Figure 5.6—Slices used by the various components of the parallel CORDIC unit. ....................................... 54 Figure 5.7—Results of a ModelSim simulation attempting to compute the value of e. As a result of

CORDIC growth, the final computed value is inaccurate....................................................................... 56 Figure 5.8—Results of a ModelSim simulation computing the value of e. By accounting for CORDIC

growth, the final computed value is accurate........................................................................................... 57 Figure 5.9—Results of a ModelSim simulation computing the value of e

–1. .................................................. 57

Figure 5.10—Results of a ModelSim simulation computing the value of e5. Since the initial value 5 is

outside the domain of convergence, the computed value is incorrect. ................................................... 58 Figure 6.1—Block diagram for the serial implementation of the CORDIC algorithm................................... 60 Figure 6.2—State diagram for the serial implementation of the CORDIC algorithm. ................................... 63 Figure 6.3—Design of the serial shift registers. ................................................................................................ 65 Figure 6.4—Design of the serial adder. ............................................................................................................. 67 Figure 6.5—Slices used by the various components of the serial CORDIC unit............................................ 68 Figure 6.6—Results of a ModelSim simulation of the serial CORDIC unit attempting to compute the value

of e. As a result of CORDIC growth, the final computed value is inaccurate. ...................................... 70 Figure 6.7—Results of a ModelSim simulation of the serial CORDIC unit computing the value of e. By

accounting for CORDIC growth, the final computed value is accurate................................................. 71 Figure 6.8—Results of a ModelSim simulation of the serial CORDIC unit computing the value of e

–1. ..... 72

Figure 6.9—Results of a ModelSim simulation of the serial CORDIC unit computing the value of e5. Since

the initial value 5 is outside the domain of convergence, the computed value is incorrect. ................. 73 Figure 7.1—Slices required by the various components of the two CORDIC designs. ................................. 76 Figure 7.2—The effect of word size on the FPGA chip area requirements of the CORDIC unit.................. 78 Figure 7.3—The effect of word size on the execution time of the CORDIC unit........................................... 78 Figure 7.4—Block diagram of a basic artificial neuron utilizing the CORDIC unit to compute the transfer

function ex................................................................................................................................................... 80

Figure 7.5—Simulation of an artificial neuron using the 4 inputs (0.3, 0.02, 2.1, 0.65) and the weights (1, 2,

–0.5, 0.25)................................................................................................................................................... 82

1

Chapter 1 Introduction

Traditional design techniques typically require a systems designer to formulate a

mathematical model of the system, and then design an algorithm to operate on the system

inputs in accordance with the model. In general, this approach works well, but there are

some applications where either the mathematical model is difficult to derive, or the

algorithm is too complex to be implemented in a cost-effective manner. Image and

speech processing are two such problems that people intuitively understand but require

complicated mathematical models that in turn require a good deal of computing power to

operate [10].

In these situations, an artificial neural network can be employed. Rather than

deriving an algorithm for analyzing the image or speech pattern, the parameters of the

network are tweaked in a process called training until the desired outputs are obtained

from the network. As will be shown in Chapter 2, networks are massively parallel

networks of small computing nodes called “neurons.” This parallelism makes neural

networks naturally suited to hardware implementations. A software implementation

running on a single microprocessor can only simulate parallelism; only in a hardware

implementation can the real-time benefits of this parallelism be achieved.

Programmable hardware devices such as FPGAs are particularly suited as platforms

for implementation, since the various parameters of the network occur during training.

Programmable hardware devices also afford several other benefits to hardware designers

by eliminating a lot of the difficulties that come with custom chip design. With a platform

for these artificial neural networks chosen, a means of performing the computations in the

interconnected nodes is needed. The number of these nodes can be large; the arithmetic

2

unit must be small enough so that it can be duplicated enough to maintain the parallelism

inherent in the structure.

The CORDIC algorithm will be presented as a solution to that problem. The

algorithm lends itself to a simple hardware implementation consisting only of basic

addition and shifting operations. In addition to its small chip area footprint, the algorithm

can compute a wide variety of functions ensuring that it can be used in a variety of ways

within a system. In particular, the algorithm can compute the exponential function, ex by

summing together the values of sinh(x) and cosh(x), both of which are computed in

parallel by the unit. The exponential function has an application as the transfer function

in a specific type of neural network and is chosen as the function of study for this thesis.

Chapter 2 will describe neural networks in detail and describe how they operate. The

structure of the network will be analyzed, as will the design of the neurons that comprise

the network. Chapter 3 will study the design of programmable hardware devices—

FPGAs in particular. The benefits they offer hardware designers will be presented, as will

the basic structures common to most implementations. Chapter 4 introduces the CORDIC

algorithm. A general-purpose definition of the algorithm is presented, and proofs of

convergence and precision are presented. Expansion into multiple computation domains

allows for the computation of sine, cosine, square root, multiplication, hyperbolic sine,

and hyperbolic cosine.

Chapter 5 and Chapter 6 study two implementations of the CORDIC algorithm and

study how the components of the CORDIC processing unit fit into a Xilinx Spartan-3

FPGA. Simulations performed using the ModelSim software are presented. Chapter 7

3

then compares these two designs and shows how they can be used in a neural network to

facilitate their implementation in a programmable device.

"

Chapter ) *rti,icia. /eura. /et1or34

As electronic devices increasingly become more a part of society, the desire for

devices to solve more complex problems is growing. ;ome problems have no easy

algorithmic solution, or the problems themselves are not completely understood. It is in

these cases that it is occasionally easier to develop a learning machine that can be taught

what to do in a situation without needing to understand the underlying processes.

Artificial neural networks are one such technique. They are designed to emulate the

human brainAs ability to learn. The same structure can be used to solve many different

problems, depending on the training methods employed.

)51 7ac38round

The structure of an artificial neural network is similar to that of the human brain. The

human brain is made up of billions of cells called neurons. The computational power of

the brain is a result of the large volume of neurons available, coupled with learning

ability.

The neurons themselves have several different classifications and subcomponents.

The computation process comes as a result of the interconnection of these different types

of neurons. Bowever, unlike the digital realm in which artificial neural networks reside,

the neurons in the brain “form a process which is not binary, not stable, and not

synchronous” [10].

Though artificial neural networks try to mimic the way in which the human brain

operates, the methodology is not designed to replace the brain, especially since so much

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l$%%$r '$ig*t%. -*$ pot$ntial to l$arn i% incorporat$d into t*$ arti4icial n$uron 6and t*u%

t*$ n$t'or789 :; allo'ing t*$ input '$ig*t% to :$ adapti<$ co$44ici$nt%. -*$ adaptation

proc$%% i% p$r4orm$d in r$%pon%$ to training %$t% o4 data9 and d$p$nd% on :ot* t*$

n$t'or7>% %p$ci4ic topolog; a% '$ll a% t*$ l$arning rul$ :$ing appli$d.

!"!"! #$%%&'()* ,$*-'()*

-*$ 4ir%t %t$p in t*$ op$ration o4 an arti4icial n$uron i% t*$ %ummation 4unction. ?%

t*$ nam$ impli$%9 t*i% i% u%uall; a %ummation o4 t*$ '$ig*t$d input% to t*$ n$uron. -*$

%ummation 4unction can :$ mor$ compl$@ t*an a %impl$ %ummation. Ot*$r 4unction% u%$d

ar$ minimum9 ma@imum9 maBorit;9 product9 and ot*$r normaliCing algorit*m%. ?n;

4unction t*at op$rat$% on multipl$ input% to produc$ a %ingl$ output Duali4i$%.

!"!". /0&*1230 ,$*-'()*

?4t$r t*$ input% *a<$ pa%%$d t*roug* t*$ %ummation 4unction9 t*$; ar$ t*$n 4$d

t*roug* a tran%4$r 4unction. -*i% tran%4$r 4unction i% u%uall; a nonlin$ar 4unction. On$ o4

t*$ goal% o4 arti4icial n$ural n$t'or7% i% to :$ a:l$ to pro<id$ nonlin$ar proc$%%ing.

Eo'$<$r9 t*$ a:ilit; o4 a n$ural n$t'or7 to p$r4orm in a nonlin$ar 4a%*ion i% d$p$ndant

upon t*$ tran%4$r 4unction o4 t*$ indi<idual n$uron%. F; c*oo%ing a lin$ar tran%4$r

4unction9 t*$ o<$rall n$t'or7 'ould :$ limit$d to %impl$ lin$ar com:ination% o4 t*$

input%. Gariou% tran%4$r 4unction% ar$ t;picall; u%$d. ? <$r; common tran%4$r 4unction i%

t*$ *;p$r:olic tang$nt. -*$ *;p$r:olic tang$nt i% a continuou% 4unction9 a% ar$ it%

d$ri<ati<$%.

Hn a 4$' ca%$%9 a uni4orm noi%$ g$n$rator i% add$d :$4or$ t*$ tran%4$r 4unction i%

appli$d. -*$ output o4 t*i% g$n$rator i% r$4$rr$d to a% t*$ n$uron>% It$mp$ratur$.J -*$

%urrounding t$mp$ratur$ can ad<$r%$l; a44$ct t*$ *uman :rain9 and :; adding t*i%

7

ca%a&ilit* to artificial neural network34 t5e &e5a6ior of t5e network 7ore clo3el*

e7ulate3 a 5u7an &rain.

!"!"# $%&'()* &), -(.(/()*

97%le7entation of t5i3 %ortion of t5e artificial neuron 7o:el i3 o%tional. ;5e out%ut

of t5e tran3fer function i3 7ani%ulate: in or:er to lie wit5in certain &oun:3. Scaling i3

%erfor7e: fir3t4 followe: &* 3o7e 3ort of t5re35ol: function.

Accor:ing to An:er3on an: ?cNeil ABCD4 t5e3e co7%onent3 are u3uall* u3e: w5en

eE%licitl* 3i7ulating &iological neuron 7o:el3.

!"!"0 12232 45)%/(3)

;5e raw error of t5e network i3 t5e :ifference &etween t5e :e3ire: out%ut an: t5e

actual out%ut. ;5e error function tran3for73 t5i3 raw error to 7atc5 t5e %articular network

arc5itecture in u3e. 9f it i3 :e3ire: &* t5e 3*3te7 arc5itect to con3i:er error in t5e network4

t5en t5i3 co7%onent i3 inclu:e: in t5e neuron 7o:el. 9n t5i3 ca3e4 %ro%agation :irection

of t5i3 error i3 u3uall* &ackwar:3 t5roug5 t5e network. ;5e &ackF%ro%agate: 6alue 3er6e3

a3 t5e in%ut to ot5er neuron3G learning function3.

!"!"6 75/85/ 45)%/(3)

Hut3i:e t5e neuron 7o:el4 &ut relate: to it i3 t5e out%ut function. Nor7all* t5e

out%ut of t5e neuron i3 eIual to t5e out%ut of t5e tran3fer function. J5en i7%le7ente:4

t5e out%ut function allow3 for co7%etition &etween t5e out%ut3 of 6ariou3 neuron3.

Jit5in a 37all Kneig5&or5oo:L of neuron34 a large out%ut &* one neuron will cau3e t5e

out%ut of a :ifferent neuron to :i7ini35. 9n ot5er wor:34 t5e lou:e3t neuron cau3e3 t5e

ot5er neuron3 to &e Iuieter.

"

2.2.# $earning Function

#he learnin+ ,un.tion 1odi,ie3 the input 5ei+ht3 o, the neuron6 7ther na1e3 +i8en

to thi3 ,un.tion are the adaptation ,un.tion9 or learnin+ 1ode6 #here are t5o 1ain type3

o, learnin+ 5hen dealin+ 5ith neuron3 and neural net5or;36 #he ,ir3t type9 3uper8i3ed

learnin+9 i3 a ,or1 o, rein,or.e1ent learnin+ and re<uire3 a tea.her9 u3ually in the ,or1 o,

trainin+ 3et3 or an o=3er8er6 >n3uper8i3ed learnin+ i3 the other type9 and i3 =a3ed upon

internal .riteria =uilt into the net5or;6 #he 1a?ority o, neural net5or;3 utili@e the

3uper8i3ed learnin+ 1ethod9 a3 un3uper8i3ed learnin+ i3 .urrently 1ore in the re3ear.h

real16 #he pro.e33e3 u3ed to train a net5or; are di3.u33ed in A6B6

2.1 Artificial 5eural 5etwork 8tructure

Crti,i.ial neural net5or;3 ,un.tion a3 parallel di3tri=uted .o1putin+ net5or;36 Da.h

node in the net5or; i3 an arti,i.ial neuron6 #he3e neuron3 are .onne.ted to+ether in

8ariou3 ar.hite.ture3 ,or 3pe.i,i. type3 o, pro=le136 Et i3 i1portant to note that the 1o3t

=a3i. ,un.tion o, any arti,i.ial neural net5or; i3 it3 ar.hite.ture6 #he ar.hite.ture9 alon+

5ith the al+orith1 ,or updatin+ the input 5ei+ht3 o, the indi8idual neuron39 deter1ine3

the =eha8ior o, the arti,i.ial neural net5or;6 Feuron3 are typi.ally or+ani@ed into layer3

5ith .onne.tion3 =et5een neuron3 eGi3tin+ a.ro33 layer39 =ut not 5ithin6 Da.h neuron

5ithin ea.h layer i3 o,ten ,ully .onne.ted to all neuron3 in the a33o.iated layer6 #hi3 .an

lead to a 8a3t a1ount o, .onne.tion3 eGi3tin+ 5ithin the net5or;9 e8en 5ith relati8ely

,e5 neuron3 per layer6 Hi+ure A6A 3ho53 a 3i1ple neural net5or; .ontainin+ I layer36 En

thi3 .a3e9 the layer3 are not ,ully .onne.ted6

"

input layer outputlayer

hiddenlayer

!igure 2.2*+ ,asi/ arti1i/ia2 neura2 net4or6.

!"#"$ %&'() +,-./

#$%&'&%()* $+(,-$. ),+ (.+% /-, +)01 &$2(3 -/ )$ ),3&/&0&)* $+(,)* $+34-,56 71+.+

&$2(3. 0-(*% 8+ 0-**+03+% %)3)9 -, ,+)* 4-,*% &$2(3. /,-: 21;.&0)* .+$.-,.6 <,+=2,-0+..&$>

-/ 31+ &$2(3. 0)$ 8+ %-$+ 3- .2++% (2 31+ *+),$&$> 2,-0+.. -/ 31+ $+34-,56 #/ 31+ &$2(3. ),+

.&:2*; ,)4 %)3)9 31+$ 31+ $+34-,5 4&** $++% 3- *+),$ 3- 2,-0+.. 31+ %)3) &3.+*/9 ). 4+** ).

)$)*;?+ &36 71&. 4-(*% ,+@(&,+ :-,+ 3&:+9 )$% 2-..&8*; )$ +'+$ *),>+, $+34-,5 31)$ 4&31

2,-0+..+% &$2(3.6

!"#"! 0122.& +,-./3

71+ &$2(3 *);+, &. 3;2&0)**; 0-$$+03+% 3- ) 1&%%+$ *);+,6 A(*3&2*+ 1&%%+$ *);+,. :);

+B&.39 4&31 31+ &$2(3. -/ +)01 1&%%+$ *);+,C. $+(,-$. -/3+$ 8+&$> /(**; 0-$$+03+% 3- 31+

1#

$u&pu&s $) &*e previ$us/0 /a0er2s neur$ns. 5idden /a0ers 7ere given &*a& na9e due &$ &*e

)a:& &*a& &*e0 d$ n$& see an0 rea/ 7$r/d inpu&s n$r d$ &*e0 give an0 rea/ 7$r/d $u&pu&s.

;*e0 are )ed <0 &*e inpu& /a0er2s $u&pu&s= and )eed &*e $u&pu& /a0er2s inpu&s. ;*e nu9<er

$) neur$ns 7i&*in ea:* $) &*e *idden /a0ers= as 7e// as &*e nu9<er $) *idden /a0ers

&*e9se/ves= de&er9ines &*e :$9p/e>i&0 $) &*e s0s&e9. ?*$$sing &*e rig*& a9$un& )$r ea:*

is a 9a@$r par& $) designing a 7$rAing neura/ ne&7$rA. Bigure 2.2 s*$7s $ne *idden

/a0er= <u& $&*er ne&7$rA ar:*i&e:&ures :an *ave 9u/&ip/e *idden /a0ers.

!"#"# $%&'%& )*+,-

Da:* neur$n 7i&*in &*e $u&pu& /a0er re:eives &*e $u&pu& $) ea:* neur$n 7i&*in &*e

/as& *idden /a0er. ;*e $u&pu& /a0er pr$vides rea/ 7$r/d $u&pu&s. ;*ese $u&pu&s :$u/d g$ &$

an$&*er :$9pu&er pr$:ess= a 9e:*ani:a/ :$n&r$/ s0s&e9= $r 9a0<e saved in&$ a )i/e )$r

ana/0Eing. LiAe &*e $u&pu& )un:&i$n $) an individua/ neur$n= &*e $u&pu& /a0er 9a0

par&i:ipa&e in s$9e s$r& $) :$9pe&i&i$n <e&7een $u&pu&s. ;*is /a&era/ in*i<i&i$n :an <e

seen in Bigure 2.2 as &*e d$&&ed /ines :$nne:&ing &*e $u&pu& neur$ns. Gn addi&i$n= &*e

$u&pu&s 9a0 a/s$ <e )ed <a:A in&$ previ$us neur$ns &$ assis& &*e /earning pr$:ess. Gn

Bigure 2.2= &*e resu/& )r$9 an $u&pu& neur$n is )ed <a:A in&$ a neur$n in &*e *idden /a0er.

!". ),*-/0/1 234,5

H varie&0 $) di))eren& /earning 9$des e>is& )$r de&er9ining *$7 and 7*en &*e inpu&

7eig*&s $) &*e individua/ neur$ns are upda&ed 7i&*in a ne&7$rA. ;*e &0pes $) /earning are

ei&*er supervised $r unsupervised. Hs s&a&ed ear/ier= &*e unsupervised /earning is :urren&/0

&*e 9$s& unAn$7n &0pe $) /earning. ;*e /earning ra&e $) a ne&7$rA dras&i:a//0 e))e:&s &*e

i&s per)$r9an:e.

11

!"#"$ %&'()*+,(- /(0)1+12

Learning in a su,er-ise. mo.e starts wit3 a 4om,arison o5 t3e networ6’s generate.

out,uts an. t3e .esire. out,uts. 9n,ut weig3ts o5 ea43 neuron are a.:uste. to minimi;e

an< .i55eren4es 5oun.. =3is ,ro4ess is re,eate. until t3e networ6 is .eeme. to be a44urate

enoug3. @5ter t3e training ,3aseA t3e neurons’ weig3ts are t<,i4all< 5ro;enA w3i43 allows

t3e networ6 to be use. reliabl<. =o better a.a,t to slig3t -ariationsA t3e learning rate 4an

be lowere.. Bne o5 t3e most im,ortant t3ings to .o w3en training a networ6 is to

4are5ull< 43oose t3e .ata use. 5or training. =<,i4all< .ata is se,arate. into a training set

an. a mu43 smaller test set. =3e training set is use. to train t3e networ6 to ,er5orm a tas6.

=3e test set is use. to -eri5< t3at t3e networ6 is able to generali;e w3at it 3as learne. to

slig3t -ariations. Cit3out t3is se,aration o5 .ata setsA one woul. not be able to 6now i5

t3e networ6 sim,l< memori;e. t3e .ata set or not.

!"#"! 31,&'()*+,(- /(0)1+12

Dnsu,er-ise. learning is ,er5orme. wit3out an< 5orm o5 eEternal rein5or4ement.

=3is learning mo.e re,resents a sort o5 en. goal 5or s<stems .esigners. Dsing t3is

met3o.A t3e s<stem tea43es itsel5 b< itsel5. =3e networ6 4ontains wit3in itsel5 a met3o. o5

.etermining w3en its out,uts are not w3at t3e< s3oul. be. =3is met3o. o5 learning is not

nearl< as well un.erstoo. as t3e su,er-ise. met3o.. 9t reFuires t3at t3e networ6 learn

online. Current wor6 3as been limite. to sel5Horgani;ing ma,sA w3i43 learn to 4lassi5<

in4oming .ata. Iurt3er .e-elo,ments wit3 t3is t<,e o5 learning woul. 3a-e uses in man<

situations w3ere a.a,tation to new in,uts is reFuire. regularl<.

"2

!"#"$ %&'()*)+ -'.&/

The learning rate o/ a networ1 is deter4ined 56 4an6 /actors. 9etwor1 architecture;

si<e and co4=le>it6 =la6 a 5ig role in the s=eed at which the networ1 learns. ?nother

/actor that a//ects the learning rate is the learning rule or rules e4=lo6ed. @low and /ast

learning rates each haAe their =ros and cons. ? lower rate will o5Aiousl6 ta1e longer to

arriAe at a 4ini4u4 error at the out=ut. ? /aster rate will arriAe 4ore Buic1l6; 5ut has a

tendenc6 to oAershoot the 4ini4u4. @o4e learning rules use the 5est o/ 5oth worlds; and

start o// with a high learning rate; and lower it graduall6 until a 4ini4u4 is reached.

!"#"# 01221) %&'()*)+ %'3/

Learning laws goAern how the in=ut weights o/ neurons within the networ1 are

4odi/ied. T6=icall6 the error at the out=ut is =ro=agated 5ac1 through the Aarious la6ers

o/ the networ1; adDusting the weights as it goes. Eow the error is =ro=agated 5ac1 is the

4aDor di//erence. The /ollowing; all /ro4 F"GH; are so4e laws co44onl6 used 56 networ1

architects.

!"#"#"4 5&667/ -89&

Ee55’s rule was the /irst general rule /or u=dating weights. Jt states; KJ/ a neuron

receiAes an in=ut /ro4 another neuron; and i/ 5oth are highl6 actiAe L4athe4aticall6 haAe

the sa4e signM; the weight 5etween the neurons should 5e strengthened.N Ee55 o5serAed

that 5iological neural =athwa6s are strengthened each ti4e the6 are used; and this rule is

designed to si4ulate that e//ect. Oost o/ the other rules 5uild u=on this /unda4ental law.

?s an e>a4=le o/ how this rule wor1s; su==ose a neural networ1 is 5eing trained to

control the acceleration o/ a car. @u==ose /urther that the networ1’s in=uts are the 5ra1e

and gas =edal =ositions 5eing as o=erated 56 a hu4an driAer. The acceleration and

"#

$e&ele(ation o. t/e &a( &an 0e &ompa(e$ 3it/ t/e $esi(e$ o5tp5t o. t/e $(i6e(. 8o3

s5ppose t/e $(i6e( o. t/e &a( 3ante$ to slo3 $o3n9 an$ p5s/e$ t/e 0(a:e. I. t/e o5tp5t o.

t/e ne5(al net3o(: 3as to $e&ele(ate9 t/an an< inp5t 3ei=/ts9 3/i&/ a >$e&ele(ate?

&omman$ 3as passe$ t/(o5=/9 s/o5l$ 0e in&(ease$. @/is 3o5l$ positi6el< (ein.o(&e t/e

a&&epta0le 0e/a6io( o. t/e net3o(:.

!"#"#"! $%& (&)*+ ,-)&

@/e $elta (5le is one o. t/e most &ommon lea(nin= (5les9 an$ is a 6a(iation o. Ae00Bs

C5le. It is also :no3n 0< se6e(al ot/e( names9 in&l5$in= t/e Di$(o3EAo.. Fea(nin= C5le

an$ t/e Feast Gean HI5a(e Fea(nin= C5le. It 3o(:s 0< t(ans.o(min= t/e e((o( at t/e

o5tp5t 0< t/e $e(i6ati6e o. t/e t(ans.e( .5n&tion. @/e (es5lt o. t/is t(ans.o(mation is 5se$

to a$J5st t/e inp5t 3ei=/ts asso&iate$ 3it/ t/e p(e6io5s la<e(s o5tp5ts. @/e t(ans.o(me$

e((o( (es5lt is p(opa=ate$ 0a&: t/(o5=/ all o. t/e la<e(s. Fee$E.o(3a($9 0a&:Ep(opa=ation

net3o(:s 5se t/is met/o$ o. lea(nin=.

!"#"#". $%& /0+12&3* (&45&3* ,-)&

@/e G(a$ient Mes&ent (5le is simila( to t/e Melta C5le in t/at t/e $e(i6ati6e o.

t(ans.e( .5n&tion mo$i.ies t/e o5tp5t e((o(. An a$$itional p(opo(tional &onstant (elate$ to

t/e lea(nin= (ate is a$$e$ to t/e mo$i.<in= .a&to( 0e.o(e t/e 3ei=/ts a(e a$J5ste$. @/is

met/o$ in its 0asi& .o( is :no3n to /a6e a slo3 (ate o. &on6e(=en&e. Osin= a 6a(<in=

lea(nin= (ate as 3as mentione$ 0e.o(e &an miti=ate t/is.

!"#"#"# 67%73&384 9&+0323: 9+;

@/is lea(nin= la3 is 5se$ .o( 5ns5pe(6ise$ net3o(:s. @e56o Po/onen 3as inspi(e$

0< lea(nin= in 0iolo=i&al s<stems9 an$ t/5s &ame 5p 3it/ t/e la3. Dit/ t/is la39 ne5(ons

&ompete .o( t/e oppo(t5nit< to lea(n. @/e ne5(on 3it/ t/e la(=est o5tp5t is t/e 3inne(9

14

and gets to update its weights and possibly some of its neighbors. 8sually the

neighborhoods start large, and shrink as training progresses.

!.# $%&A Implementations

Currently, most neural network research and testing is done using software

simulators. =oftware implementations allow for easy analysis of network behaviors.

Additionally, prediction-style problems in many cases do not require an embedded

hardware application. However, hardware neural networks can offer many advantages.

An optimiCed hardware implementation can yield better performance than a software

configuration running on a standard microprocessor. Additionally, a hardware

implementation can allow for applications that would be difficult to achieve in a software

set-up, such as with remote sensing applications. Designing for an FPGA also offers

many advantages, as discussed in Chapter H.

The ability of FPGAs to be re-programmed offers several specific advantages.

Jarious techniques in the category of “density enhancement” aim to increase the amount

of “effective circuit functionality per unit circuit area” [1N]. One way to accomplish this

is to separate out the various stages of the networkQs learning algorithm onto different

regions of the FPGA. Another way is to use optimiCed constant-coefficient multipliers to

handle the weighting calculations of the neuronQs inputs. These calculations will be fast.

In a training situation, these constant weights can be changed in under 6T !s [1N].

FGPAs also allow for the hardware implementation of artificial neural networks that

can dynamically adUust their topology. This allows for more complex learning algorithms

to adUust the topology, resulting in a more sophisticated final network.

! ! "#

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"#

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1#

This thesis studies the implementation of the exponential function in an FPGA using

C;RDIC. Though not as common as hyperbolic tangent, there are applications where the

exponential function is used as a transfer function. Eu and Fatalama used the

exponential function as a transfer function in their implementation of a neural network

that acted as an associative memory. I1JK Similarly, Malgamuge used the exponential

function in the implementation of a defuzzication approximator. I19K.

1#

!"#$ter 3 FPGA.

Any designer faces a number of different onto which the system can be

implemented. Each platform comes with a set of benefits and tradeoffs. The nature of the

system in addition to its environment need to be taken into account when choosing a

platform.

3.0 1e.234 1ec2.264.

One approach is to reali?e the design as a software program and implement it using a

microprocessor of some kind. There are numerous architectures that can be chosen, each

with its own benefits. It can be easy to find one that is suited for the design. This

approach does not have any special manufacturing costs associated with itB the only cost

comes for the purchase of the processors. Cowever, this techniDue is best suited for

applications that are mostly seDuential in nature. For applications that are parallel in

nature, a custom hardware-based design can offer much in the way of performance

benefits.

Once the designer has elected to use a custom hardware implementation, the type of

implementation must then be chosen. At the lowest level, a fully custom integrated circuit

can be designed at the transistor level. This offers the designer the most amount of

fleGibility, however design costs can be higher due to the compleGity of the

implementation and fabrication of the design. An Application-Hpecific Integrated Circuit

(AHIC) can alternatively be employed to reali?e the design. Lather than designing at the

transistor level, the designer is presented with a library of logic gates with different

performance and power characteristics that can all be used in the design. Hince the design

! ! "#

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"#

3.# FPGA Structure

!"#

!"#

!"# !"#

BlockRAM

)elay-Locked Loop

)elay-Locked Loop

)elay-Locked Loop

)elay-Locked Loop

234 Logic

234 Pins

BlockRAM

BlockRAM

BlockRAM

Mul

tiplie

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tiplie

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!i#$r& 3.*+,nt&rnal 1tr$2t$r& 34 a Xilinx Spartan-3 !:;< =>?.

$%e standard -P/A %as t%ree 1ain co1ponents6 con7igura:le logic :locks= I/O

:locks= and a progra11a:le interconnectA Bac% co1ponent plays a role in alloDing 7or

t%e Dide Eariety o7 %ardDare designs t%at can :e i1ple1ented in -P/AsA -igure FAG

s%oDs a :lock-leEel diagra1 o7 t%e Earious co1ponents t%at 1ake up an -P/AA

$%e con7igura:le logic :locks IJLBsM are D%ere t%e actual logic 7unctions speci7ied

:y t%e designer are i1ple1entedA In 1ost -P/A designs= t%e con7igura:le logic :locks

"#

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22

allo&ing t+e -ignal to be properly capt3red -o it i- pre-entable to t+e re-t o5 t+e FG89:

T+e o3tp3t logic allo&- 5or optional b355ering in a 5lip-5lop= or t+e -ignal can be directly

-ent to t+e pin:

Be5ore any -ignal lea?e- or enter- t+e c+ip= it pa--e- t+ro3g+ an electronic inter5ace

co@ponent t+at deter@ine- t+e electrical c+aracteri-tic- o5 t+e -ignal and control t+e

-a@pling o5 any inp3t ?al3e:

Be-ide- t+e-e t+ree ba-ic co@ponent-= @any ne&er F8G9- pro?ide additional

5acilitie- to @ake t+e de-ign proce-- -i@pler: 9n early addition &a- large array- o5 block

SR9D t+at can be 3-ed 5or data -torage: C+aining toget+er CLB- 5or -i@ple data -torage

can be c3@ber-o@e and area ine55icient= -o 3-ing t+e block SR9D can lea?e @ore c+ip

area 5or t+e +ard&are de-ign: Fa-t carry logic i- o5ten a?ailable &+ic+ allo&- 5a-t adder

de-ign- -3c+ a- carry looka+ead adder- to be i@ple@ented: So@e de-igner- are taking

t+at idea a -tep 5or&ard and i@ple@enting -tatic @3ltiplier- or ot+er 3nit- dedicated to

per5or@ing -i@ple arit+@etic operation-: Ne&er de-ign- can incl3de proce--or- -3c+ a-

t+e 8o&er8C= allo&ing -o5t&are and +ard&are de-ign- to eHi-t on t+e -a@e c+ip:

3.3! #ilin' Spartan-3

T+e XilinH Spartan-3 i- t+e plat5or@ 3-ed 5or t+e de-ign- di-c3--ed in t+e 5ollo&ing

c+apter-: T+e Spartan-3 3-e- SR9D cell- to -tore t+e progra@@ing in5or@ation: Since

t+e SR9D cell- lo-e t+eir -tate &+en t+e po&er -3pply i- t3rned o55= t+ey @3-t be

reprogra@@ed eac+ ti@e t+e c+ip i- po&ered on: T+i- reK3ire- t+e progra@ to be -tored

in a non?olatile 5or@at t+at can be tran-lated onto t+e F8G9:

23

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Figure 3.*—Block diagram of a 5lice in a Spartan-3.

The Spartan-3 CLBs are broken up into two slices. Figure 3.2 shows what a slice

looks like. Each slice contains two two-variable L?Ts and a multiplexer that selects

between the two. The output of each slice can be any function of five variables, or for

some restricted functions, as many as nine variables can be used. An additional

24

$%ltiple+er i- %-ed to -elect bet2een t4e o%tp%t- o5 t4e t2o -lice-6 T4i- enable- eac4 CLB

to operate on any 5%nction o5 -i+ =ariable-> or a re-tricted cla-- o5 5%nction- o5 %p to 1@

=ariable-6 Eac4 -lice al-o contain- carry and control logic t4at 5acilitate t4e

i$ple$entation o5 arit4$etic 5%nction-6 Fig%re 363 -4o2- 4o2 t4e $%ltiple+er- are %-ed

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can be con5ig%red eit4er a- latc4e- or 5lip-5lop-6

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$

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!igure (.(*Block diagram o3 a Comple6 7ogic Block 8C7B9 in a ;partan=(.

T4e Spartan-3 contain- a n%$ber o5 block REJ- de-igned to e55iciently -tore

relati=ely large a$o%nt- o5 data6 Eac4 block contain- 1KK o5 data -torage> and anot4er 2K

5or optional parity c4ecking6 Eac4 block %-e- SREJ cell- 5or -torage6 Eac4 block can

"#

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2#

!h#$ter 4 The !+,-.! Algorithm

The COrdinate Rotation DIgital Computer (CORDIC) algorithm is a technique that

can be used to compute the value of trigonometric functions. CORDIC differs from other

methods of computation because it can be easily implemented using only addition,

subtraction and bit shift operations. It is not as fast as table-based methods, but it can use

significantly less chip area, making it desirable for application where area is more

important than performance.

4.6 7#89gro:;<

The CORDIC algorithm was first proposed by Volder in his paper GThe CORDIC

Trigonometric Computing Technique,H published in 1JKJ L2M. It was originally intended

to be used for real-time airborne computation, but has since found other applications. In

1J71, Walther demonstrated that the algorithmPs domain could also be expanded beyond

computing trigonometric equations to also include hyperbolic and linear (multiply-add-

fused, etc.) functions.

Walther presented a possible hardware implementation using three !-bit registers,

three !-bit adderRsubtractors, three shifters, and a small look-up table. Volder presented a

serial design containing three !-bit"registers, three 1-bit adderRsubtractors, and a number

of shift gates that specified which bits from the registers get fed into the

adderRsubtractors. This thesis will explore both implementations and analySe the

capability of this algorithm to be used in an artificial neural network.

"#

4"# $%&'()*+,-.%/'

The algorithm operate0 in one o2 t3o mode05 Rotation or 7ectoring. The t3o mode0

determine 3hich 0et o2 2unction0 can ;e computed u0ing the algorithm. In Rotation mode=

the !" and #" component0 o2 the 0tarting >ector are input= a0 3ell a0 an angle o2 rotation.

The hard3are then iterati>el? compute0 the !@ and #@component0 o2 the >ector a2ter it ha0

;een rotated ;? the 0peci2ied angle o2 rotation.

In 7ectoring mode= the t3o component0 are input= and the magnitude and angle o2

the original >ector are computed. Thi0 i0 accompli0hed ;? rotating the input >ector until it

i0 aligned 3ith the !"aAi0. B? recording the angle o2 rotation to achie>e thi0 alignment=

3e kno3 the angle o2 the original >ector. Once the algorithm i0 complete= the !@

component o2 the >ector i0 eEual to the magnitude o2 the 0tarting >ector.

The CORDIC algorithm accompli0he0 it0 computation0 ;? u0ing onl? add0=

0u;tract0= and 0hi2t0. Thi0 i0 done ;? iterati>el? rotating the input >ector and 0lo3l?

con>erging on the 2inal rotated >ector. Thi0 i0 done in a 0erie0 o2 3ell@de2ined 0tep0. The

2ir0t rotation 0tep 0ee0 the >ector rotated !

! radian05

H4.1K

! !

!!

= ±x0

= #0#$% !

0± "

&( )

x!

=!!0

= #0'(# !

0± "

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Lhere !0

and y0 repre0ent the input >ector aligned at the origin 3ith magnitude !

!

and angle !!5

H4."K

!

!i = #i cos!i

$i = #i sin!i

In each 0u;0eEuent 0tep= a ne3 angle o2 rotation !i i0 determined 0uch that5

! ! "#

$%&'(! !!!" !"#!$ %!!# $&!'()*)+!% , !

)*i,!-.,/-i0/i12!i,!0-30i45!i2!45516i27!/*.!-1/4/i12!0450354/i12,!8.-91-:.;!i2!.40*!,/.8!

/1!<.!4001:85i,*.;!3,i27!125=!42!4;;!$1-!,3</-40/(!42;!4!,*i9/&!

!!

!!

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#!

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40

!"#! $%&'()*(&+(,

The algorithm is now fully defined, and it will now be demonstrated that the

algorithm converges on the previously noted functions. The specific region of

convergence will also be shown.

!"#"-!./(,$%&'()*(&+(,$%&0i2i%&,

Assume that the CORDIC algorithm is in vectoring mode. Let !! be the angle of the

input vector after the !th iteration of the algorithm. The algorithm tries to reduce the angle

of the input vector. Therefore, after step i+! , the angle of the vector will change such

that

(4.25) !!!!"!# !

!!"

!

where !!! is the rotation performed in the !th iteration of the algorithm. In order for

the algorithm to converge in " iterations, then all subsequent iterations must bring ! to

within !!!!!!

of zero. If this is the case, then when the "th iteration completes, the input

angle will be zero. Since the rotations accumulate, the following condition is derived:

(4.26)

!!

!!! !

"

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In order for the algorithm to converge, the condition in (4.26) must hold when the

algorithm first begins:

(4.27)

!!

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!

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To find the domain of initial values for which the algorithm converges, the above

inequality is solved:

! ! "1

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With the algorithm now fully defined, and its convergence proven, the accuracy and

precision of the algorithm will now be discussed. Generally speaking, for each iteration

of the algorithm, an additional bit of accuracy is obtained.

>rror creeps into the results from many sources. ?aturally, since there is not an

infinite number of bits available to any real hardware device, rounding errors are inherent

to any implementation. Additionally, since there are a finite number of iterations to any

real-world implementation of the algorithm, the desired rotation angle can never be fully

realiBed. This results in an angle approximation error.

!"#"/ 0&12'3%(4*526'272n8(83.n*

The CORDIC algorithm operates using bit-shifts, the natural representation for any

number used in the algorithm is going to be a fixed-point representation rather than

floating-point. A fixed point number is a scaled integer, where the binary point is implied

to be ! positions to the left of the JKL. As a result, the integer is 2! times larger than the

number it is representing. This is similar to storing 2.N4 as 2N4. This scale, combined

with the number of bits available completely determines the range and precision available

to all numbers in the algorithm. The scale determines how many bits are available to the

left and right of the binary point.

As the binary point moves to the right, greater ranges of numbers are available, but

the scale becomes coarser, with larger gaps between adOacent numbers. Jikewise, as the

binary point moves to the left, the scale is finer, but the range of possible numbers is

smaller.

! ! ""

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=X

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"#

5.1.1 The Control Unit

$he 'ontrol unit i/ re/pon/i1le for regulating the flo5 of data through the CORDIC

unit. $he unit i/ a finite /tate ma'hine ha>ing three /tate/? a/ /ho5n in Figure 5.2. $he

default /tate for the unit i/ the IDCD /tate. In thi/ /tate? the regi/ter/ are not loading? and

the unit i/ /taE/ in thi/ /tate until the S$GR$ /ignal i/ a//erted. Hhen the S$GR$ /ignal

i/ a//erted? the unit mo>e/ into the IRDCOGD /tate.

In the IRDCOGD /tate? the regi/ter load /ignal i/ a//erted? and the IJI$ /ignal i/

al/o a//erted? 'au/ing the initial >alue/ to 1e loaded into the regi/ter/ Kthe/e >alue/ are

repre/ented a/ LM? NM? and OM in Figure 5.PQ. $he unit then ad>an'e/ to the CORIS$D

/tate. $he regi/ter load /ignal/ remain a//erted? 1ut the IJI$ /ignal i/ not a//erted. G/ a

re/ult? the regi/ter/ are loaded 5ith the >alue/ from the 'orre/ponding adder/? rather than

the input >alue/. $he unit maintain/ an internal iteration 'ount? and 5hen the/e >alue/ are

eTual? the 'ontrol unit mo>e/ 1a'U into the IDCD /tate? 5ith the DOJD /ignal a//erted?

/ignifEing that the >alue/ output 1E the regi/ter/ are >alid. $a1le 5.2 /ho5/ the

un'onditional output/ for ea'h /tate. Other /ignal/? /u'h a/ the looUVup ta1le addre//?

SWGR$? and SSX /ignal/ >arE and are 'ontinuou/lE updated 5hile in the CORIS$D

/tate. $he logi' 1ehind the /tate tran/ition/ i/ /ho5n in Figure 5.Y.

!DL$

%R$L'AD C'M%+T$

SHAMT 0 ST'%1ALSTART

!"#$%&'5)*+,-.-&'/".#%.0'12%'-3&'4.%.55&5'6789:6'$;"-)'

5#

! "#$%! &'%$()#! *(+&,-%!

"."-! # 1 #

#(.%! 1 # #

$#! # 1 1

-/012!3456,7897:;<;97/1!897<=91!>7;<!9><?><@!A9=!2/8B!@</<2!;7!<B2!?/=/1121!:2@;C74!

! "

###$

! "

###$

$%&

'()*+

'+),+

!

D;C>=2!3436F</<2!<=/7@;<;97!19C;8!A9=!<B2!?/=/1121!*('#"*!>7;<4!

The generation of the SHAMT signal is complicated by the need to perform repeat

iterations, and the need to wait one cloc> cycle to read hyperbolic tangent data from the

L@T. Bigure 5.4 shows the logic behind the SHAMT signal, as well as the other signals

that are state independent (S@BXH, S@BI, ADDR, and DONE). The subtract signals

S@BXH and S@BI are determined by the sign of the I register, since the PORDIP unit

is operating in rotation mode. Therefore, the sign bit of the I register is connected

directly to the subtract inputs of the corresponding adders.

The SHAMT register contains the shift amount, which also corresponds to the

current iteration count, which is then connected to the X and H registers. Since data from

the loo>-up table ta>es one cloc> cycle to be retrieved, SHAMT is reTuired to lag one

cycle behind the ADDR signal, which is fed to the loo>up-table. This is shown as a direct

connection between the output of the ADDR register and the input of the SHAMT

! ! "#

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),4)!'/-$%6%/)(!')(!<4=;%*!

K,%/!LM1N:!64)-,%(!),%!-./()4/)!L:O@P1QE!),%/!),%!2O>R!('&/4=!'(!4((%$)%5E!

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DO12

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5"6# -&! 2+'+2,! ()3*!

789# &&3! 22&! 5&)&*!

9:&;# (! 32! ()(*!

<=5># &! .! &2)5*!

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/01!2312!31456317189:!;<3!906:!=<7><8189!<;!901!?@ABC?!5869!231!D1926E1D!68!/2FE1!

5)3)!/01!=<893<E!5869!2==<589:!;<3!&2*!<;!901!:E6=1:!5:1D!FG!901!189631!D1:6H8)!

5.1.2!The Shift -egisters

/01!I!28D!J!31H6:913:!3145631!:06;9!=2>2F6E69G)!K68=1!901!:06;9!27<589!68=312:1:!L690!

12=0!6913296<8!<;!901!2EH<36907'!2!:928D23D!:68HE1MF69!:06;9!31H6:913!=288<9!F1!5:1D)!N!

31H6:913!=2>2FE1!<;!:06;968H!2!O2362FE1!27<589!6:!81=1::23G)!P58D271892EEG'!90131!231!9L<!

2>>3<2=01:!9<!D1:6H868H!:5=0!2!31H6:913)!/01!12:61:9!28D!7<:9!2312M=<8:=6<5:!6:!9<!

>13;<37!2!:68HE1!<81MF69!:06;9!>13!=E<=Q!=G=E1!28D!31>129!2:!81=1::23G!5896E!901!O2E51!02:!

F118!:06;91D!FG!901!D1:631D!27<589)!/01!:68HE1!F69!:06;9!=28!F1!023DML631D'!768676R68H!

2312!31456317189:)!/06:!2>>3<2=0!3145631:!901!=<7>59296<8!9<!>25:1!5896E!901!:06;968H!6:!

=<7>E191)!/06:!6:!5:1D!2:!>239!<;!901!2312!<>9676R296<8!H2681D!;3<7!901!F69M:1362E!

67>E17189296<8!D6:=5::1D!68!?02>913!+)!

C9!6:!>31;1331D!9029!901!:06;9!F1!>13;<371D!68!<81!=E<=Q!=G=E1)!/06:!=28!F1!

2==<7>E6:01D!5:68H!75E96>E1S13:'!28D!6:!6EE5:93291D!;<3!2!,MF69!31H6:913!68!P6H531!5)5)!P<3!

906:!D1:6H8'!L06=0!5:1:!32MF69!31H6:913:'!32! 32 ! #75E96>E1S13:!231!5:1D!;<3!12=0!:06;968H!

5869)!/01!31H6:913:!02O1!9L<!<59>59:'!901!58:06;91D!<59>59!D631=9!;3<7!901!31H6:913'!28D!901!

:06;91D!<59>59'!L06=0!6:!901!<59>59!;3<7!901!75E96>E1S13:)!/01!KTNU/!:6H82E!=<893<E:!901!

27<589!FG!L06=0!901!<59>59!6:!:06;91D)!/01!:06;9!31H6:913!>13;<37:!28!236907196=!:06;9!

53

ope'a)*o+ )o e+,u'e p'ope' e.e/u)*o+ 0he+ +e2a)*3e 3alue, a'e u,e5. 7o+,e8ue+)l9: )he

;<= >)he ,*2+ b*)@ *, /o++e/)e5 )o )he ,h*A)e5 ou)pu), oA )he Bul)*ple.e', )o allo0 Ao' a

,*2+ e.)e+,*o+ )o o//u' 0he+ ,h*A)*+2.

!"#

$"# 0123

%H'FT*3+01230

123

0123

%H'FT*2+

%H'FT*1+

%H'FT*0+

D*3+

D*2+

D*1+

D*0+

CL/ %HAMT Figure 5.5—Design of the variable shift register.

Used Available Utilization

Slices CD 13:31F D.GH

Slice Flip-Flops I5 FI:IFJ D.FH

LUTs 1IF FI:IFJ D.IH

IOBs 1DJ FF1 JG.1H

BRAMs D 3F D.DH

GCLKs 1 K 1F.5H

Table 5.H—Device utilization for the parallel shift register.

The ,h*A) 'e2*,)e', u,e a ,*2+*A*/a+) po')*o+ oA )he 5e3*/e a'ea: 'ela)*3e )o )he 'e,) oA

)he 5e,*2+: a, ,ho0+ *+ Table 5.J. Mo)e )ha) )he )able o+l9 /o3e', a ,*+2le 'e2*,)e': a+5

)he'e a'e )0o ,h*A) 'e2*,)e', *+ )he )o)al 5e,*2+. The N 'e2*,)e' *, a ,)a+5a'5 'e2*,)e'

0*)hou) ,h*A)*+2 Au+/)*o+al*)9.

5.1.$ %&e )**+u- %a/0e

The lookup )able /o+)a*+, )he 3alue, oA )he a'/ h9pe'bol*/ )a+2e+) +e/e,,a'9 Ao' ea/h

*)e'a)*o+ oA )he al2o'*)hB. P 7 p'o2'aB 0'*))e+ Ao' )ha) pu'po,e 2e+e'a)e, )he QRSL Ao'

)he )able. The p'o2'aB u,e, )he 7 Ba)h l*b'a'9 Au+/)*o+, *+ /o+Uu+/)*o+ 0*)h a A*.e5V

54

point conversion function to output a 1HDL file containing a description of the lookup

table in fixed-point notation.

"#e% &'a)lable ",)l)-a,)o/

0l)1e# 0 13,312 0.0%

0l)1e 2l)p42lop# 0 26,624 0.0%

L"T# 0 26,624 0.0%

789# 38 221 17.2%

9:&;# 1 32 3.1%

<=L># 1 8 12.5%

Table 5.5ABe')1e u,)l)-a,)o/ DoE ,he paEallel lookup ,able.

The presence of the lookup table has essentially zero impact on the area requirements

for the unit, since the entire table can be synthesized into a single LRAM, as shown in

Table 5.5.

5.1.$ Design Summar1

2)HuEe 5.IA0l)1e# u#e% bJ ,he 'aE)ou# 1oKpo/e/,# oD ,he paEallel =8:B7= u/),.

The entire design uses very little of the QPSA’s resources, and Qigure 5.6 shows that

much of the QPSA’s slices are used up by the X and Y shift registers. The large

multiplexers required by the design result in massive resource requirements. Chapter 6

! ! ""

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H(0!IJ!6,(&5!10$!eK)/#*eL7!

M(!?I!,(e$)(,0'&!HA,(.!:!$e#e)(&L5!#*2&!)!NEOPDMF!393*e5!(.e!)*-0$,(./!A,**!()Be!?;!

3*03B!393*e&!(0!30/#*e(e7!M(!(.e!(.e0$e(,3)*!/)K,/2/!3*03B!1$e42e'39!01!Q"7R!STU5!(.e!

2',(!A,**!()Be!R7;"!!&!(0!30/#2(e!(.e!1,')*!V)*2e7!

5.2 $imulation Results

W.,&!&e3(,0'!#$e&e'(&!(.e!$e&2*(&!01!&,/2*)(,0'&!#e$10$/e+!2&,'-!(.e!+e&,-'!&#e3,1,e+!

,'!"7I7!W.e!+e&,-'!2&e&!?:!6,(&!(0!$e#$e&e'(!e)3.!A0$+5!A,(.!;!6,(&!10$!(.e!,'(e-e$!#)$(!01!

(.e!'2/6e$5!)'+!:X!6,(&!10$!(.e!1$)3(,0')*!#)$(!01!(.e!'2/6e$7!W.2&!(.e!V)*2e&!02(#2(!69!

(.e!Y5!Z5![5!)'+!(.e!)++e$!(.)(!30/#2(e+!(.e!eK#0'e'(,)*!12'3(,0'!)$e!e11e3(,Ve*9!&3)*e+!

2#!69!)!1)3(0$!01!::X7!W.e!&,/2*)(e+!3*03B!$2'&!)(!IRR!STU7!

5.2.1 $imulation 1: Computing e With CORDIC ;rowth

Error

W.e!1,$&(!&,/2*)(,0'!#e$10$/e+!+e/0'&($)(e&!(.e!e11e3(!01!(.e!CDEFGC!-),'!K"7!W0!

30/#2(e!(.e!eK#0'e'(,)*!12'3(,0'!e$5!(.e!Y!$e-,&(e$!/2&(!6e!,',(,)*,Ue+!A,(.!I5!(.e!Z!

$e-,&(e$!A,(.!R5!)'+!(.e![!$e-,&(e$!A,(.!(.e!+e&,$e+!)$-2/e'(!(0!(.e!eK#0'e'(,)*!12'3(,0'7!

W.,&!&,/2*)(,0'!)((e/#(&!(0!30/#2(e!(.e!V)*2e!01!e5!&0!)'!,',(,)*!V)*2e!01!I!,&!#*)3e+!,'(0!

(.e![!$e-,&(e$7!

5#

!"#$%& ()*+,&-$./- 01 2 304&.5"6 -"6$.2/"07 2//&68/"7# /0 9068$/& /:& ;2.$& 01 e) <- 2 %&-$./ 01

=>,?@= #%0A/:B /:& 1"72. 9068$/&4 ;2.$& "- "7299$%2/&)

$he results of this simulation are shown in 3igure 5.6. $he algorithm iterate7 for a

total of 89 times :in;lu7ing the <R>?OAD state an7 the two repeat iterations reDuire7 in

the hEperFoli; 7omainG. $he final heHa7e;imal Ialues in the J an7 K registers are

L9625NC5L# an7 P3Q262ARL# respe;tiIelE. Shen ;onIerte7 to 7e;imal an7 s;ale7

a;;or7inglET theE Fe;ome L.266QLP for the J register an7 P.Q688LP for the K register. $he

Ialue of the eHponential fun;tion is the sum of these two numFers: 2.25L2LPT whi;h

mat;hes the output of the > signal.

$he a;tual Ialue of e to four 7e;imal pla;es is 2.6LN8. $his simulation 7emonstrates

an error in ;omputation FE P.9#6L. $his is a result of the CORDIC magnitu7e error fa;tor

"i 7is;usse7 in 9.2 an7 illustrate7 in 3igure 9.2. In or7er to pro7u;e a;;urate resultsT the

J register nee7s to Fe preWs;ale7 FE the gain fa;tor ".

5.#.#!Simulation #. Computing e Compensating for

CORDIC :rowth

In or7er to ;ompute an a;;urate Ialue of eT the growth oFserIe7 in 9.2 must Fe

a;;ounte7 for. $o pro7u;e an uns;ale7 final IalueT the initial Ialue must Fe 7iIi7e7 FE

the growth fa;tor. $he formula use7 to ;ompute the amount of growth is shown in :9.28G.

A pre;ompute7 Ialue is shown in $aFle 9.L. 3or this simulation rather than initialiXing J

with LT J will Fe initialiXe7 with the heHa7e;imal Ialue L85L>N62L#T whi;h eDuals

L.2P65LP. K is again initialiXe7 with P an7 Y with L.

5#

!"#$%& ()*+,&-$./- 01 2 304&.5"6 -"6$.2/"07 8069$/"7# /:& ;2.$& 01 e) <= 2880$7/"7# 10% >?,@A>

#%0B/:C /:& 1"72. 8069$/&4 ;2.$& "- 288$%2/&)

$%& '&(ult( o- t%i( (imulation a'& (%o2n in 3igu'& 5.6. $%& -inal 7omput&9 :alu& o- e

i( output on t%& ; <u(. =t( %&>a9&7imal :alu& 2@#;152B1C 7on:&'t( to 2.#1631EF 2%i7%

mat7%&( t%& a7tual :alu& o- e. G%&n taH&n to 3E 9&7imal pla7&( t%& :alu& output in ; i(

2.#1626166EE211EEEEEEEEEEEEEEEEE1EF 2%i7% 9i--&'( -'om t%& '&al :alu& o- e <I onlI

E.EEEEEEE515C2E5E165E633EEE1E. $%& onlI 2aI -o' t%i( &''o' to <& '&9u7&9 2oul9 <& to

u(& mo'& p'&7i(ion in t%& '&gi(t&'(. Gi9&ning t%& '&gi(t&'(F o' (%i-ting t%& <ina'I point to

t%& l&-t 7an a7%i&:& t%i(. =n a99ition to allo2ing mo'& p'&7i(ion in t%& '&(ult(F it al(o

allo2( g'&at&' p'&7i(ion -o' t%& :alu&( (to'&9 in t%& a'7 %Ip&'<oli7 tang&nt looHup ta<l&.

!"#"$ %&'()*+&,-.$/.0,'1(+&-2.!34.

=t i( al(o impo'tant -o' t%& unit to 7omput& t%& :alu& o- t%& &>pon&ntial -un7tion -o'

n&gati:& a'gum&nt(. Sin7& t%& 9omain o- 7on:&'g&n7& -o' t%& algo'it%m i( (Imm&t'i7

a<out EF %al- o- t%& po((i<l& a'gum&nt( a'& n&gati:&. $%i( (imulation 7omput&( t%& :alu&

o- e–1

. L i( initialiM&9 2it% 1.2E#51E to &n(u'& an un(7al&9 '&(ultF an9 N i( initialiM&9 2it%

E. $%& O '&gi(t&' 7ontain( t%& a'gum&nt -o' t%& &>pon&ntial -un7tion an9 i( t%u( initialiM&9

to –11E P3EEEEEEE1C in 2Q( 7ompl&m&nt notationR.

!"#$%& ()D+,&-$./- 01 2 304&.5"6 -"6$.2/"07 8069$/"7# /:& ;2.$& 01 e

EF)

5#

$he simulation results presented in Figure 5.6 sho7 that the 89R;<8 unit is a=le to

handle the negative argument. $he final value in the @ register A05@C;5#81EF

corresponds to 0.HEI#I6JH5JC10, 7hich is of the same accuracL as the computation for

e1.

5.2.$ Simulation $/ Computing Outside the Domain of

Convergence

Ms discussed in J.E, the 89R;<8 algorithm does not converge on an accurate

ans7er for all input values. $a=le J.H sho7s the domains of convergence for all the

computation domains supported =L the 89R;<8 algorithm. For the rotation mode, 7hich

this design uses, the domain of convergence is a limiter on the magnitude of the initial

value of N. <f N 7ere initialiOed 7ith a value 7hose magnitude is greater than 1.11#1I10,

then the final computed value 7ould =e incorrect. For this simulation, the P register is

again initialiOed 7ith 1.C0I510, and Q is again initialiOed to 0, =ut N is initialiOed to 5, so

that the unit 7ill attempt to compute e5.

!"#$%& ()*+,-&.$/0. 12 3 415&/6"7 ."7$/30"18 917:$0"8# 0;& <3/$& 12 e

() 6"89& 0;& "8"0"3/ <3/$& ( ".

1$0."5& 0;& 5173"8 12 918<&%#&89&= 0;& 917:$0&5 <3/$& ". "891%%&90)

$he simulation results sho7n in Figure 5.10 demonstrate that the 89R;<8 unit is

una=le to compute e5. $he final value output =L @ is H.056H10, 7hich is no7here near the

correct value A1J#.J1HC10F. H.056H10 acts is an asLmptote for the computed values of @.

9nce the initial values of N move outside the domain of convergence, the computed @

value rapidlL approaches H.056H10, and remains at that value no matter ho7 large a value

"#

$ is initiali+e- .ith. 1 similar as4mptote e7ists 8or .hen $ is initiali+e- .ith 9al:es that

are too negati9e. In this =ase> the ? 9al:es approa=h @.AB6#1@.

!"#! $%&&'()

The parallel -esign is a straight8or.ar- implementation o8 the CGHDIC eJ:ations.

?9en .ith the large register si+es> the -esign has a small 8ootprint insi-e the SpartanLA.

Mith iterations lasting one =lo=N =4=le> the per8orman=e is =onsistent. Oer8orman=e =an Pe

impro9e- P4 :sing 8e.er iterations> .hi=h :s:all4 entails :sing a smaller .or- si+e. The

sim:lations -emonstrate a==eptaPle a==:ra=4> espe=iall4 gi9en the area reJ:irements 8or

the -esign. Qor s4stems that reJ:ire an e9en smaller 8ootprint> Chapter 6 presents a

smaller> slo.er PitLserial implementation that 8:rther aims to re-:=e area reJ:irements P4

:sing 1LPit a--erRs:Ptra=tors an- simple shi8t registers.

! ! "#

Chapter 6 *he +erial Implementation

$!%t'a)*ht,-'.a'/!)012303ntat)-n!-,!th3!567895!a2*-')th0!)%!/)%:;%%3/!)n!5ha1t3'!

<=!>h)23!that!/3%)*n!'3?;)'3/!@3'A!2)tt23!-,!th3!BCD$E%!'3%-;':3%F!th3'3!0)*ht!G3!%-03!

a112):at)-n%!.h3'3!,;'th3'!a'3a!'3/;:t)-n!)%!n3:3%%a'A=!9t!.a%!-G%3'@3/!)n!<=H=I!that!th3!

t.-!@a')aG23J.)/th!%h),t!'3*)%t3'%!a::-;nt3/!,-'!ha2,!th3!'3%-;':3!'3?;)'303nt%!,-'!th3!

/3%)*n=!Th)%!:ha1t3'!1'3%3nt%!an!a2t3'nat3!/3%)*n!that!;%3%!G)tJ%3')a2!a')th03t):!a2-n*!.)th!

-n3JG)t!a//3'%!t-!3L3:;t3!th3!567895!a2*-')th0=!9t!.)22!G3!%h-.n!that!th)%!/3%)*n!

'3?;)'3%!,a'!23%%!-,!th3!BCD$E%!'3%-;':3%F!G;t!.)22!'3?;)'3!0-'3!t)03!t-!3L3:;t3=!

6.1 Design

!

!

X

!

BITC&T

'()*

+()*

SUB'+

#

!

SUB..(

)*

S/'T

+Sign

'Sign

atanh()T

BITC&T

!!i#$r& 6.1+,lo/0 1i2#r23 4or t6& 7&ri2l i38l&3&nt2tion o4 t6& C;<=>C 2l#orit63.

$%!%h-.n!)n!B)*;'3!"=HF!th3!-@3'a22!th3!/3%)*n!'30a)n%!'32at)@32A!;n:han*3/!.h3n!

:-01a'3/!t-!th3!1a'a2232!/3%)*n!%h-.n!)n!B)*;'3!<=H=!$22!th3!:han*3%!.3'3!0a/3!t-!th3!

)n/)@)/;a2!:-01-n3nt%!-,!th3!/3%)*n=!Th3!XF!YF!an/!Z!'3*)%t3'%!a'3!n-.!%tan/a'/!-n3JG)t!

%h),t!'3*)%t3'%!.)th!1a'a2232!2-a/!an/!1a'a2232!-;t1;t!:a1aG)2)tA=!Th)%!P331%!th3)'!)nt3'na2!

2-*):!%)0123!an/!'3/;:3%!a'3a!'3?;)'303nt%=!Th3!a//3'Q%;Gt'a:t-'%!a'3!n-.!'3/;:3/!t-!

-13'at)n*!-n!%)n*23JG)t!-13'an/%F!.h):h!a2%-!'3/;:3%!th3)'!:-0123L)tA=!Th3!a//3'%!a2%-!

"#

$%&'()& ( *+),-*+%, '.(' /(01/ '.1 $(223 %4',4' /% '.(' )' $(& 51 (,,+)16 '% '.1 &17' ,()2 %*

%,12(&6/8 9.)/ (++%:/ '.1 ;<-5)' (66)')%& '% 51 ,12*%2=16 %&1 5)' (' ( ')=18

>($. )'12(')%& 21?4)21/ '.1 @ (&6 A $2%//-0(+41/ '% 51 /.)*'16 53 '.1 $4221&' )'12(')%&

$%4&'8 9.1 ':% =4+'),+1712/ (''($.16 '% '.1 @ (&6 A 21B)/'12/ (++%: '.1 $%221$' 5)' '% 51

/1+1$'16 *%2 '.1 $%221/,%&6)&B 21B)/'128 C)&$1 '.1 21/4+'/ %* '.1 (66)')%& %2 /45'2($')%& (21

*16 5($D (/ '.1 /12)(+ )&,4'/ '% '.1 21B)/'12/E (& (66)')%&(+ C>@9 $%&'2%+ /)B&(+ (&6 <F#

=4+'),+1712 )/ &11616 '% $.%%/1 1)'.12 '.1 5)' /1+1$'16 *2%= '.1 21B)/'12 %2 '.1

$%221/,%&6)&B /)B& 5)'8 G)'.%4' '.)/ /)B&(+E 5)'/ $%=,4'16 ,210)%4/+3 )& '.1 )'12(')%&

:%4+6 51 *16 )&'% '.1 (6612/8 9.1 /)B& %* 1($. 21B)/'12 )/ /(016 ,2)%2 '% '.1 171$4')%& %*

1($. )'12(')%&E (++%:)&B *%2 (& (2)'.=1')$ /.)*' %* '.1 0(+41/ 51)&B *16 )&'% '.1 (6612/8

H =4+'),+1712 :(/ (+/% 4/16 '% (++%: '.1 $%221$' 5)' '% 51 *16 *2%= '.1 (2$ .3,125%+)$

'(&B1&' +%%D4, '(5+1 '% '.1 I-(66128 9.1 =4+'),+1712 (++%:/ '.1 +%%D4, '(5+1 '% 51 ,+($16

)& JKHL (&6 ,2101&'/ (&3 (66)')%&(+ $+%$D $3$+1 61+(3/ *2%= 51)&B )&'2%64$16 )&'% '.1

61/)B&E (/ :%4+6 51 '.1 $(/1 )* '.1 0(+41 :121 +%(616 )&'% ( /.)*' 21B)/'128 H/ 51*%21E '.1

$%&'2%+ 4&)' ,2%0)61/ '.1 (6621// )&'% '.1 +%%D4, '(5+18

9.)/ 61/)B& 4/1/ ( ;<-5)' :%26 /)M1E :)'. N 5)'/ *%2 '.1 :.%+1 ,(2' %* '.1 &4=512E (&6

<O 5)'/ *%2 '.1 *2($')%&(+ ,(2' %* '.1 &4=5128

Used Available Utilization

Slices #;P #;E;#< #8QR

Slice 2lip42lops #N; <"E"<N Q8SR

LUTs <S" <"E"<N #8QR

IOBs #;< <<# SP8TR

BRAMs # ;< ;8#R

<CL>s # O #<8SR

Table 6.ABOverall device utilization for the serial design.

! ! "#

T%&!'&()*&!+,)-)./,)01!203!,%&!4&3)/-!'&4)51!)4!4%061!)1!T/7-&!"898!T%)4!'&4)51!+4&4!

01-:!9;<!02!,%&!=C;S9@AAB4!/(/)-/7-&!4-)*&4C!/4!0DD04&'!,0!,%&!;#<!3&E+)3&'!7:!,%&!

D/3/--&-!'&4)518!T%)4!)4!/!3&'+*,)01!02!@F8GH8!I1!/''),)01C!,%&!=)-)1J!4:1,%&4).&3!3&D03,&'!

,%/,!/!K/J)K+K!*-0*L!23&E+&1*:!02!9;M8G!MO.!*/1!7&!+4&'8!T%&!D/3/--&-!'&4)51!,0D4!0+,!

/,!F@8A!MO.8!T%&!4)KD-)*),:!02!,%)4!'&4)51!!3&4+-,4!)1!-&44!*0K7)1/,)01/-!-05)*!'&-/:!

6%)*%!)1!,+31!/--064!203!2/4,&3!*-0*L!4D&&'48!

!"1"1 C%&'(%) +&,'

T%&!D/3/--&-!'&4)51!/--06&'!&/*%!),&3/,)01!,0!7&!*0KD-&,&'!)1!01&!*-0*L!*:*-&8!T%)4!

3&'+*&'!,%&!*0KD-&J),:!02!,%&!*01,30-!+1),8!T%&!46),*%!,0!/!4&3)/-!'&4)51!K&/14!,%/,!,%&!

1+K7&3!02!*-0*L!*:*-&4!3&E+)3&'!,0!*0KD-&,&!&/*%!),&3/,)01!'&D&1'4!01!,%&!603'!4).&C!

4)1*&!/--!(/-+&4!/3&!*0KD+,&'!01&!7),!/,!/!,)K&8!P3&()0+4-:C!,%&!4+7,3/*,!*01,30-!4)51/-4!

,%/,!'&,&3K)1&!6%&,%&3!&/*%!/''&3!)4!/'')15!03!4+7,3/*,)15!*0+-'!7&!&(/-+/,&'!&/*%!*-0*L!

*:*-&8!I1!,%&!4&3)/-!'&4)51C!,%&4&!(/-+&4!1&&'!,0!7&!'&,&3K)1&'!01*&!/,!,%&!7&5)11)15!02!

,%&!),&3/,)01!/1'!4/(&'!+1,)-!,%&!*+33&1,!(/-+&!)4!2+--:!*0KD+,&'8!T0!/**0KD-)4%!,%)4C!/!

1&6!4,/,&!)4!/''&'!,0!,%&!4,/,&!K/*%)1&!02!,%&!*01,30-!+1),C!/4!4%061!)1!Q)5+3&!"8#8!

63

IDLE PRELOAD

SETUPCOMPUTE

ST#RT

%ST#RT

&'T()T + ,1#). S/#0T 1 ,1&'T()T 1 ,1

&'T()T + ,1#). S/#0T + ,1

!"#$%& ()*+,-.-& /".#%.0 12% -3& 4&%".5 "065&0&7-.-"27 21 -3& 89:;<8 .5#2%"-30)

The IDL* and ./*LO1D states remain unchanged. The IDL* state is active when

the algorithm is not being executed. The ./*LO1D state is used to load the initial values

into the X, Y, and Z registers. The S*TF. state is the new state and is only active the

very first clock cycle of each iteration. In the S*TF. state, the values in the X, Y, and Z

registers are evaluated to determine the subtract and sign signals. These signals are saved

into registers for use during the remaining clock cycles of the current iteration. The

JOM.FT* state is active until all 32 bits have been computed. Once this happens, IDL*

becomes the active state, otherwise if more iterations remain, the machine returns to the

S*TF. state to begin execution of the next iteration.

1 new internal control value is also added, named BITJOT. Whereas SH1MT holds

the current iteration count, BITJOT holds the number of bits that have been processed

within the current iteration. When this counter rolls over to zero, then the active iteration

is completed.

6#

! IDL%! P'%LO)D! S%TUP! CO.PUT%!

INIT! $ % $ $

DON%! % $ $ $

PLD! $ % $ $

S0I1T! $ $ % %

T2345!6789S:2:5!;<:=<:>!?;@!:A5!>5@B24!C;D:@;4!<DB:7!

To manage the new shift registers, a new SHIFT signal is also added. When asserted,

the SHIFT signal causes the shift registers to load the input bit into the MSB position,

and shift out the LSB. The old LD signal has been changed to cause a parallel load

operation in the shift registers. This allows execution of the algorithm to begin sooner.

Otherwise, without the parallel load, the initial values would need to be shifted into the

register. The values of these signals in each of the four states are shown in Table 6.H.

! U>5E! )F2B42345! U:B4BG2:B;D!

S4BC5>! 3J %3,3%H $.3K

S4BC5!14B=H14;=>! 33 H6,6H# $.%K

LUT>! 6L H6,6H# $.3K

IOI>! %H6 HH% 5L.$K

I').>! $ 3H $.$K

JCLK>! % J %H.5K

T2345!6739D5FBC5!<:B4BG2:B;D!?;@!:A5!>5@B24!C;D:@;4!<DB:7!

The device utiliNation for the control unit is shown in Table 6.3. The parallel control

unit uses 3O slices, and this control unit uses 3J slices, making the area reQuirements for

the two units essentially the same. This unit reQuired more slice flip-flops T33U than the

parallel unitVs HO flip-flops.

6.#.$ %he )hift -egisters

The W, X, and Y registers in the serial design are all identical shift registers with

parallel load and parallel output capability. In addition to the clock signal, the registers

have two control inputs, two data inputs, and two data outputs. The data inputs are

65

labeled as S+I- and /. S+I- is the bit to be shifted in to the MSB position of the register

and / is the parallel data input. The t=o control signals are /LD and SAIFT. Chen

SAIFT is assertedD then the contents of the register shift to the right everF clock cFcleD

=ith S+I- becoming the ne= MSB. Chen /+LD is assertedD then the parallel data in / is

loaded into the register at the next rising edge of the clock.

!L#

!31

&'()

&'*+T

!L#

!3-

!L#

!-

!'*+T31 !'*+T3- !'*+T-

.L/ .L/ .L/

!"#$%& ()*+,&-"#. /0 12& -&%"34 -2"01 %&#"-1&%-)

The basic design is sho=n in Figure 6.3. Chen /LD is not assertedD then the data

inputs for each flip-flop are the data outputs of the adLacent flip-flip to the left. Chen

/LD is assertedD then the bits in / become the inputs for each of the flip-flops.

-ot sho=n in the figure are the clock enable inputs for the flip-flops. After the

algorithm is completeD the values should be held constantN that isD neither shifting nor

loading. The SAIFT and /LD inputs are connected through an OR gate to the clock

enable inputs of each of the flip-flops. As a resultD the register =ill onlF shift if SAIFT is

asserted and =ill onlF do a parallel load if /LD is asserted. In anF caseD the parallel

outputs are available as the /+OUT signalD and serial output is available as the S+OUT

signalD =hich al=aFs corresponds to the LSB of the register.

66

"sed A'aila+le ",ili-a,i./

Sli1es 2$ 1&,&12 (.2*

Sli1e 2li342l.3s &2 26,624 (.1*

5"Ts 4$ 26,624 (.2*

789s 44 221 1$.$*

9:A;s ( &2 (.(*

<=5>s 1 8 12.-*

Ta+le 6.4BCe'i1e D,ili-a,i./ E.r a si/Gle serial shiE, reGis,er Ii/1lDdi/G JKL1 NDl,i3leOerP.

Since this design does not have the large amount of multiplexers required by the

variable shift register described in -.1.2, the resource requirements of this register are

significantly reduced. The device utiliFation for one shift register is shown in Table 6.4.

The table includes the bit-select multiplexer shown in Figure 6.1 that is used to perform

the bit-shift operation. Only 2$ slices are required for this design, compared to $( for the

parallel shift register. The parallel shift registers are each 21(* larger than the serial

registers. Since the parallel shift registers were used twice in the parallel design, this area

reduction is the key to the small area requirements of the entire serial design.

!"#"$!%&' )**+,- %./0'

The lookup table remains essentially unchanged. In the serial design, a multiplexer is

added to choose the individual bits to be fed into the serial adder.

"sed A'aila+le ",ili-a,i./

Sli1es 8 1&,&12 (.1*

Sli1e 2li342l.3s ( 26,624 (.(*

5"Ts 16 26,624 (.1*

789s 12 221 -.4*

9:A;s 1 &2 &.1*

<=5>s 1 8 12.-*

Ta+le 6.QBCe'i1e D,ili-a,i./ E.r ,he serial l..RD3 ,a+le.

The parallel lookup table did not require any slices. The entire design was

implemented in one BROM. Since the serial design requires a &2:1 multiplexer, this

! ! "#

i%&'(%(n*+*i,n!,-!*.(!',,/0&!*+1'(!2(30i2(4!5!4'i6(47!8.i4!4%+''!in62(+4(!in!+2(+!i4!%,2(!

*.+n!,--4(*!19!*.(!4+:in;4!in!*.(!2(;i4*(24!+n<!+<<(247!

!"#"$ %&' S'*i,- .//'*0

!

!

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6+229!in!,-!*.(!6022(n*!4*+;(7!

68

The adder that computes the exponential value is a 32-bit parallel adder that uses the

parallel outputs of the ; and < registers.

"#r%&' (&r&''#' )*&%'&+'# "#r%&' ,-%'%.&-%/n

"'%1#2 4 16 13,312 0.0%

"'%1# 3'%453'/42 1 0 26,624 0.0%

6,72 7 32 26,624 0.0%

89:2 7 97 221 3.2%

:;)<2 0 0 32 0.0%

=>6?2 1 1 8 12.5%

7&+'# @A@BC#*%1# D-%'%.&-%/n E/r -F# 2#r%&' &nG 4&r&''#' &GG#r2A

As the design would imply, the resource requirements for this component are quite

small. Table 6.6’s serial column shows that only 4 slices are required to implement this

design. The parallel column shows the device utilization for the adder that computes the

exponential function.

!"#"$!%&'()* ,-../01

3%HDr# @AIB"'%1#2 D2#G +J -F# *&r%/D2 1/K4/n#n-2 /E -F# 2#r%&' >9;C8> Dn%-A

This design is even more efficient at using the FPOA’s resources, requiring much

less of the chip’s area than the parallel design. As Figure 6.5 shows, the distribution of

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731!'1!1$e!5*(1!*8!')),1,*n'6!56*59!5:56e(.!

6.#.$!Simulation $/ Computing e 3ith CORDIC 9rowth

<rror

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1$e!H!&eA,(1e&.!

!!igure 6.6*Results of a 2o3elSim simulation of the serial CORDIC unit attempting to =ompute the

>alue of !. ?s a result of CORDIC growthA the final =ompute3 >alue is ina==urate.

;$e!&e(361(!*8!1$,(!(,236'1,*n!'&e!($*En!,n!J,A3&e!K.K.!;$e!'6A*&,1$2!,1e&'1e)!8*&!'!

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?1/4*!34*)e6!

6.#.#!Simulation #. Computing e Compensating for

CORDIC :rowth

@/!-(0e(!+-!,-9.)+e!4/!4,,)(4+e!34*)e!-?!e;!+%e!A(-B+%!-C'e(3e0!1/!D67!9)'+!Ce!

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! ! "#

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.-$+!-8!4-)5e,!e9e./+%-)!+%7e:!

6.#.$!Simulation $/ Computing e–1

;+!%$!(4$-!%7<-,+()+!8-,!+2e!/)%+!+-!.-7</+e!+2e!3(4/e!-8!+2e!e9<-)e)+%(4!8/).+%-)!8-,!

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(6-/+!?0!2(48!-8!+2e!<-$$%64e!(,5/7e)+$!(,e!)e5(+%3e:!@2%$!$%7/4(+%-)!.-7</+e$!+2e!3(4/e!

-8!eAB:!C!%$!%)%+%(4%&e*!1%+2!B:#?"DB?!+-!e)$/,e!()!/)$.(4e*!,e$/4+0!()*!E!%$!%)%+%(4%&e*!1%+2!

?:!@2e!F!,e5%$+e,!.-)+(%)$!+2e!(,5/7e)+!8-,!+2e!e9<-)e)+%(4!8/).+%-)!()*!%$!+2/$!%)%+%(4%&e*!

+-!AB!GH???????BI!%)!#J$!.-7<4e7e)+!)-+(+%-)K:!

!

Figure 6.*—Results of a ModelSim simulation of the serial CORDIC unit computing the value of e@A

.

@2e!$%7/4(+%-)!,e$/4+$!<,e$e)+e*!%)!H%5/,e!I:L!$2-1!+2(+!+2e!MNOP;M!/)%+!%$!(64e!+-!

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6.#.5!Simulation 5/ Computing Outside the Domain of

Convergence

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"3

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.% )3a) )30 u,+) >+99 a))0m') )% $%m'u)0 !H.

Figure (.*+,esults of a 3odel5im simulation of the serial C:,;<C unit computing the value of e

5.

5ince the initial value 5 is outside the domain of convergence, the computed value is incorrect.

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74

Chapter 5. -y operating only on single bits in a serial fashion, the complexity of the shift

registers is reduced significantly. The size of the adders used in the design is also reduced

since they only need to handle one bit at a time. Precision and accuracy are not sacrificed

to achieve the reduction in resource utilization. However, the added execution time may

prevent this design from being used in more time-sensitive applications. For those, the

parallel design or a faster table-based approach would be better suited.

7#

!"#$%&' ) !*+,-./0*+ #+1 2.%.'& 3*'4

$rti(i)ia+ ne.ra+ net/or1s ha4e the potentia+ to 6e)ome in4a+.a6+e too+s (or s8stems

9esigners +oo1ing to imp+ement arti(i)ia+ inte++igen)e into their /or1. <he a6i+it8 o( these

net/or1s to 6e traine9 (or a spe)i(i) pro6+em an9 to operate a.tonomo.s+8 opens .p a

9oor to ne/ /a8s o( 9ata ana+8sis an9 other app+i)ations /here it is 9i((i).+t to 9esign

straight(or/ar9 a+gorithms to pro9.)e the 9esire9 res.+ts.

=>?$s are +i1e/ise 6e)oming in)reasing+8 .se(.+ (or 9esigners. <he a6i+it8 o( the

)hips to 6e reprogramme9 spee9s protot8ping an9 simp+i(ies the 9esign pro)ess (or +arger

s8stems. <he training pro)e9.re (or arti(i)ia+ ne.ra+ net/or1s re@.ires )hanges to interna+

/eights o( the net/or1. <he reprogramma6i+it8 o( the =>?$ means that these )hanges

)an 6e ma9e easi+8. <he a6i+it8 to p+a)e an arti(i)ia+ ne.ra+ net/or1 in an em6e99e9

en4ironment /ith rea+A/or+9 inp.ts (.rther eBpan9s the n.m6er o( app+i)ations a4ai+a6+e.

>re4io.s+8C it /as 4er8 9i((i).+t to 6.i+9 a ne.ra+ net/or1 in an =>?$ 6e)a.se o( the

9i((i).+t8 o( (itting the arithmeti) har9/are on the same )hip as the net/or1.

De.ra+ net/or1s re@.ire )omp+eB mathemati)a+ s.pport in or9er to (a)i+itate the

)omp.tation o( the s.mmationC /eightingC an9 trans(er (.n)tions. Eost arithmeti)

a+gorithms are optimiFe9 (or spee9 an9 re@.ire +arge amo.nts o( )hip area /hen

imp+emente9. De.ra+ net/or1s are inherent+8 para++e+ )omp.ter s8stems an9 in or9er to

.se a +arge arithmeti) .nitC a++ the )omp.tations /o.+9 ha4e to 6e pipe+ine9 thro.gh one

or se4era+ o( these .nits. <his /o.+9 +essen the para++e+ism o( the net/or1C /hi)h a+so

res.+ts in +onger )omp.tation times.

7#

The '()*+' implementations presented are compact enough that they potentially

could be duplicated in the F=>A, allowing each neuron to have its own '()*+' unit.

This maintains the parallelism of the network. Two alternate designs of '()*+' units

have been presented, a parallel design and a much smaller serial design that takes longer

to execute. Either of these could be used in a neural network at the neuron level.

7.# $omparing the 1esigns

The parallel design fits in 32J of the KpartanL3Ms slices and can run at a theoretical

maximum clock frequency of 7O PQz. The serial design is much smaller, needing only

13J slices, and can also run at almost twice the clock frequencyT 13U.V PQz.

Figure 7.1+,lices required by the various components of the two CORDIC designs.

The parallel design requires a large amount of 32T1 multiplexers to accomplish the

shifting. This is necessary because the amount by which the operands are shifted

77

increases each iteration of the algorith0. When switching to the serial a44roach5 these

0ulti4le7ers are eli0inate8 resulting in significant resource sa9ings. As seen in ;igure

7.15 it is this sa9ings that accounts for 0ost of the efficienc= of the 8esign.

>he effect of wor8 si?e on the area re@uire0ent of the 8esigns can Ae seen in ;igure

7.2. >he 4arallel 8esign alwa=s re@uires 0ore area than the serial 8esign5 an8 the nu0Aer

of slices re@uire8 for the 4arallel 8esign increases 8ra0aticall= with each increase of the

wor8 si?e. >he area re@uire0ent of the serial 8esign increases roughl= linearl=5 while the

4arallel 8esign follows a shar4 e74onential cur9e.

>he affect wor8 si?e has on e7ecution ti0e is shown in ;igure 7.C. >he unit is

assu0e8 to Ae o4erating at the 0a7i0u0 clock fre@uenc=5 as re4orte8 A= the Eilin7

s=nthesi?er. >his 9alue is 8ifferent for Aoth the 4arallel an8 serial 8esigns. >he 0a7i0u0

clock fre@uenc= also 8ecreases as wor8 si?e increases5 which further lengthens e7ecution

ti0e with larger wor8 si?es. >he serial 8esign is se9erel= i04lacte8 A= the increase in

wor8 si?e. F7ecution ti0e increases e74onentiall= with wor8 si?e5 while e7ecution ti0e

for the 4arallel 8esign follows a roughl= linear track.

"#

Figure 7.2+The effect of word size on the F78A chip area re<uirements of the CORDIC unit.

Figure 7.C+The effect of word size on the execution time of the CORDIC unit.

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optimized the algorithm for area, requires each iteration of the algorithm to take longer.

Each bit in the operands will use one clock cycle to compute the new value. For these

designs, which use the word sizes of 32 bits and 31 iterations Cwith 2 repeatsD, the 3E

clock cycles that the paralle implementation requires are increased to 1,FG7 cycles. This

is an increase of 3FFFI. This is offset somewhat by the increase in clock frequency, but

the serial implementation still takes significantly longer to complete.

For applications that can tolerate less precision, further savings in both area and

computation time can be achieved. Jeural networks in particular are probabilistic in

nature and may not need 32 bits of precision. Kecreasing the word size to 1L bits will

drastically reduce the area requirement for the parallel design, since its area requirement

decreases exponentially with word size. The area requirement of the serial design

depends only linearly on the word size, so the area savings would not be as significant.

The execution time, however, would decrease exponentially.

Noth implementations also have complex control units that are designed with

flexibility in mind. Ot is possible that the clock frequency for both designs could be

increased if the control unit could be simplified for a specific application.

7.# Integration .ith Artificial 4eural 4etwor7s

7.#.9 :;<=I: Artificial 4euron

This section discusses the design of a basic artificial neuron that uses the PQRKOP

unit to compute its transfer function. Figure 7.E shows the design of this neuron. This

sample design uses E inputs, but the design can be scaled to accommodate any number of

inputs.

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Figure 7.*—Bloc0 diagram of a basic artificial neuron utili9ing the CORDIC unit to compute the

transfer function ex.

The 4 inputs are weighted by constants that are stored internally in the neuron. 9

separate multiplier computes the weighted value for each input in parallel. 9s per the

artificial neuron model shown in Figure 2.1, these weighted values are then passed

through a summation function. Three adders are cascaded to add the four values together.

The CORDIC unit then computes the transfer function. The output of the final adder is

used as the argument to the function. In this case, since the CORDIC unit has been

designed to compute ex, the sum is connected to the INGH input. INGI is initialized to 0,

and INGK is initialized to 1.2075 to ensure an unscaled result. The NT9RT and RENET

signals may be provided externally or may be hardQwired to high or low. The E output of

the CORDIC unit then becomes the output of the neuron (NS9T) and may be connected

to any number of neurons in the next layer of the network.

The multipliers can be of any design, but since all inputs use a fixed point, the output

must be shifted accordingly. The design used here has 2" bits reserved for the fractional

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83

computations: a high-speed lookup table 7either on-chip or off: or either of the CORDIC

implementations discussed here.

Table-based implementations work similar to the logarithm tables found in the back

of textbooks, requiring interpolations between rows. These designs can be very fast and

accurate, but require large amounts of chip area. For large networks, it would require a

much larger 7and more expensive: FPGA to allow the lookup table to coexist with the

network. Additionally, all arithmetic calculations would have to be queued, slowing

down the operation of the entire network. If the table implementation is fast enough and

the network small enough, then performance may be comparable to a CORDIC

implementation.

The CORDIC algorithm is powerful enough and small enough to be able to support a

neural network, ideally with a CORDIC unit in each neuron. This would maintain the

parallelism that is key to the operation of the neural network. The longer computation

time is not a maLor shortcoming, since the power of a neural network lies in its

parallelism. The fact that all neurons can be computing in parallel and all neurons can

finish processing their inputs at the same time allows for a natural progression of data

through the network.

The flexibility of the algorithm with its two computation modes that can each operate

in one of three domains means that the same unit can compute a wide variety of

functions. This gives the network designer the flexibility to vary the transfer functions

used with only minimal changes and no redesigning necessary. It would also be possible

for the CORDIC unit to perform the multiplication of the weighting factors with the

"#

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85

!"#"$"%&"'

[1] J. S. *alther, “A unified algorithm for elementary functions,” in Spring (oint

Computer Conference, vol. 38, pp.379–385, 1971.

[2] J.E. Holder, “The COLDIC Trigonometric Computing TechniOue,” 12E Trans.

Electronic Computers, vol. EC-8, no. 3, pp. 330–334, Sept. 1959.

[3] H. Dawid and H. Meyr, “COLDIC Algorithms and Architectures,” in Digital

Signal :rocessing for Multimedia Systems, ed. by K.K. Parhi and T. Nishitani,

Marcel Dekker, 1999, pp. 623–655.

[4] L. Andraka, “A survey of COLDIC algorithms for FPGA-based computers,” in

1nternational Symposium on Field :rogrammable @ate Arrays, 1998.

[5] ^. H. Hu, “The _uanti`ation Effects of the COLDIC Algorithm,” 1EEE Trans.

Signal :rocessing, vol. 40, pp. 834–844, July 1992.

[6] IEEE Std. 754-1985, “Standard for Binary Floating Point Arithmetic,” 1985.

[7] A. A. Liddicoat and L. A. Slivovsky. :rogrammable logic. 3rd

Edition of EE

Handbook. CLC Press.

[8] cilind. Spartan-3 FPGA family: Complete data sheet. Datasheet DS099, cilind.

[9] M.M. Mano and C.L. Kime, BLS1 :rogrammable Logic Devices, Pearson

Prentice Hall, Upper Saddle Liver, NJ, 3rd edition, 2004. Supplement to Logic

and Computer Design Fundamentals.

[10] D. Anderson and G. McNeil, “Artificial Neural Networks Technology,”

DoD Data g Analysis Center for Software, August 1992.

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87

[18] '. )u and S.N. Batalama, “An Efficient Learning Algorithm for

Associative Memories,” IEEE $rans. Neural Networks, vol. 11, no. 5, pp. 1058–

1066, Sept. 2000.

[19] S. Halgamuge, “A Trainable Transparent Universal ApproPimator for

DefuRRification in Mamdani-Type Neuro-FuRRy Controllers,” IEEE $rans. Fuzzy

Systems, vol. 6, no. 2, pp. 304–314, May 1998.