Thermal Mechanical Specification and Design Guide - Intel€¦ · Intel® C610 Series Chipset Thermal Mechanical Specification and Design Guide September 2014 Order No.: 330790-001

Intel® C610 Series ChipsetThermal Mechanical Specification and Design Guide

September 2014

Order No.: 330790-001

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Intel® C610 Series ChipsetThermal Mechanical Specification and Design Guide September 20142 Order No.: 330790-001

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http://www.intel.com/info/hyperthreading

http://www.intel.com/design/chipsets/hdaudio.htm

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http://www.intel.com/content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecture-general.html

http://www.intel.com/content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecture-general.html

http://www.intel.com/go/virtualization

http://ark.intel.com/

http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-instructions-aes-ni/

http://www.intel.com/content/www/us/en/architecture-and-technology/intel-active-management-technology.html

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Revision History

Document Number Revision Number Description Revision Date

330790 001 Initial release September 2014

Revision History—Intel® C610 Series Chipset

Intel® C610 Series ChipsetSeptember 2014 Thermal Mechanical Specification and Design GuideOrder No.: 330790-001 3

Contents

Revision History..................................................................................................................3

1.0 Introduction................................................................................................................. 71.1 Design Flow........................................................................................................... 71.2 Terminology...........................................................................................................8

2.0 Packaging Mechanical Specifications............................................................................ 92.1 PCH Package..........................................................................................................92.2 PCB Pad Recommendations.................................................................................... 10

2.2.1 Pad Type Recommendations...................................................................... 102.2.2 Non-critical to Function Solder Joints........................................................... 12

2.3 Solder Balls..........................................................................................................122.4 Package Mechanical Requirements.......................................................................... 12

3.0 Thermal Specifications...............................................................................................133.1 Thermal Design Power (TDP).................................................................................133.2 Thermal Specifications...........................................................................................133.3 Storage Specifications........................................................................................... 14

4.0 Thermal Simulation.....................................................................................................16

5.0 Thermal Metrology......................................................................................................175.1 Junction Temperature Measurements.......................................................................17

5.1.1 Heatsink Thermocouple Attach Methodology................................................. 17

6.0 ATX Reference Thermal Solution.................................................................................196.1 Reference Design Heatsink Performance.................................................................. 19

7.0 Design Recommendations for Solder Joint Reliability................................................. 207.1 Solder Pad Recommendation.................................................................................. 20

Appendix A Thermal Solution Component Vendors........................................................... 22

Appendix B Mechanical Drawings for Package and Reference Thermal Solution............... 23

Intel® C610 Series Chipset—Contents


Figures1 Thermal Solution Design Flow..................................................................................... 72 Package Dimensions (Top and Land side Views)............................................................ 93 Package Dimensions (Side View)............................................................................... 104 Intel® C610 series chipset Land Pattern......................................................................115 Thermal Solution Decision Flow Chart.........................................................................176 Thermocouple/Die attach Method...............................................................................187 HeatSink Modifications Required for Thermocouple Attach.............................................188 Heatsink Performance curves.................................................................................... 199 Example of Wide Traces Used in BGA Routing..............................................................2110 50x40 Reference PCH Heatsink Keep Out Zone............................................................ 2411 30x30 Reference PCH Heatsink Keep Out Zone............................................................ 2512 Intel® C610 series chipset Detailed Package Mechanical Drawing................................... 2613 30x30 Reference Heatsink Mechanical Drawing Sheet 1................................................ 2614 30x30 Reference Heatsink Mechanical Drawing Sheet 2................................................ 2715 30x30 Reference Heatsink Mechanical Drawing Sheet 3................................................ 2816 50x40 Reference Heatsink Mechanical Drawing Sheet 1................................................ 2917 50x40 Reference Heatsink Mechanical Drawing Sheet 2................................................ 3018 50x40 Reference Heatsink Mechanical Drawing Sheet 3................................................ 31

Figures—Intel® C610 Series Chipset


Tables1 Pad Size / Geometry and Type Recommendations........................................................ 112 TDP Summary For various Chipset Configurations........................................................ 133 Chipset Thermal Specifications.................................................................................. 144 Storage Conditions.................................................................................................. 145 Reference Heatsink Enabled Components....................................................................226 The mechanical drawings included in this appendix...................................................... 23

Intel® C610 Series Chipset—Tables


1.0 Introduction

The goals of this document are to:

• Outline the thermal and mechanical operating limits and specifications for theIntel® C610 Series Chipset for use in Server and Workstation.

• Describe reference thermal solutions that meet the specifications of the Intel®C610 series chipset.

Note: Unless otherwise specified, the term "Platform Controller Hub" or chipset will be usedto refer to any version of the chipset. Only where required will a specific product codebe used.

Properly designed thermal solutions provide adequate cooling to maintain the PlatformController Hub junction temperatures at or below thermal specifications. This isaccomplished by providing a low local-ambient temperature, ensuring adequate localairflow, and minimizing the case to local-ambient thermal resistance. By maintainingthe chipset junction temperature at or below the specified limits, a system designercan ensure the proper functionality, performance, and reliability of the chipset.Operation outside the functional limits can cause data corruption or permanentdamage to the component.

The simplest and most cost-effective method to improve the inherent system coolingcharacteristics is through careful chassis design and placement of fans, vents, andducts. When additional cooling is required, component thermal solutions may beimplemented in conjunction with system thermal solutions. The size of the fan orheatsink can be varied to balance size and space constraints with acoustic noise.

Design Flow

To develop a reliable, cost-effective thermal solution, several tools are available to thesystem designer. The following figure illustrates the design process implicit to thisdocument and the tools appropriate for each step.

Figure 1. Thermal Solution Design Flow

Step 1: Thermal Simulation· Thermal Model· Thermal Model User’s

Guide

Step 2: Heatsink Selection· Thermal Reference· Mechanical Reference

Step 3: Thermal Validation· Thermal Testing Software· Software User’s Guide

1.1

Introduction—Intel® C610 Series Chipset


Terminology

Item Description

BLT Bond Line Thickness. Final settled thickness of the thermal interface material after installation ofthe heatsink.

CTE Coefficient of Thermal Expansion. The relative rate a material expands during a thermal event.

FC-BGA Flip Chip Ball Grid Array. A package type defined by a plastic substrate where a die is mountedusing an underfill C4 (Controlled Collapse Chip Connection) attach style. The primary electricalinterface is an array of solder balls attached to the substrate opposite the die. Note that the devicearrives at the customer with solder balls attached.

MD Metal Defined pad is one where a pad is individually etched into the PCB with a minimum widthtrace exiting it.

PCH Platform Controller Hub. The PCH is connected to the processor via the Direct Media Interface(DMI) and the Intel® Flexible Display Interface (Intel® FDI).

SMD The Solder Mask Defined pad is typically a pad in a flood plane where the solder mask openingdefines the pad size for soldering to the component.

TDP Thermal design power. Thermal solutions should be designed to dissipate this power level. TDP isnot the peak power that the PCH can dissipate.

TIM Thermal Interface Material. A thermally conductive material used between the component andheatsink to improve thermal conduction.

TMTV Thermal Mechanical Test Vehicle. A mechanically equivalent package that contains a resistiveheater in the die to evaluate thermal solutions. The package has daisy chain connections for use inevaluation of solder joint reliability.

1.2

Intel® C610 Series Chipset—Introduction


2.0 Packaging Mechanical Specifications

PCH Package

The Platform Controller Hub uses a 25mm x 25mm square flip chip ball grid array (FC-BGA) package. The following figures show select dimensions of interest a fully detailedpackage drawing can be found in the appendix.

Figure 2. Package Dimensions (Top and Land side Views)

Notes: 1. All dimensions in mm.

2. Drawing not to scale.

3. See Mechanical Drawings for Package and Reference Thermal Solution fortoleranced dimensions

2.1

Packaging Mechanical Specifications—Intel® C610 Series Chipset


Figure 3. Package Dimensions (Side View)

Notes: 1. All dimensions in mm.

2. Drawing not to scale.

3. See Mechanical Drawings for Package and Reference Thermal Solution fortoleranced dimensions

PCB Pad Recommendations

Intel recommends customers implement the pad sizes and shapes shown below.These recommendations allow for trace breakout in a typical multi-layer board design.In addition the pads are sized for solder joint protection of the critical to functioninterconnects.

Pad Type Recommendations

Intel defines two pad types based on how they are constructed. A metal defined (MD)pad is one where a pad is individually etched into the PCB with a minimum width traceexiting it. The solder mask defined (SMD) pad is typically a pad in a flood plane wherethe solder mask opening defines the pad size for soldering to the component.

In thermal cycling a MD pad is more robust than a SMD pad type. The solder maskthat defines the SMD pad can create a sharp edge on the solder joint as the solderball / paste conforms to the window created by the solder mask.

The solder joints under the die (die shadow) can experience stress due to a coefficientof thermal expansion (CTE) mismatch between the package and board. The size of thedie tends to influence the localized CTE of the package substrate driving higherstresses on the solder joints under the die shadow. For this reason the recommendedpad type in this region is MD.

For certain failure modes the MD pad may not be as robust as SMD in shock &vibration (S&V). During S&V, the predominant failure mode for a MD pad in the cornerof the BGA layout is pad craters and solder joint cracks. A corner MD pad can be mademore robust and behave like a SMD pad by having a wide trace enter the pad. Thistrace should be 10 mil minimum but should not exceed the pad diameter and exit the

2.2

2.2.1

Intel® C610 Series Chipset—Packaging Mechanical Specifications


pad at a 45 degree angle (parallel to the diagonal of the package). During boardflexure that results from shock & vibration a SMD pad is less susceptible to a crackinitiating due to the larger surface area.

The figure and table below show the recommended Intel® C610 series chipset landpattern and pad types.

Figure 4. Intel® C610 series chipset Land Pattern

Table 1. Pad Size / Geometry and Type Recommendations

Size / Shape Type Location Quantity Comment

16 mil SoldermaskDefined on 22mil metalpad or flood Cu

nCTF Package Corner 9 Shown In Blue

16 mil Metal Defined nCTF Package Corner 12 Shown in Brown

continued...

Packaging Mechanical Specifications—Intel® C610 Series Chipset


Size / Shape Type Location Quantity Comment

15 mil Metal Defined nCTF Package Corner 9 Shown in Cyan

15 mil Metal Defined CTF Package Corner 14 Shown in Red

10x13.5mil oblong MetalDefined

CTF Package Edge 66 Shown in Yellow

12 mil, Wide Trace MetalDefined =10 mil

CTF Package Interior 606 Shown in Green

15 mil, Wide Trace MetalDefined =10 mil

Die Shadow CTF Package Center 120 Shown in Purple

Total 836

Notes: 1. I/O Trace width is equal to 4 mil2. Wide traces should have a 10 mil minimum width but not to exceed the pad diameter and exit

the pad at a 45 degree angle (parallel to the diagonal of the package)3. Where possible, 10 mil traces 45 degrees outward from die center4. No 2 Wide Trace Metal Defined or Solder Mask Defined Pads allowed in Die Shadow

Non-critical to Function Solder Joints

Several selected solder joints of the PCH are defined as non-critical to function (NCTF)when evaluating package solder joints post environmental testing. The PCH signals atNCTF locations are typically redundant ground or non-critical reserved pins, so the lossof the solder joint continuity at end of life conditions will not affect the overall productfunctionality.

Solder Balls

A total of 836 solder balls corresponding to the lands are on the bottom of the PCHpackage for surface mounting with the motherboard. The package solder ball has thefollowing characteristics:

• Lead-free SAC (SnAgCu) 405 solder alloy with a silver (Ag) content between 3%and 4% and a melting temperature of approximately 217°C. The alloy iscompatible with immersion silver (ImAg) and Organic Solderability Protectant(OSP) motherboard surface finishes and a SAC alloy solder paste.

• Solder ball diameter 18.2mil [0.462mm], before attaching to the package.

Package Mechanical Requirements

The package has a bare die that is capable of sustaining a maximum static normalload of 15 lbf (67N). These mechanical load limits must not be exceeded duringheatsink installation, mechanical stress testing, standard shipping conditions, and/orany other use condition.

Notes: • The heatsink attach solutions must not induce continuous stress to the packagewith the exception of a uniform normal load to maintain the heatsink-to-packagethermal interface.

• These specifications apply to uniform compressive loading in a directionperpendicular to the die top surface.

• These specifications are based on limited testing for design characterization.Loading limits are for the package only

2.2.2

2.3

2.4

Intel® C610 Series Chipset—Packaging Mechanical Specifications


3.0 Thermal Specifications

To ensure proper operation and reliability of the PCH, the case (or junction)temperature must be at or below the maximum value specified. System and/orcomponent level thermal solutions are required to maintain these temperaturespecifications.

Thermal Design Power (TDP)

Real applications are unlikely to cause the chipset component to consume maximumpower dissipation for sustained time periods. Therefore, in order to arrive at a morerealistic power level for thermal design purposes, Intel characterizes powerconsumption to reach a Thermal Design Power (TDP). TDP is the target power level towhich the thermal solutions should be designed. The following table highlights keytypical configurations and associated TDP and port usage.

Table 2. TDP Summary For various Chipset Configurations

Workstation Server Typical Low power #1 Low power #2 Boot-only

Number of USB2Ports

14 6 4 2 (Device detectiononly)

0

Number of USB3Ports

4 4 31 1 (Device detectiononly)

0

Number of SATA3Ports

8 5 2 2 0

Number of SATA22

Ports2 1 1 1 0

Number of PCIeLanes

8 4 2 23 0

1 GbE MAC Status Enabled Disabled Disabled Disabled Disabled

HD Audio Status Used Unused Unused Unused Unused

TDP Max (W) 6.5 5 4 3.2 1.0

S0 Idle power (W) 0.80 0.80 0.80 0.80 0.80

Note: 1. Assumes that one of the USB3 ports only detects devices, and the other two work at full capacity2. Assumes that SATA port 5 and 6 run at Gen 2 speed for optical device usage3. Assumes that one of the PCIe ports runs at L1

Thermal Specifications

Intel recommends designing the chipset thermal solution to an appropriate TDP givenprojected use for maximum flexibility and reuse. The chipset package has poor heattransfer capability into the board and has minimal thermal capability without thermalsolutions. Intel requires that system designers plan for an attached heatsink when

3.1

3.2

Thermal Specifications—Intel® C610 Series Chipset


using the chipset. The designed thermal solution must able to meet the specifiedthermal specification in the below table. The reference thermal solution is described infollowing chapters.

Table 3. Chipset Thermal Specifications

Parameter Value Notes

Tjunction-max 100 °C 1,3,4,

Tjunction-min 5 °C 1,3,4

TSENSOR--max 95 °C 1,2,3,4,5,6

Notes: 1. Refer to the Intel® C610 Series Chipset and Intel® X99 Chipset Platform Controller Hub (PCH)Datasheet for thermal management mechanisms

2. Temperature value is based on thermal sensor output3. These specifications are based on preliminary measurement and subject to change.4. Designing to a lower Tjunction target will minimize the occurrences throttling as a result of chipset

over temperature5. The chipset silicon has an on die thermal sensor which is intended for usage in fan speed control

and thermal management to allow optimal acoustic operation. When evaluating the thermalrequirements under lower power and fan speeds, make sure to use engineering judgment on theairflow requirements taking the thermal sensor and fan speed control capability into account. Thethermal solution should be designed to have sufficient head room to cover TDP under maximumlocal ambient and altitude conditions; however, it is up to the thermal engineer to determine thequality, risk and cost regarding the acoustic solution.

6. Dual thermal specifications based on Tjunctionand Digital Thermal Sensor enables the thermalsolution designer to optimize the component thermal solution and the system thermalmanagement in a way that is best suited for the integration of the chipset thermal management.The Following Equation provides a conversion between TSENSOR and Tjunction at the Intel® C610series chipset maximum operating temperature. TSENSOR = (Tjunction ± 5)

7. Chipset temperature must be kept below Tjunction at all times

Storage Specifications

The following table includes a list of the specifications for device storage in terms ofmaximum and minimum temperatures and relative humidity. These conditions shouldnot be exceeded in storage or transportation.

Table 4. Storage Conditions

Parameter Description Min Max Notes

Tabsolute storage The non-operating devicestorage temperature.Damage (latent orotherwise) may occurwhen subjected to for anylength of time.

-25 °C 125 °C 1, 2, 3

Tsustained storage The ambient storagetemperature limit (inshipping media) for asustained period of time.

-5 °C 40 °C 4, 5

continued...

3.3

Intel® C610 Series Chipset—Thermal Specifications


Parameter Description Min Max Notes

RHsustained storage The maximum devicestorage relative humidityfor a sustained period oftime.

60% @ 24 °C 5, 6

TIMEsustained storage A prolonged or extendedperiod of time; typicallyassociated with customershelf life.

0 Months 6 Months 6

Note: 1. Refers to a component device that is not assembled in a board or socket that is not to be electrically

connected to a voltage reference or I/O signals.2. Specified temperatures are based on data collected. Exceptions for surface mount reflow are specified in

by applicable JEDEC standard and MAS document. Non-adherence may affect component reliability.3. Tabsolute storage applies to the unassembled component only and does not apply to the shipping media,

moisture barrier bags or desiccant.4. Intel® branded board products are certified to meet the following temperature and humidity limits that

are given as an example only (Non-Operating Temperature Limit: -40C to 70C & Humidity: 50% to 90%,non-condensing with a maximum wet bulb of 28°C). Post board attach storage temperature limits are notspecified for non-Intel® branded boards.

5. The JEDEC, J-JSTD-020 moisture level rating and associated handling practices apply to all moisturesensitive devices removed from the moisture barrier bag.

6. Nominal temperature and humidity conditions and durations are given and tested within the constraintsimposed by Tsustained and customer shelf life in applicable Intel® box and bags.

Thermal Specifications—Intel® C610 Series Chipset


4.0 Thermal Simulation

Intel provides thermal simulation models of the PCH and associated user guides to aidsystem designers in simulating, analyzing, and optimizing their thermal solutions in anintegrated, system-level environment. The models are for use with the commerciallyavailable Computational Fluid Dynamics (CFD)-based thermal analysis tool FloTHERM*(version 9.1 or higher) by Flomerics, Inc. and Icepak* by Fluent. Contact your Intelfield sales representative to order the thermal models and users' guides.

Intel® C610 Series Chipset—Thermal Simulation


5.0 Thermal Metrology

The system designer must make temperature measurements to accurately determinethe thermal performance of the system. Intel has established guidelines for propertechniques to measure the PCH case and junction temperatures. The flowchart inbelow offers useful guidelines for thermal performance and evaluation.

Figure 5. Thermal Solution Decision Flow Chart

Attach the device to the board using normal reflow

process

Attach thermocouple. Setup the system in the desired configuration

Run representative workload for the configuration and

monitor the device temperature

Revise Heatsink design or Boundary conditions

Temperature>Specification?

Start

EndNo

Yes

Junction Temperature Measurements

To ensure functionality and reliability, the Tcase of the PCH must be maintained at orbetween the maximum/minimum operating range of the temperature specification asnoted in the thermal specifications. The surface temperature at the geometric centerof the die corresponds to Tcase. Measuring Tcase requires special care to ensure anaccurate temperature measurement. Temperature differences between thetemperature of a surface and the surrounding local ambient air can introduce errors inthe measurements. The measurement errors could be due to a poor thermal contactbetween the thermocouple junction and the surface of the package, heat loss byradiation and/or convection, conduction through thermocouple leads, and/or contactbetween the thermocouple cement and the heatsink base (if a heatsink is used). Formaximum measurement accuracy, only the 0° thermocouple attach approach isrecommended.

Heatsink Thermocouple Attach Methodology

1. Mill a 3.3 mm (0.13 in.) diameter and 1.5 mm (0.06 in.) deep hole centered (with0.7mm offset to left side refer to Diagram below) on the bottom of the heatsinkbase.

2. Mill a 1.3 mm (0.05 in.) wide and 0.5 mm (0.02 in.) deep slot from the centeredhole to one edge of the heatsink. The slot should be parallel to the heatsink fins.

3. Attach thermal interface material (TIM) to the bottom of the heatsink base.

4. Cut out portions of the TIM to make room for the thermocouple wire and bead.The cutouts should match the slot and hole milled into the heatsink base.

5.1

5.1.1

Thermal Metrology—Intel® C610 Series Chipset


5. Attach a 36 gauge or smaller calibrated K-type thermocouple bead to the center ofthe top surface of the die using a high thermal conductivity cement. During thisstep, ensure no contact is present between the thermocouple cement and theheatsink base because any contact will affect the thermocouple reading. It iscritical that the thermocouple bead makes contact with the die

6. Attach heatsink assembly to the package and route thermocouple wires outthrough the milled slot.

Figure 6. Thermocouple/Die attach Method

Figure 7. HeatSink Modifications Required for Thermocouple Attach

Intel® C610 Series Chipset—Thermal Metrology


6.0 ATX Reference Thermal Solution

Intel has developed reference thermal solutions to meet the cooling needs of the PCHin a typical High End Desktop (HEDT) or Server system under operating environmentsand specifications defined in this document. This section describes the overallrequirements and targets for the reference thermal solution. and validation criteria.Other chipset components may or may not need attached thermal solutions dependingon your specific system local-ambient operating conditions.

Note: The reference thermal mechanical solution information shown in this documentrepresents the current state of the design. The data is subject to modification andrepresents design targets, not commitments by Intel.

Reference Design Heatsink Performance

The reference heatsink designs were created to maintain Tcase of the PCH at or belowthe Tcase Max specification. The performance curves for the two reference designs areshown below.

Figure 8. Heatsink Performance curves

6.1

ATX Reference Thermal Solution—Intel® C610 Series Chipset


7.0 Design Recommendations for Solder JointReliability

Solder Joint Reliability (SJR) remains a major topic of concern in designing systemsespecially for surface mounted components. Solder ball cracking and fracture is afailure mode associated with over stressing the surface mounted component on themotherboard. The over-stressing typically occurs when the motherboard is subjectedto bending deflection. The deflection of the motherboard applies loads to these surfacemounted components that attempt to peel the component from the board. Theseloads stress the solder balls of the component and either initiate cracks, which growthrough the solder during thermal and power cycling, or cause fracture, which resultsin an electrical open.

Loading conditions such as shock typically stress the motherboard and generatestresses at the solder joints that leads to either crack initiation or complete fracture ofthe balls. This section will discuss guidance specific to the PCH. Please refer to theSystem Mechanical Design Guidance for Dynamic Events Application Note, SupportingDesktop, Workstation and Servers for more information on system design guidance,and best practices.

Non-Critical to Function (NCTF) Solder Balls are located in the corners of the ball gridarray, where they are most susceptible to stressing from motherboard flexure, andunder the die shadow. These NCTF balls mitigate degradation to componentperformance once damage has occurred at the solder balls. The NCTF solder ballsprovide for load shedding during solder ball loading events.

Solder Pad Recommendation

Additional protection from pad cratering on the motherboard has been demonstratedthrough the usage of thick traces at the corner NCTF ball locations. NCTF tracethicknesses of 60-80% of the pad diameter were tested in board level shock tests withmetal define pads and reduced the occurrence of pad cratering failures. Pad crateringis the failure mode in which solder pads in the motherboard separate from the PCB.

The wide traces shown in the following figure are an example of how wide traces maybe used at NCTF pads.

7.1

Intel® C610 Series Chipset—Design Recommendations for Solder Joint Reliability


Figure 9. Example of Wide Traces Used in BGA Routing

Note: The NCTF locations shown inabove figure are not the NCTF locations of the PCHpackage and is shown to illustrate the application of wide traces.

Designers are encouraged to use wide traces in designs where pad cratering hasoccurred along the corners of the package. Recommended pad locations for widetraces are shown in the PCH land pattern The wide traces effectively increase thestrength of the pad to motherboard interface and may cause a crack to initiate in adifferent failure mode in the NCTF solder ball while increasing the shock margin.

Design Recommendations for Solder Joint Reliability—Intel® C610 Series Chipset


Appendix A Thermal Solution Component Vendors

Note: These vendors and devices are listed by Intel as a convenience to Intel's generalcustomer base, but Intel does not make any representations or warranties whatsoeverregarding quality, reliability, functionality, or compatibility of these devices. This listand/or these devices may be subject to change without notice.

Table 5. Reference Heatsink Enabled Components

Item Intel PN CCI PN

50x40x12 Heatsink Assembly G65665 00Z91330101

30x30x12 Heatsink Assembly G68101 00Z91340101

Contact Info CCI TECHNOLOGY CORPMonica [email protected]

Intel® C610 Series Chipset—Thermal Solution Component Vendors


Appendix B Mechanical Drawings for Package andReference Thermal Solution

Table 6. The mechanical drawings included in this appendix

Description PN

50x40 Reference PCH Heatsink Keep Out Zone KOZ-G65665

30x30 Reference PCH Heatsink Keep Out Zone KOZ- G68101

Intel® C610 series chipset Detailed Package Mechanical Drawing G69519

30x30 Reference PCH Heatsink Mechanical Drawing G68101

50x40 Reference PCH Heatsink Mechanical Drawing G65665

Mechanical Drawings for Package and Reference Thermal Solution—Intel® C610 Series Chipset


Figure 10. 50x40 Reference PCH Heatsink Keep Out Zone

A

4

B

3

C D

43

21

A

2

C

1

D

2200 MISSION COLLEGE BLVD.

P.O. BOX 58119

SANTA CLARA, CA 95052-8119

R

27.483

27.483

22.479

0

0

12.649

5.004

30.099

30.099

14.999

12.649

12.649

12.649

5.004

20.549

24.562

24.562

20.549

5.08

3.099

1.549

1.422

2X

0.965 PTH

2X

1.422

SOLDER AREA AROUND PTH HOLE,

NO COMPONENT ALLOWED

14.999

14.999

22.479

7.925

0.591

KOZ_G65665_BGA-HS1BDWG. NOSHT.REV

THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS

MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.

SHEET 1 OF 1

DO NOT SCALE DRAWINGSCALE: 1

BKOZ_G65665_BGA-HS

CREV

DRAWING NUMBER

SIZE

KOZ_G65665_BGA-HS

TITLE

-

DEPARTMENT

SEE NOTES

SEE NOTES

FINISH

MATERIAL

DATE

APPROVED BY

--

DATE

CHECKED BY

APRIL 23'12

JUNSONG WU

DATE

DRAWN BY

APRIL 23'12

JUNSONG WU

DATE

DESIGNED BY

UNLESS OTHERWISE SPECIFIED

INTERPRET DIMENSIONS AND TOLERANCES

IN ACCORDANCE WITH ASME Y14.5M-1994

DIMENSIONS ARE IN MM

TOLERANCES:

THIRD ANGLE PROJECTION

PARTS LIST

DESCRIPTION

PART NUMBER

ITEM NOQTY

KOZ_G65665_BGA-HS

TOP

REVISION HISTORY

ZONE

REV

DESCRIPTION

DATE

APPR

-A

INITIAL RELEASE

APR 13'2012

-

BADD AIR FLOW DIRECTION

APR 23'12

MAX 1.524MM COMP HEIGHT

UNDER HS BASE AREA

0.889MM MAX COMP HEIGHT

AROUND THE PACKAGE

PACKAGE AREA, NO COMP ALLOWED

2.032MM MAX COMP HEIGHT UNDER CLIP (2X)

HEATSINK FIN /

AIRFLOW DIRECTION

SCALE 2.5

SEE DETAIL A

DETAIL A

SCALE 10

Intel® C610 Series Chipset—Mechanical Drawings for Package and Reference Thermal Solution


Figure 11. 30x30 Reference PCH Heatsink Keep Out Zone

A

4

B

3

C D

43

21

A

2

C

1

D

2200 MISSION COLLEGE BLVD.

P.O. BOX 58119

SANTA CLARA, CA 95052-8119

R

17.475

0

0

12.649

25.095

14.999

12.649

12.649

12.649

7.62

10.541

19.558

19.558

10.541

5.08

3.099

1.549

1.422

14.99914.999

7.925

0.591

17.475

2X

0.965

PTH HOLE

2X

1.422

SOLDER AREA AROUND PTH,

NO COMPONENT ALLOWED

7.62

17.475

25.095

17.475

KOZ_G68101_BGA-HS1ADWG. NOSHT.REV

THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS

MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.

SHEET 1 OF 1

DO NOT SCALE DRAWINGSCALE: 1

AKOZ_G68101_BGA-HS

CREV

DRAWING NUMBER

SIZE

KOZ_G65665_BGA-HS

TITLE

-

DEPARTMENT

SEE NOTES

SEE NOTES

FINISH

MATERIAL

DATE

APPROVED BY

--

DATE

CHECKED BY

MAY 08'12

JUNSONG WU

DATE

DRAWN BY

MAY08'12

JUNSONG WU

DATE

DESIGNED BY

UNLESS OTHERWISE SPECIFIED

INTERPRET DIMENSIONS AND TOLERANCES

IN ACCORDANCE WITH ASME Y14.5M-1994

DIMENSIONS ARE IN MM

TOLERANCES:


PARTS LIST

DESCRIPTION

PART NUMBER

ITEM NOQTY

KOZ_G65665_30_30_BGA-HS

TOP

REVISION HISTORY

ZONE

REV

DESCRIPTION

DATE

APPR

-A

INITIAL RELEASE

MAY08'2012

-

MAX 1.524MM COMP HEIGHT

UNDER HS BASE AREA

0.889MM MAX COMP HEIGHT

AROUND THE PACKAGE

PACKAGE AREA, NO COMP ALLOWED

2.032MM MAX COMP HEIGHT UNDER CLIP (2X)

HEATSINK FIN /

AIRFLOW DIRECTION

SCALE 2.5

SEE DETAIL A

DETAIL A

SCALE 10



Figure 12. Intel® C610 series chipset Detailed Package Mechanical Drawing

8 7 6 5 4 3 2

H

G

F

E

D

C

B

A

8 7 6 5 4 3 2 1

H

G

F

E

D

C

B

A

2

6

C

C

P

BB1

C1

A

B2

C2

2

2

2

44X 1.75

4X 1.75

4X R1.75

2X 2

2X 2

N

F3

F2

F4

G1

G2

G2

G1(SOLDER RESIST OPENING)

0.5 0.05

(SOLDER RESIST OPENING)1 0.05

(SOLDER RESIST OPENING)0.35 0.05

(SOLDER RESIST OPENING)0.43 0.015

H

THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONT ENTS MAY NOT BE DISCLOSED, REPRODUCED, DI SPLAYED OR MODIFIED, WITHOUT THE PRI OR WRITTEN CONSENT OF INTEL CORPORAT ION.

G69519 1 3DWG. NO SHT. REV

DEPARTMENTR 2200 MISSION COLLEGE BLVD.

P.O. BOX 58119SANTA CLARA, CA 95052-8119

TITLE

PACKAGE MECHANICAL DRAWING

SIZE DRAWING NUMBER REV

A1 G69519 3SCALE: 6 DO NOT SCALE DRAWING SHEET 1 OF 2

FINISHMATERIAL

DATEAPPROVED BY

DATECHECKED BY

DATEDRAWN BY

DATEDESIGNED BYUNLESS OTHERWISE SPECIFIEDINTERPRET DIMENSIONS AND TOLERANCESIN ACCORDANCE WITH ASME Y14.5M-1994

DIMENSIONS ARE IN MILLIMETERSALL UNTOLERANCED LINEAR

DIMENSIONS ±0.1ANGLES ±0.5


0.6 MAX ALLOWABLECOMPONENT HEIGHT

1. PACKAGE EXPECTED TO BE WITHIN HIGH TEMPERATURE COPLANARITY RANGE OF -0.14 TO +0.22mm.

COMPONENT KIZ.

3. THE DIE SIZE SHOWN IN THIS DRAWING IS THE PHYSICAL DIE SIZE.

4. ALL TOLERANCES ARE RSS.

5. ALL Z STACKUP HEIGHT ESTIMATES ARE BASED ON PRE SMT BALL HEIGHT.

DIE SIDE COMPONENT KOZ.

TOP VIEW(UNDERFILL FILET GEOMETERYREMOVED FOR VISUAL CLARITY)

B

BOTTOM VIEWBALLS ANYWHERE

4X SUBSTRATE MARK ZONE

B

CPIN 1

SECTION B-B

TBD

0.203

A

D

E

PIN 1

DETAIL ASCALE 20

DETAIL BSUBSTRATE ALIGNMENT FIDUCIALS

2 PLACESSCALE 30

DETAIL CSUBSTRATE ALIGNMENT FIDICIAL

SCALE 30

DETAIL DSOLDER RESIST OPENING

836 PLACESSCALE 75

DETAIL ESUBSTRATE ALIGNMENT FIDUCIAL

SCALE 75

6

2

SYMBOLMILLIMETERS

COMMENTSNOM. TOL.

B1 25 0.04

B2 25 0.04

C1 6.78 N/A

C2 7.85 N/A

F2 0.819 0.02

F3 0.963 0.075

F4 1.782 0.072

G1 0.685 MIN SPACING FROM

BGA PAD CENTERTO PACKAGE EDGEG

2 0.685 MIN

H 0.7 N/AMIN PITCH FOR BALLSANYWHERE PATTERN

N0.303 0.05 PRE-SMT BGA HEIGHT

0.208 0.04 POST-SMT BGA HEIGHT UNDER THE DIE

P 0.462 0.05 PRE-SMT BGA BALL DIAMETER

0.14 C A B

0.04 C

0.14 C A B

0.04 C

Figure 13. 30x30 Reference Heatsink Mechanical Drawing Sheet 1


















Documents

Thermal Mechanical Specification and Design Guide - Intel€¦ · Intel® C610 Series Chipset Thermal Mechanical Specification and Design Guide September 2014 Order No.: 330790-001