The Way Towards Front Side Metallization By Copper-plating:

What We Can Learn From MicroelectronicsMicroelectronics

April 15th 2010

José Luis Hernández, Mónica Alemán, Christophe Allebé, Twan Bearda, Joachim John, Izabela Kuzma, Harold Philipsen, Niels Posthuma, Victor Prajapati, Simon Rodet, Jef Poortmans

Outline

• Front Side Metallization Challenges– Ag Screen Printing – Challenges and Oportunities

• Cu metalization in microelectronics – a showcase– Barrier layers – metal and dielectrics

– Cu plating– Cu plating

– Cu protocols and contamination

• Cu plated solar cells at IMEC

22nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Standard Si Solar Cell – LOW COST

Texture

Emitter n++ diffusion

PSG glass removal

SiNx ARC

3

Rear Al Screen Printing

Front Ag Screen Printing

Co-firing ~ 930 ºC• >90% Si market share• Simple, cost effective process• Efficiency ~ 15%-17%• Gap with high efficiency – 25% Edge Isolation

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

• Line aspect ratio• Finger width reduction

Shadow losses

• Low resistance• Low resistivity metal – Ag vs Cu

Line resistance

• Decrease of area with high SRV. • Lower contact resistance required

Recombination in contact area

Contacting advanced

Ag Screen Printing – Challenges & Opportunities

4

• Contact high resistance and shallow emittersContacting advanced

emitters

• AgSustainability

• SP hard contact technique - Wf breakage• Limit towards thinner Silicon

Technologicallimitations

• Ag is expensive• SP very competitive - multiple steps in one

Cost

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Multi-step Front Metallization

Open SiN

• Recombination in contact area• Damage emitter

Multi step process allows to independently control the different functionalities of front contact and enable the use of advanced emitters

Si

SiNx

Laser

LASER ABLATION

52nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Si

Cu

Si

Conductinglayer

• Aspect ratio• Sustainable, industrial and low cost

Contact layer

• Adhesion to Si and dielectric• Low Contact Resistance • Barrier Properties• Seed layer – to enable plating

JETTING /e-LESS

Cu PLATING

Synergy With Microelectronics

SOLUTION: Cu

Al

W

CHALLENGES:• Need to reduce RC delay• Limitations in feature size definition for technology node <0.25µm

Evolution vs Revolution

6

SOLUTION:• Replacement of Al ~3 µΩcm vs Cu ~1.9 µΩcm• Move from PVD to Plating• Introduction of damascene approach -> CMP • Use of low-k materials • Introduction of Cu in cleanrooms (Cu plating)• Introduce W at contact level

W

Cu introductionSynergy between PV and Microelectronics

Cu contamination?Barrier materials?Contact resistance?Impact of dielectric?

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Barriers

• 450ºC processing• Reliability - Electromigration, Stress Voiding• Current densities ~MA/cm2

• Layers needs to be DENSE and CONFORMAL -> Microelectronics

Barriers for what?

AR = 3.5

100nm

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• Layers needs to be DENSE and CONFORMAL -> Complicated tool concepts

• Thickness needs to scale-down with via size

Microelectronics

• 1000hrs - 85 ºC - 85% RH (IEEE61215)• Soldering temperature?• FGA @ 450ºC?• Current densities ~kA/cm2

PV

Microelectronics - Barriers

W

•Ti i-PVD•TiN MOCVD or ALD

Cu

•TaN i-PVD•Ta i-PVD

3D•Ti PVD

Al

•Ti PVD•TiN PVD

>0.25 µm< 0.25 µm

Cu

W

TaN/Ta

Ti/TiN

Si

8

3D

MEMS•TiW or Ti

• Act as adhesion and barrier materials • Contacting done through Silicides• Mainstream W contacts (some work to replace W with Cu)• Dielectric barriers also needed for mobile ions and low-k protection (SiC, SiCN, SiON,...)• PVD Cu (~100nm) is used as a seed layer for Cu plating

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Pre-clean

• Wafer pre-clean important before barrierdeposition - interface– Adhesion improvement

– Contact resistance improvement

92nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Plating Challenges

WfMetal Seed

e-

Cu Anode

Cu+Inorganic & Organic additives

• Damascene approach

Dual Damascene

200nmCu

Cu

30µmPV

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• Damascene approach• Dimension – Filling small vias <200nm• Narrow line resistivity – impurity incorporation• Plating non-uniformity σ<3%

• Chemistry control – additive control• Direct plating

Microelectronics

• Contacting front grid – seed layer conductivity -• Contacting backside contact – Light Induced Plating –Non-selective

• Throughput (~10µm @ >1000WPH)

• Chemical waste

PV

Contamination Protocols

• Define risks

• Measure

• Monitor

Tools and samples/wfs classified according to:

11

DXC factorD – detrimental factor – impact + quality of monitoringC – control factor – ability to measure and cleanX – cross contamination

Copper in CMOS is level 3 (scale 0-5)- detrimental with high risk of x-contamination BUT easy to measure (TXRF) and easy to clean

Proper protocols can control Cu contamination

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Copper Diffusion – A CMOS Example

SiSi ANNEAL15 min in N2200nm SiNx

5x1013 at/cm2 Cu contamination backside

Sweeping TXRF on frontside

650µm

SiNx used to protect tool chucks from contamination

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• SiNx blocks Cu during anneal at 450ºC

• Without SiNx enhanced out-diffusion for T>350ºC

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Cu Reliability Concerns

Barrier

Seed

Cu

SiNx

Diffusion through dielectricpin-holes/defects during

plating

SiNx

Copper corrosionCu capping

Plating on dielectric due to“mushroom growth” during

plating

Si

13

Effective barrier duringsubsequent processing and at operating conditions

(25yrs)

Alignment problemsbetween metal and dielectric opening

Establish protocol to prevent contamination of high temperature steps

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Front Contact Processing Schemes - IMEC

ARC SiNx opening

Barrier +Cu PVD

Patterning

Lift-off

ARC SiNx opening

Ni

Silicidation

Selective Etching(unless e-less Ni)

ARC SiNx opening

Aerosol Jetting

Cu plating

WITH PHOTOLITHOGRAPHY LITHO FREE

14

Lift-off Selective Etching(unless e-less Ni)

Cu platingPatterning-free

Very low cost

Alignment of laserand printing system

No barrier on SiN during plating

+

+

-

-

Self aligning –patterning free

Process window?

No barrier on SiNduring plating

+

-

-

Photolithography

Alignment of laser and barrier/seed

No barrier on SiNduring plating-

-

-

Cu plating

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Cu Plated i-PERC Cells at IMEC

• C-Si CZ 125mmx125mm Local Al-BSF Finger with 70µm

Area (cm2)

Rsh(ΩΩΩΩ/sq) Jsc(mA/cm2) Voc(mV) FF Eff(%)

144 80 37.5 644 77.0 18.6

152nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Copper Plating / images

SEMSEM

Si wf

Al BSF

Cu fingerCu finger

Si wfX-section @45º

16

FIB

•Conformal dense Cu deposition

2nd Metallization Workshop – Constance – April 15th 2010 José Luis Hernández

Wafer center33 µm

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