The Trend of TSV Packaging - · PDF fileThe Trend of TSV Packaging Dr. ChoonHeung Lee ... Package-on-Package Flip chip + Wire bonding TSV Wire bonding + Wire bonding Package Stacking

Enabling a

Microelectronic

World®

The Trend of TSV Packaging

Dr. ChoonHeung Lee Amkor

© 2011 Amkor Technology, Inc. Amkor Proprietary Business Information 2

Smaller

form factor

orcost

^^^

I/O numbers or performance>>> 1950~1970year

1980year

1990year

2000year

Package Trend


3.5

3.4

1.3

0.9

8.8

5.7

5.5

4.0

1.3

2.5 10.6

8.9

2010 OSAT Revenue : $23.6B

* Source : Gartner Dataquest (Oct.’11), Prismark (Aug.’11), Amkor Estimates

2015 OSAT Revenue : $32.7B

Packages Growth Rate


Package-in-Package

Package-on-Package TSVFlip chip + Wire bonding

Wire bonding + Wire bonding

Package Stacking 3D Stacking 3D IC

3D Packaging Paradigm Change


TSV

Memory Stack Logic + MemoryWide IO

•Performance

•Form Factor

•Performance

•Low Power

•Form Factor

•Performance

•Form Factor

•PerformanceDrive

Force

Direct Vertical Stack

Vertical Via Technology

Wafer Technology

Stacking Technology

FPGA

Interposer use side by side

3D-TSV IC Technology Tree


TSMC reveals plan for 3DIC design based on silicon interposer & TSV(Jun 8th 2010)

Elpida, PTI & UMC to partner for 3DIC commercialization of logic+DRAM stack with

28nm by 2011(Jun 23rd 2010)

Xilinx brings 3D TSV interconnects to commercialization phase in digital FPGA

world (Oct 27th 2010)

3DIC memory with wide I/O interface is coming by 2013, says NOKIA (Sep 17th 2010)

Micron reveals “Hyper Memory Cube” 3DIC technology (Feb 18th 2011)

Samsung wide I/O memory for mobile products – A deeper look (Feb 28th 2010)

Several News in TSV Area

http://www.i-micronews.com/upload/Micronews/images/Xilinx 3D TSV silicon interposer 11.jpg

© 2011 Amkor Technology, Inc. Amkor Proprietary Business Information

TSV Packaging Process

7

Wafer RDL / Bumping

Carrier Wafer Detach

Wafer Grinding

Carrier Wafer Attach

TSV Wafer Prepare

Chip on Substrate

Chip Stacking – 3D

3D Finalizing


2.5D Interposer TSV

8


TSV

Vias “First”

Vias drilled in bare Si

Vias filled with Poly-Si

Possible via resistance issues

Front-End FAB Process

Vias “Early/Middle”

W-CVD or

Cu plated

Front-End

FAB Process

Vias “Last” – Back Side

OSAT

Process

Active Interposer

Passive Interposer

Passive Interposer

substrate

3D IC Technology

9


Interposer Technology

10


Interposer Supply Chain – Logistics

SATWfr

SupportThin

Assy

Foundry/

IDMVias Early

Ship

Front Side

NiPdAu Pad

Wfr

SupportThin

Debond

Debond

Continue at Foundry

Send to SAT

Back Side

Bump

Back Side

Bump

Ship

Business Concerns :

• Ownership of TSV related failures

• Cost

• Agreed to metric for good known good Wfr

Technical Concerns :

• BOM Compatibility

Same bump metallurgies

Same passivation materials

• Thin wafer handling / shipping

Wafer Finish –

Can be at either

Foundry or OSAT

11


TSV RDL Bumping Packaging Test

Source : Yole, 2010

Who Is Doing What?


GSM Memory Conference, 2011

Interposers Increase Logic Capacity while Reducing Power

- Higher yields

- Over 2X FPGA capacity advantage

- 50% power reduction from40nm

FPGAs

- 5X reduction in latency

- 100X improvement in inter-die

bandwidth/watt

- Passive silicon interposer

: Minimizes heat flux issues

: 20X denser wire pitch

: 65 nm technology

13


Example : XILINX VIRTEX 5 market price

$6749.75

The Cost of TSV Is Compatible with the

Application Markets?

14

GPUDRAM DRAM

nVidia Quadro 2000 is priced at $600



$7832.37

$6749.75

Example : nVidia market price


Si Interposer Substrate : „A Si Interposer BGA PKG

with Cu-filled TSV and Multi layer Cu Plating Interconnect‟,

Kouichi Kumagai et al, 2008 ECTC

15


Si TSV Interposer RF Module


Source : Yole, 2010

3D Interposer Wafer Forecast by Application


3D Device TSV

18


solder ball

Cu pillar bump

TSV

EMC

Substrate

NCP 1Logic die

Memory die

NCP 0

Cu pillar

bump

TIM Heat spreader

Wide I/O memory die ( ~1200ubumps, no TSV)

28node (Cu pillar, 10um dia. TSV)

Substrate (14 x 14 /12 x 12 mm)

Die 2 Substrate interconnection : TCNCP

Die 2 Die interconnection : TCNCP

Heat spreader attach (exposed die

molding) :optional

Mobile Applications


Band Width Limit vs. Cost Budget

Affordable Cost

For the performance

$50(?)

$30

$20


Quad core AP + wide I/O memory price is assumed as $50

Dual core AP + LPDDR2 price is $20~$30

iPad2 BOM/Cost Analysis by iSupply April 2010

The Cost of TSV Is Compatible with the

Application Markets?


EMC

Substrate

Memory Applications

• DDR3 4Gb DIMM (1.066GHz) for server application is around $250

• DDR3 4Gb for PC is around $20


Application Driver Status Barrier

Image sensorsPerformance,

Form factorProduction None

CPUs + memory Performance16nm Si node or

beyond

Cost, process, yield,

infrastructure

GPUs + memory Performance 2014Cost, process, yield,

infrastructure

FPGAs Performance 2014Cost, process, yield,

infrastructure

Wide I/O memory

with processor

Performance (bandwidth

extension, lower power

consumption),

Form factor

2012~13


KGD, infrastructure

(including business

logistics)

Memory (stacked)Performance,

Form factor (z-height)2012


assembly

Key to 3D commercialization is a cost/performance ratio!

Source : TechSearch, 2011

3D TSV Applications


Documents

The Trend of TSV Packaging - · PDF fileThe Trend of TSV Packaging Dr. ChoonHeung Lee ... Package-on-Package Flip chip + Wire bonding TSV Wire bonding + Wire bonding Package Stacking