The Symbiotic Relationship Between Moore’s Law and Computational Modeling

Pete Woytowitz Computational Modeling and Reliability

Lam Research Corporation October 10, 2013

Lam Research Confidential

Lam Research Confidential Slide - 2

Moore’s Law and Computational Power Semiconductors and Integrated Circuits Computational Achievements & Opportunities Conclusions & Summary

Outline – Moore’s Law and Computational Modeling

Lam Research Confidential Slide - 3

Transistor counts alone don’t tell the entire story

– But they tell quite a bit !

Cost of FLOPS (floating point operations per second) driven by

– Transistor counts – Hardware architecture – Software (S/W) – Productivity (yield)

These are interrelated & together they drive the efficacy of computational modeling

Moore’s Law

Ref : Wikipedia (Moore’s Law)

Lam Research Confidential Slide - 4

GFLOPS – 1 Billion floating point operations per second

– Typical 2013 Machine – 70 GFLOPS (I7, 3.4 GHz) – Cost = $4K

Smaller dimensions allow more transistors per mm2 = more cache and memory

Smaller dimensions and distances between physical components = faster clock speeds

Moore’s Law and Computational Power

0

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

10,000,000,000

100,000,000,000

1,000,000,000,000

10,000,000,000,000

1/1/1961 11/6/1967 9/10/1974 7/15/1981 5/19/1988 3/24/1995 1/26/2002 11/30/2008 10/5/2015

Cost per GFLOP vs. Time

Cost per GFLOP

17M IBM 1620's$8.3 Trillion (1961)

Cray X-MP$33M (1984)

Two 16 CUP Biowulf Pen Pro$42K (1997)

Quad AMD 7970$0.73 (2012)

Sony Playstation$0.22 (2013)

Ref : Wikipedia (FLOPS )

How do they do it ?

Lam Research Confidential Slide - 5

Scaling, performance & costs – Time delay to switch transistor on/off, td

Performance improves with – Smaller devices – More complex devices (multi-core, GPU) – Better H/W architecture (3D, FinFET’s) – Better S/W architecture (RISC, Hyper-threading)

Moore’s Law and the Transistor

width theis andlength gate is thicknessoxide-gate is where

)/)(/()/(

WLT

IVTWLIVCt

ox

dsddoxdsddgd ∝∝

N N

+

+

-

Gate voltage high -> Transistor On

L W

Tox

50 to 500 nm

Lam Research Confidential Slide - 6

Chip performance to price goes up with

– Smaller scaling – Higher number of IC’s per wafer – Improved yield (lower defects)

Particles cause majority of defects

– Sputtering/etching of chamber materials – Flaking of deposits from chamber

components – Wear/abrasion of moving parts

Moore’s Law and Computational Power

densitydefect theis D

and area die theisA where and issues random and systematic

toduelost fractions are -1 and 1fraction yield theis where

s

ADr

r

rs

eY

YYYYYY

−=

−=

Ref: International Technology Roadmap for Semiconductors (ITRS), International SEMATECH, 2003 Ed.

Gate Length, L (nm)

Wafer Size (mm)

Lam Research Confidential Slide - 7

FEOL (this sequence repeated normally once)

Manufacturing Semiconductors & Integrated Circuits (IC’s)

Wafer Fab + CMP

* D/L/E – Multiple Dep/Litho/Etch Steps

Clean Dep Photo- resist Lithography Etch

Implantation / Diffusion D/L/E * Strip/Clean

Clean Deposition

(Metal/Insulator /Photoresist)

Lithography Etch Strip/Clean CMP

Clean Deposition/Etch (Metal/Insulator

/Photoresist) Assemble

BEOL (this sequence repeated at least twice for each layer)

WLP (this sequence repeated for each stack)

Lam Research Confidential Slide - 8

Semiconductor Processing Equipment Lam Equipment Examples

SABRE® Copper Electrofill Technology and Market Leadership

INOVA® PVD

Unique & Patented Technologies for Growth

ALTUS® CVD Tungsten Leadership in Tungsten Deposition SPEED® HDP CVD

Advanced High Aspect Ratio GapFill

GAMMA ® Dry Strip Best of Breed for Strip

SOLA ® UVTP First production-worthy UVTP

system

VECTOR® PECVD Productivity Benchmark for Dielectrics

Lam Research Confidential Slide - 9

Semiconductor Processing Equipment Anatomy of WFE (Wafer Fabrication Equipment)

Overall System

Sub-system / module

Component

Wafer Level

Device Level

Molecular Level

Lam Research Confidential Slide - 10

Computational Modeling Enabling Moore’s Law

Interaction of Wafer Deformations w. Photolithography Because of the very small feature sizes that need to be resolved (22 nm and less), many

seemingly small wafer distortions can have influence COMSOL structural mechanics module helped understand sensitivity of surface

distortions induced (possibly by previous processes) on detected “overlay” errors Plate theory in conjunction w. COMSOL plate elements used to help characterize

correlation of out-of-plane distortions with measurable overlay error

θy -θy

u=Overlay Error u = z θy

z

Undeformed Deformed

Lam Research Confidential Slide - 11

Computational Modeling Enabling Moore’s Law

Interaction of Wafer Deformations w. Photolithography Typical wafer bow before photolithography clamping may be 100 um Typical allowable overlay values may be < 10 nm Thru modeling can show that a freely warped wafer, displacing only ≈1 um, can

generate overlay errors on order of 10 nm

Litho Pattern 1 Results -Contours of Out of plane Displacements (mm), (max OOP displacement = 1.00 um, min OOP displacement = -.504 um)

Litho Pattern 1 Results (Contours of Out of Plane Displacements with Deformed Shape (mm))

Lam Research Confidential Slide - 12

Increasing aspect ratio’s and buckling sensitivity of lines in integrated circuits – Aspect ratio’s (A/R) of integrated circuit structures are growing

• Higher A/R for metal lines (interconnects) allow higher current with smaller footprint • Aspect ratio (A/R) for the gate electrode structure has increased by about 2x from 3.2 at

90nm node to around 5.6 at the 22nm nodes • Intermediate structures for manufacturing can exceed the final structure A/R

Computational Modeling Enabling Moore’s Law

ITRS Roadmap, Gate Electrode Scaling & Feature Aspect Ratio [1]

Typical Line Structure Classic Buckling Pattern Observed in Thin Film

Lam Research Confidential Slide - 13

Finite element analysis prediction of buckling and A/R limits – When t/b < .30 (A/R > 3.3) classical formula produces error < 15% – For A/R > 4 classical formula for critical buckling stress, σcr , has error < 5% – A/R’s from Figure 6 well within region of applicability of classical formula

• However, adjustment factor of .521 still needed to correlate theory to experiment

Computational Modeling Enabling Moore’s Law Buckling Sensitivity of Lines in Integrated Circuits

Limits of Applicability for Classical Stiffener Buckling Formula

b - 500nm

( )2

2

2

112

−=

btEk

cr υπσ

0

1000

2000

3000

4000

5000

6000

0 0.05 0.1 0.15 0.2 0.25

Effe

ctiv

e St

ress

(MPa

)

t/b Ratio

Critical Buckling Stress

Large Markers (Typical) Indicate Experimental Data at Consistent Film Stress, Modulus and A/R = (b/t)

Small Markers Indicate Theory

Ref: Woytowitz et. al., SES/ASME-AMD Joint Meeting , 2013

Young's Modules E – 70 GPa Poisson's Ratio = .30

b - 500nm

Lam Research Confidential Slide - 14

Component Level Analysis Gas Ring / Chamber Interface Thermal Analysis

Determine effectiveness of heater & coolant channels – Predict temperature uniformity on gas ring – Predict impact at chamber interface (o-ring) – Study heater size, attachment method

Chamber / Gas Ring

Temperature Contours

Gas Ring Heater

Lam Research Confidential Slide - 15

Power Input

Sub-System Reactor Analysis UV Lamp / Magnetron Design for SOLA

Model magnetrons/RF cavity/ SOLA lamp energy coupling Identify hardware modifications available for optimization of lamp

emission

Contour plots for electric potential (V) Contour plots for electric feile (V/m)

0.00E+00

1.00E+02

2.00E+02

3.00E+02

4.00E+02

5.00E+02

0 1 2 3 4 5

Powe

r Abs

orbe

d [W

]

Excitation Frequency [GHz]

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Sub-System Reactor Analysis Sealing and Flow Control Methodology (CVD Application)

Modulating flow into various chamber regions Effective conductance of off-set flow-paths

Lam Research Confidential Slide - 17

Sub-System Reactor Analysis Simulating Gas Flow in Chamber

Predict mass fraction of precursor as function of time Axisymmetric model of circularly

symmetric chamber Allows for optimized design of

inlet and outlet geometry Understand response of system

(important for throughput)

t = t0

t= t1

t= t2

Lam Research Confidential Slide - 18

Computational Modeling helps enable Moore’s Law thru • Detailed analysis of nano sized features and such physics as

CMP, photolithography, material compatibility (stress/stability), feature evolution (and more) • Component analysis to understand and optimize

Thermal uniformity, flow uniformity (CVD), RF Design, wafer stress and temperature • Continuous improvement (particle reduction, power consumption, device reliability)

Challenges and Developing Capabilities • Optimization – DOE, robust design, multi-variable & multi-objective • Efficient non-linear execution • Fracture, cohesive zones, advanced fracture, thin film material properties • System level mechanics problems (controls, dynamics, robotics) • Rarefied gas phase molecular modeling & chemistry (MD) • Ab-initio methods (quantum chemistry)

Conclusions • Computational modeling is heavily relied on and playing an increasingly important role • Continued correlation of modeling results to physical observations will develop best practices • Multi-physics modeling systems will continue to play increasingly important role

Computational Modeling Enabling Moore’s Law Summary & Conclusions