TECHNICAL REPORT

The RF System For The TITAN Mass Measurement Penning Trap

TITAN group, TRIUMF

Alexei Bylinskii

Chris Owen

August 31, 2007

1

ACKNOWLEDGEMENTS

• TITAN group: Paul Delheij, Jens Dilling, Vladimir Ryjkov, Alain Lapierre, Ryan Ringle, Mel Good, Mathew Smith, Maxime Brodeur, Thomas Brunner, Christian Champagne, Cecilia Leung • Amiya Mitra • Bill Rawnsley • Chris Owen • Don Dale • Hubert Hui • Iouri Bylinskii • Joseph Lu • Michael Laverty • Pierre Amaudrauz

2

ABSTRACT

TITAN is a state-of-the-art facility at TRIUMF for precisely measuring the masses of short-live nuclei by means of a Penning trap. Ion manipulation in the trap and the mass measurement are performed by means of RF electric fields. An RF system has been developed to generate and apply appropriate RF signals to 8 electrodes in the trap. Due to very short half-lives of isotopes measured at TITAN and a wide range of masses, the requirements on the RF system are unprecedented for this type of facility, in particular, a wide frequency range of 100 kHz to 70 MHz and amplitudes of up to 30 V. Consequently, high-power wideband RF amplifiers have been introduced to drive each electrode. The RF source is a single generator followed by a 180° phase splitter and a series of power splitters which produce the 8 channels, one going to each amplifier. A low-power RF switching matrix allows to apply different RF excitation modes by switching these channels and changing the RF phase on the electrodes, thus creating a dipole or a quadrupole field in the desired plane. A special set of filters also allows to individually bias every electrode for trapping field corrections. The system has been built up to function with only two RF channels temporarily, which is sufficient for the 11Li experiment currently in progress. It performed to specifications during the first run in August 2007.

3

TABLE OF CONTENTS

NOTATION 6 ABBREVIATIONS 6 INTRODUCTION 7 PERSPECTIVE 7

I. TITAN Set-Up 7 II. Nuclear Physics Motivation 7

III. Penning Trap And Mass Measurement 8 IV. RF Excitation Of Ions 9

RF SYSTEM REQUIREMENTS 11 RF SYSTEM OVERVIEW AND STATUS 12

I. System Concept And Main Parameters 12 II. System Status 14

SUBSYSTEMS 15 RF ELECTRODE NETWORK 15

I. Description 15 II. Estimated Capacitances And Inductances 17

1. Capacitance 17 2. Inductance 19

III. Network Resonance Measurements 20 1. Isolated Channels (8-port network) 20 2. X Channel And Y Channel (2-port network) 21

IV. Electrode Voltage Estimates 24 GENERATORS 27 180 SPLITTER MODULE 28

I. Design Concept 28 II. Design Details And Implementation 28

III. Performance Characteristics 30 1. Power Characteristics 30 2. Phase Characteristics 30 3. Switching Characteristics 31

RF AMPLIFIERS 32

I. Description And Performance 32 II. Auxiliary Systems 34

1. Thermal Protection 34 2. Gain Control 35 3. Input Attenuation 36 4. Power Supply 36

4

TERMINATIONS 37

I. Description 37 II. Performance 37

1. Matching 37 2. Heat-Up 37

DC BIASING MODULE 38 PEAK DETECTOR DIAGNOSTIC 40

I. Description 40 II. Calibration 43

INTEGRATION 44 SIMULATIONS 44

I. RF Simulation 44 II. DC Biasing And Low-Frequency Simulation 46

III. Simulation Limitations 47 TEST RESULTS 48

I. Low-Power (No RF Amplifiers) 48 1. Network Analyzer Measurements 48 2. Quadrupole Drive 49

II. Full System Tests 50 1. Voltage Calibration 50 2. Pulse Mode Response 51

CONCLUSION 53 SYSTEM STATUS AND FIRST EXPERIMENT 53 FUTURE DEVELOPMENT 53

I. Multiple Excitation Modes 53 II. Amplitude Modulation 54

III. Peak Detector Diagnostic 54 IV. Resonance 55

REFERENCES 56

APPENDICES 57 APPENDIX A System Turn ON/Off Procedure APPENDIX B 180 Splitter Module Schematic And PCB Layout APPENDIX C DC Biasing Module Schematic And PCB Layout APPENDIX D Mechanical Drawings Of The DC Biasing Module Box APPENDIX E DC Biasing Cable Specifications APPENDIX F Datasheets

5

NOTATION

m – ion mass S2n – two-neutron separation energy ω- – magnetron angular eigenfrequency ωz – axial angular eigenfrequency ω+ – reduced cyclotron angular eigenfrequency ωc – true cyclotron angular frequency ωrf – RF electric field frequency applied at the trap electrodes q – ion charge B – magnetic field strength in the middle of the trap υc – true cyclotron frequency Cii – self-capacitance of element i Cij – mutual capacitance between elements i and j Qi – total charge on element i Ui – potential on element I Lo – self-inductance M – mutual inductance l – wire length r – wire cross-section radius h – distance between parallel wires μ0 – permeability of free space

ABBREVIATIONS

ADC – Analog-to-Digital Converter AR – Amplifier Research CPET – Cooler Penning Trap CW – Continuous Wave DAQ – Data Acquisition EBIT – Electron Beam Ion Trap IC – Integrated Circuit ISAC – Isotope Separation and Acceleration MPET – Mass Measurement Penning Trap RF – Radio Frequency RFQ – Radio Frequency Quadrupole TITAN – TRIUMF’s Ion Trap for Atomic and Nuclear science TOF – Time-Of-Flight

6

INTRODUCTION

PERSPECTIVE I/ TITAN Set-Up TITAN (TRIUMF’s Ion Trap for Atomic and Nuclear science) is an experimental set-up in the ISAC (Isotope Separation and Acceleration) facility at TRIUMF for measuring the masses of exotic nuclei with very high accuracy. The target relative muncertainty is 10

ass -8 (δm/m). Masses of nuclei

with half-lives as short as 10 ms will be measured. These parameters make the facility state-of-the-art. The exotic nuclei are produced at the ISAC facility by means of a 500 MeV proton beam from the main cyclotron striking a target. In ionic form, they undergo mass-to-charge separation and only the isotope of interest is transported through the beamline. The ions are extracted from the ISAC beamline before the ISAC RFQ (Radio Frequency Quadrupole) and enter the TITAN RFQ, where they undergo gas cooling and bunching. Bunched ions are then transported to the EBIT (Electron Beam Ion Trap), where charge breeding takes place – an essential step in increasing the mass measurement resolution. The next stage is cooling in the CPET (Cooler Penning Trap), to be installed in the future. Finally, the ions are trapped in the MPET (Mass Measurement Penning Trap), where final ion manipulations and the mass measurement take place. The method of mass measurement is explained below, after “Nuclear Physics Motivation”.

FIG.1 TITAN set-up diagram [1].

II/ Nuclear Physics Motivation

FIG.2 11Li halo nucleus.

11Li TITAN’s first goal is to measure the mass of the 11Li isotope (half-life 8.6 ms). 11Li is a halo nucleus structure (see FIG.2), a Borromean system [2], which cannot be explained by conventional nuclear models such as the Shell Model. Alternative models have been proposed, the key parameter for which is the two-neutron separation energy, which can be found by

S2n = m11Li – m9Li – 2mn (Eq.1)

7

Unfortunately all previous measurements of the said parameter have been performed to insufficient precision and have not shown consistency. In fact, the most precise measurement to date was 25% (76keV) higher than the AME 2003 average (see FIG.3).

75

88

93

91

Other planned mass measurements include 74Rb to test the unitarity of the CKM matrix, isotopes in the neutron-rich area of the chart to study nuclear structure near the neutron drip-line, and seed nuclei of 92Mo to test the significance of the neutrino-induced Beta decay process in supernovae. [3]

Mistral 2003

FIG.3 S2n parameter measurements for 11Li by different laboroatories, AME2003.

III/ Penning Trap And Mass Measurement The principle behind the mass measurements is a Penning trap [4]. It consists of a ring electrode and two cap electrodes, which are hyperboloids of revolution (see FIG.4). A DC voltage is applied between the ring electrode and the cap electrodes. The electrode structure sits in the core of a strong superconducting solenoid with the magnetic field aligned with the trap axis. In this superposition of electric and magnetic fields, the ions perform three harmonic eigenmotions: axial oscillations in the electric potential well due to the cap electrodes with angular frequency ωz, as well as magnetron motion ω- (slow drift around the trap axis) and modified cyclotron motion ω+ (fast motion around a small orbit) due to the Lorenz force (see FIG.5). The relative magnitudes of the eigenfrequencies are as follows

FIG.4 Penning trap concept.[5]

FIG.5 Ion motion in a Penning trap. [5]

ω- < ωz < ω+ (Eq.2) The amplitudes and phases of the eigenmotions depend on initial conditions (velocity of the ions when entering the trap, time of closure of the trap, displacement from beam axis). The sum of the magnetron and the reduced cyclotron eigenfrequencies is equal to the cyclotron frequency of the ion precessing in the magnetic field: ω+ + ω- = ωc = (q/m)*B (Eq.3)

8

At TITAN the goal is to measure the cyclotron frequency ωc from which mass can be obtained, given that the charge state and the magnetic field are known. An azimuthal quadrupole Radio Frequency (RF) electric field with frequency close to the sum of the magnetron and the reduced cyclotron eigenfrequencies will couple the two eigenmotions. During the conversion of magnetron motion to cyclotron motion (shown in FIG.6), the ions gain radial energy (high frequency motion at large radius). If RF frequency equals the cyclotron frequency, the conversion is complete and the ions have the highest magnetic moment at the end of the conversion, when they are ejected from the trap. The magnetic field gradient at the fringe of the solenoid accelerates the ions towards an MCP detector, where time-of-flight (TOF) from the moment of ejection is registered. The minimum in the time-of-flight data versus RF frequency corresponds to the cyclotron frequency ωc (since the ions acquire the highest magnetic moment and get the strongest kick from the magnetic field gradient). From Eq.3, mass can then be obtained.

FIG.6 Conversion of magnetron motion to cyclotron motion with RF quadrupole excitation (a – first half of conversion, b – second half). [4]

FIG.7 Typical shape of the time-of-flight spectrum. [4]

A typical shape of the spectrum is shown in FIG.7. IV/ RF Excitation Of Ions The motion of ions in the trap can be manipulated by applying various configurations of an RF electric field. A dipole electric field in the appropriate direction applied at one of the eigenfrequencies will excite the associated eigenmotion. For example, dipole RF along the trap axis applied at frequency ωz will drive axial oscillations, while dipole RF in the X-Y plane will drive magnetron motion if its frequency is ω- and reduced cyclotron motion if its frequency is ω+. The most important application of such eignemotion manipulation is sample cleaning; if the dipole RF frequency is scanned over the desired range, ions with

9

masses falling in that range will be driven to very high amplitude until they hit the wall of the trap, leaving only the desired ions trapped. Another application is adjustment of the magnetron orbit, which translates into the maximum radial energy of the ion during the cyclotron quadrupole excitation used for mass measurements (described above). A quadrupole electric field in the appropriate plane applied at the sum of two eigenfrequencies will couple the associated eigenmotions, causing a beating between them. Given an RF field in the X-Y plane ωrf = ω- + ω+ = ωc, magnetron and cyclotron motions are coupled and this effect is used for the mass measurement, as described above. Similarly, ωrf = ωz + ω+ in the X-Z or Y-Z plane will couple axial and reduced cyclotron motions, while ωrf = ωz + ω- will couple axial and magnetron motions.

10

RF SYSTEM REQUIREMENTS The RF system is key to ion manipulation in the Penning trap and to mass measurements. For TITAN, the requirements on the RF system are unusual for a Penning trap facility due to the short-lived nature of the isotopes and the high accuracy desired. TABLE 1 summarizes the key requirements and the reasons behind these requirements. TABLE 1. RF System Requirements REQUIREMENT REASON Frequency 100 kHz to 70 MHz or 10 Hz to 1 kHz (magnetron excitation)

The eigenfrequencies and the cyclotron frequency are mass-dependent. In order to be able to excite resonantly ions with a wide variety of masses from very heavy nuclei to hydrogen nucleus (υc = 57 MHz), a wide RF range is required. Magnetron frequency is mass-independent to first order and is under 1kHz as determined by trap parameters.

RF amplitude 50 mV to 30 V base to peak

The time of cyclotron quadrupole excitation must equal the time it takes for magnetron motion to be completely converted to cyclotron if a signal is to be seen at the MCP. Because the nuclei are short-lived, the excitation time is limited by the half-life (if the ions decay before they get to the detector, the statistical error inceases). The conversion time can be shortened by increasing the amplitude of the RF field. Up to 30 V amplitude is required for the shortest-lived nuclei (11Li with 8.6 ms half-life). On the other hand, stable nuclei used for reference measurements can be irradiated with RF for longer periods of time, thus requiring very small RF amplitudes. Longer irradiation time increases TOF peak resolution, which is essential for the reference measurements.

RF amplitude uncertainty < 1% This maximum RF level error determines the margin within which the RF irradiation time can be different from the conversion time. A bigger difference will result in smaller radial energy of the ion at the point of ejection from the trap and consequently much weaker signal at the MCP. Also, a wider TOF peak results and decreases the resolution.

RF diagnostic: peak detector In order to balance RF amplitude on different channels, to observe the <1% amplitude stability requirement and to be aware of system failure, an RF diagnostic is required with information about the RF amplitude on the RF electrodes.

Phase difference between opposite poles (electrodes) < 1°

Bigger phase difference may cause unwanted ion oscillations in the trap and unpredictable non-linearities in the TOF data.

Pulse mode operation; pulse width 1 ms to 1 s, depending on half-life of isotope under test

RF must be turned on once the ions are loaded into the trap, and turned off prior to ejection. The RF excitation time (pulse width) is limited by the half-life, as discussed above.

Pulse shape repeatability Needed for good TOF resolution. Pulse switch time < 100 μs Switch time one order of magnitude shorter than pulse width for the

shortest-lived nuclei. Capable of switching between all RF excitation modes (dipole for each eigenfrequency and quadrupole for each pair of eigenfrequencies, 6 in total)

Maximum ion manipulation capability.

Switching time between RF excitation modes < 1ms

This switching time must be at least an order of magnitude shorter than the half-life of the shortest-lived nuclei.

–10V to +10V DC bias on individual RF electrodes

RF electrodes in the TITAN Penning trap are also used for the static electric field corrections; therefore DC biasing must be performed.

11

RF SYSTEM OVERVIEW AND STATUS I/ System Concept And Main Parameters There are 8 electrodes in the TITAN MPET available for RF. They are called guard electrodes and are also used for electric field corrections. Each of these electrodes is a quarter of a segmented flat ring; there are four guard electrodes upstream of the hyperbolic ring electrode and four downstream as shown in FIG.8. All the Penning trap electrodes are gold-coated copper. The voltages are delivered to the electrodes by means of 60 cm long, 0.8 mm diameter copper wires, running parallel to each other. The electrodes and the wires sit in ultra-high vacuum. The wires attach to vacuum feedthroughs. A conceptual diagram of the rest of the system is shown in FIG.9. On the outside of the feedthroughs sits the DC Biasing Module. It has 8 inputs for 100 kHz – 70 MHz RF and 8 inputs for DC to 1 kHz signals. The module has 8 outputs, each connecting to a feedthrough pin corresponding to a guard electrode. Each output gets a superposition of one high-frequency and one low-frequency signal from the inputs, while the high-frequency inputs and the low-frequency inputs themselves are isolated from each other by a set of filters. This ensures DC source protection from RF and RF source protection from output biasing. Each RF channel is driven by a 25W RF amplifier from Amplifier Research (model KMA1020). The power is dumped into 50 Ω loads mounted on heat sinks. The voltages in the lines are sampled before the loads by the RF inputs of the DC Biasing Module and transmitted to the electrodes; very little power is dumped in this pathway. The maximum amplifier power of 25 W corresponds to 50 V RF amplitude across a 50 Ω load, which is enough headroom above the 30 V requirement. At the same point (before the loads), voltages are sampled by Diagnostic Modules, which provide a differential DC output between 0 and 2 V corresponding to an RF peak-to-peak value. The differential output goes through an ADC (Analog-to-Digital Converter) into the DAQ (Data Acquisition) system. The RF amplifiers have a gain of approximately +44 dB. The output power (and thus amplitude) is controlled by varying the input signal at the source. For fine-tuning, however, amplifier gains can be adjusted manually by turning a potentiometer on the Gain Control circuit; this is useful for balancing the amplitudes in channels driven by different amplifiers.

96 mm

Guard electrodes

FIG.8 RF (guard) electrodes in the TITAN MPET

12

There are two RF signal sources: two 80MHz Agilent function generators. The frequency scan is controlled by a signal from the DAQ system. Typically one generator is set up for one type of excitation (cyclotron quadrupole) and the other for another type of excitation (cyclotron dipole). The module that follows, the 180 Splitter, has two built-in switches that allow it to alternate between the inputs (from one generator or the other) and to switch the input signal ON and OFF. The first capability allows to quickly switch between excitation frequencies and the other allows to provide pulse-mode RF. The 180 Splitter Module itself is a device that gives 4 outputs of the 0° phase and 4 outputs of the 180° phase RF with approximately +8 dB gain with respect to the input signal. The RF switching matrix that follows connects any of the 8 channels coming out of the Splitter to any of the 8 inputs to the RF amplifiers, depending on the TTL logic input determined by the desired RF excitation configuration.

RF Generator 1

RF Generator 2

180 deg. Splitter

180°

0°

Switching matrix

RF High-Power

Amplifiers

50 ohm Loads

1X-

1X+

2Y+

2Y-

2X+

2X-

1Y+

1Y-

DiagnosticWires and electrodes in vacuum

Gen1 / Gen2 switch

RF On / Off

DC bias voltages

DC Biasing

FIG.9 RF system diagram.

13

II/ System Status The system has been built up to the functionality required for the 11Li experiment (shown in FIG. 10). Because of the high purity of the beam, dipole excitation for sample cleaning is not required. Furthermore, magnetron radius is controlled by setting initial conditions with Lorenz steerers at the entrance to the trap. As a result, only cyclotron quadrupole excitation is required, eliminating the need for an RF switching matrix and all 8 amplifiers, one to drive each electrode. In fact, with a fixed excitation configuration like this, only 2 RF amplifiers are needed, one to drive each phase (0° or 180°). Each of the high-power channels is then hard-wired to the appropriate electrodes within the DC Biasing Module. Most of the mof the system habeen completely developed anused at partial functionality fo

odules ve

d only

r the

y a

y one

180°

s

y

en o

ects el. The

11Li experiment. Only one input isused on the 180 Splitter since onlsingle generator is needed to provide the cyclotron frequency. Onlof the 0° outputs and one of theoutputs is used (theoutput channels have excellent isolation, so thidoes not affect the Splitter performance). Onltwo of the peak detectors have bebuilt – one for each channel. Only two 50 Ω loads have been installed and only twinputs to the DC Biasing Module are being used. Hard-wiring within the module connall the “X” electrodes to one channel and all the “Y” electrodes to the other channjumpers are easily removed to restore the capability of providing RF independently to all 8 electrodes.

RF Generator 1

RF Generator 2

180 deg. Splitter

180°

0°

RF High-Power

Amplifiers

50 ohm Loads

1X-

1X+

2Y+

2Y-

2X+

2X-

1Y+

1Y-

Diagnostic

Wires and electrodes in vacuum

Gen1 / Gen2 switch

RF On / Off

DC bias voltages

DC Biasing

FIG.10 RF system built up for the 11Li experiment.

The system is easily expanded to full functionality by buying the remaining amplifiers, adding more loads and peak detectors and re-wiring the DC Biasing module, as well as buying and installing any additional miscellaneous hardware required. Additional design nuances and improvements should also be considered, as described in the “Future Development” section later in the Conclusion.

14

SUBSYSTEMS

RF ELECTRODE NETWORK I/ Description FIG.11 shows an expanded view of all the TITAN Penning trap electrodes with spatial axes defined. The Z-axis points downstream of the beamline. The Y-axis is vertical and the X-axis is horizontal. The RF electrodes (these are also electrostatic correction electrodes) are labelled 1X+, 1X-, 1Y+, 1Y-, 2X+, 2X-, 2Y+, 2Y- depending on relative position. A particular RF field configuration (dipole, quadrupole, octupole) is achieved in the trap center by applying either 0° or 180° phase RF to the appropriate electrodes. TABLE 2 below summarizes the phase configurations required for all RF field configurations and how each is used at TITAN.

z

x

y

Y2+

Y1+

Y2-

Y1-

X2+

X1+

X2-

X1-

FIG.11 RF electrode configuration in the TITAN MPET [6].

TABLE 2. Electrode phase configurations for different RF field configurations.

RF phase on each electrode (°) RF Field Configuration

Applications 1X- 1X+ 1Y- 1Y+ 2X- 2X+ 2Y- 2Y+

Azimuthal Quadrupole

Cyclotron frequency determination

0 0 180 180 0 0 180 180

XZ Quadrupole

Axial to cyclotron conversion

0 180 n n 180 0 n n

YZ Quadrupole

Axial to cyclotron conversion

n n 0 180 n n 180 0

15

X Dipole Magnetron or reduced cyclotron excitation

0 180 n n 0 180 n n

Y Dipole Magnetron or reduced cyclotron excitation

n n 0 180 n n 0 180

“XY” Dipole Magnetron or reduced cyclotron excitation

0 180 0 180 0 180 0 180

Z Dipole Axial excitation 0 0 n

0 0 n

0 n 0

0 n 0

180 180 n

180 180 n

180 n 180

180 n 180

Octupole Will not be used in near future

0 0 180 180 180 180 0 0

The wires running in vacuum between the feedthroughs and the trap electrodes are supported by ceramic holders shown in FIG.12. The hole configuration determines the wire separation, although in reality they may be closer together or further apart due to slack between holders. The wires are approximately 60 cm long and 0.8 mm in diameter, running parallel to each other. The ground reference is located at the round edge of the holder.

(a) (b)

0.8 mm7.5 mm

2.5 mm

FIG.12 Vacuum wires configuration: a) Ceramic holder b) Hole geometry (zoom)

This configuration of electrodes and wires in vacuum forms an 8-port RF network, where every element has a capacitance with respect to ground (situated at the enclosing cylinder), some self-inductance, as well as a mutual capacitance and a mutual inductance with respect to every other element. The wires, in particular, behave as coupled transmission lines. This is a very complex network and various approaches have been taken to investigate its behaviour. The goal is to have a stable response across the required frequency range of 100 kHz – 70 MHz with the same voltage at the RF electrodes that is seen at the feedthroughs.

16

II/ Estimated Capacitances And Inductances 1. Capacitance a) Electrodes The estimated capacitance of each guard (RF) electrode to ground is 3±1 pF, as per electric field calculations performed by Vladimir Ryjkov (contact him for more details). The estimated mutual capacitance of adjacent guard electrodes is 0.17±0.05 pF, according to the parallel plate approximation using the closest edges of the electrodes. b) Feedthroughs The capacitance of the feedthrough pins to ground was measured to be 5±1 pF each using a capacitance meter. c) Wires The wire configuration was simulated in 2D in COMSOL Multiphysics 3.2 as shown in FIG.13. The ground was assumed to be at the vacuum cylinder, which encloses the wires and the electrodes. The effect due to grounded small metal components coming close to the wires was deemed negligible and was therefore ignored.

7.5mm

2.5mm

51.0mm

Ground cylinder

37.0mm

wires

FIG.13 Geometry simulated in COMSOL.

The wires are numbered as in FIG.14 (wires 1,2,3,7,8,9,12 are for the RF electrodes). TABLE 3 contains self-capacitances (Cii elements, marked red) of the 13 wires and the mutual capacitances of all pairs (Cij elements). The self-capacitances have been calculated according to this definition:

1

13 12 10 9 7

65432

8 11

FIG.14 Wire numbering

Cii = Qi / Ui given that all electrode potentials are equal. (Eq.4 [7]) The mutual capacitances have been calculated according to this definition:

Cij = Qi / Uj given that all electrode potentials but Uj are zero. (Eq.5 [7]) Note that the matrix is symmetric (i.e. Cji = Cij). The self-capacitances (along the diagonal) have been highlighted red. Mutual capacitances exceeding 1 pF have been bolded.

17

TABLE 3. Wire capacitance matrix. 1 2 3 4 5 6 7 8 9 10 11 12 13

1 5.13 1.31 0.25 0.10 0.05 0.04 3.15 0.26 0.05 0.03 0.00 0.06 0.002 1.31 2.11 1.18 0.24 0.09 0.05 2.93 2.85 0.18 0.05 0.03 0.35 0.043 0.25 1.18 1.25 1.14 0.22 0.10 0.22 2.56 2.51 0.17 0.05 1.76 0.244 0.10 0.24 1.14 1.25 1.18 0.25 0.05 0.17 2.51 2.56 0.22 0.24 1.765 0.05 0.09 0.22 1.18 2.11 1.31 0.03 0.05 0.18 2.85 2.93 0.04 0.356 0.04 0.05 0.10 0.25 1.31 5.13 0.02 0.03 0.05 0.26 3.15 0.01 0.067 3.15 2.93 0.22 0.05 0.03 0.02 4.01 0.94 0.05 0.01 0.01 0.25 0.028 0.26 2.85 2.56 0.17 0.05 0.03 0.94 2.15 0.48 0.04 0.01 2.55 0.119 0.05 0.18 2.51 2.51 0.18 0.05 0.05 0.48 1.32 0.48 0.05 2.41 2.41

10 0.03 0.05 0.17 2.56 2.85 0.26 0.01 0.04 0.48 2.15 0.94 0.11 2.5511 0.00 0.03 0.05 0.22 2.93 3.15 0.01 0.01 0.05 0.94 4.01 0.02 0.2512 0.06 0.35 1.76 0.24 0.04 0.01 0.25 2.55 2.41 0.11 0.02 3.38 0.8513 0.00 0.04 0.24 1.76 0.35 0.06 0.02 0.11 2.41 2.55 0.25 0.85 3.38

In COMSOL, the calculations were done according to these steps: - Assign boundary conditions consistent with the definition of the capacitance element to be calculated (an arbitrary voltage; 1 V was used in all cases). For self-capacitances, for example, all electrodes were assigned +1V. - Solve the system: potentials and electric fields are calculated. The potential distribution for the self-capacitance calculation, for example is shown in FIG.15.

FIG.15 Potential distribution in the space around the wires with 1 V applied to all of them.

- Compute the surface integral of surface charge density on the desired electrode to get its charge. - Compute the desired capacitance element by dividing the calculated charge by the assigned potential. d) Overall The capacitance of each channel was measured by means of a capacitance meter with respect to ground. The measurement was done at the BNC connectors right outside of the feedthroughs. The total capacitance was found to be 20±5 pF. With 5 pF for the BNC connector (measured separately), 5 pF for the feedthrough pin, 5 pF for the wire (maximum element of the matrix in TABLE 3) and 3 pF for the electrode, the 20 pF measurement agrees with these estimates.

18

2. Inductance a) Wires The estimated self-inductance of each wires is 0.8±0.2 μH, calculated with the following formula based on the high-frequency assumption and ground at infinity assumption:

⎟⎟⎠

⎞⎜⎜⎝

⎛−−−= 2

20

0 2412ln

2 lr

lr

rll

Lππ

μ (Eq.6 [8])

where l is wire length and r is wire radius. The estimated mutual inductance of a closest pair of wires is 0.6±0.1 μH, calculated with the following formula:

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+−

++=

lh

lhl

hhll

M2222

0 1ln2πμ

(Eq.7 [8])

where l is wire length and h is wire separation. b) Electrodes And Feedthroughs The self-inductance and mutual inductance of the RF electrodes and feedthrough pins was deemed negligible and was not calculated.

19

III/ Network Resonance Measurements 1. Isolated Channels (8-port network) a) Reflection Network Analyzer measurements were performed on the network to characterize its behaviour in the required frequency range. FIG.16 shows plots of reflected power (dB with respect to the source power) from each of the ports versus frequency. Note that this measurement was done by calibrating the reflection port cable of the Network Analyzer, then connecting it to a 50 Ω terminator and the BNC jack of the desired port on the temporary lid, which is set up above the feedthrough pins and connected to them via 6 cm long jumpers. Thus, only one port is driven at a time, while all the rest are floating.

Reflected power from different ports of the 8-port network vs. frequency

-80

-70

-60

-50

-40

-30

-20

-10

00 10 20 30 40 50 60 70

Frequency (MHz)

Ref

lect

ed P

ower

wrt

Sou

rce

(dB

)

X1+ X1- X2+ X2- Y1+ Y1- Y2+ Y2-

FIG.16 Reflected power from different ports of the 8-port network vs. frequency.

A resonant effect can be seen on these graphs, which occurs between 50 and 60 MHz (maximum reflected power corresponds to strong mismatch). b) Transmission FIG.17 shows plots of transmitted power (dB with respect to the source power) from the driven X1+ port (terminated) to each of the other ports (all except X1+ floating). Maximum coupling occurs between 60 and 70 MHz. This corresponds to a dip in the reflected power on FIG.16.

20

Transmitted power to different ports of the 8-port network from the X1+ port vs. frequency

-80

-70

-60

-50

-40

-30

-20

-10

00 10 20 30 40 50 60 70

Frequency (MHz)

Tran

smitt

ed P

ower

wrt

Sou

rce

(dB

)

X1- X2+ X2- Y1+ Y1- Y2+ Y2-

FIG.17 Transmitted power to different ports from the X1+ port.

2. X Channel And Y Channel (2-port network) For these measurements, all the X inputs were jumpered together and all the Y inputs were jumpered together to represent the quadrupole configuration. a) Single Phase Drive For these measurements, either the X port or the Y port was driven (with 50 Ω terminated input) and reflected power was measured, as well as transmitted power to the opposite channel. FIG. 18 displays the results. Note that the reflection and transmission parameters are very similar to the 8-port network results above. Note also that the X and Y channels are symmetrical.

21

Reflected And Transmitted Power In the 2-port Network (X and Y) vs. Frequency

-80

-70

-60

-50

-40

-30

-20

-10

00 10 20 30 40 50 60 70

Frequency (MHz)

Frac

tion

of in

put p

ower

(dB

)Reflection from X Reflection from YTransmission from X to Y Transmission from Y to XQuadrupole Drive Reflection

FIG.18 S-parameters of the 2-port network.

b) Quadrupole Drive To simulate quadrupole drive, a temporary resistive phase splitter was installed to provide 0° phase to the X channel and 180° phase to the Y channel. Both inputs are 50 Ω terminated. The schematic is shown in FIG.19. The reflected power from the input in this configuration is the blue graph in FIG.18. Note that the network characteristics change in the quadrupole configuration; there is a much stronger resonance between 40 and 70 MHz. On the other hand, the temporary splitter itself is not a well-behaved RF circuit and may be significantly contributing to the effect.

FIG.19 Temporary phase splitter schematic.

Voltage was also sampled by an oscilloscope at one of the 0° phase feedthrough pins and at one of the 180° phase feedthrough pins, while the input was provided from an RF generator in sweep mode. The oscilloscope probes were set to 10x attenuation to minimize their effect. The voltage vs. frequency graph is shown in FIG.20. 22

Quadrupole Drive Feedthrough Voltages vs. Frequency

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0 20 40 60 80

Frequency (MHz)

RF

Volta

ge (V

)0 degree phase 180 degree phase

The resonance point (maximum attenuation at the feedthroughs) is observed at 42 MHz

dditional resonances at higher frequencies.

d as MHz range. Some of the effect is fixed by

e DC Biasing Module. This is discussed later.

FIG.20 RF seen on feedthroughs in the quadrupole drive configuration with the temporary phase splitter.

and the frequency response is reasonably flat between 100 kHz and 20 MHz. Note a It can be seen from the results above that the network by itself is not as well behavedesired, with resonance in the 100 kHz to 70 th

23

Network Analyzer (Function

Generator)

Oscilloscope

1 kCopper wire Electrode

Ground plateCoaxial cable

T piece

60 cm

1 cm

50 ohm terminator

Probe

FIG.21 The test set-up.

V/ Electrode Voltage EstimatesI

he network characteristic of greatest interest is the actual RF voltage on the electrodes; tely, it does not necessarily correspond to the

oltage that is seen on the peak detector at the 50 Ω load. To find the relationship

the

utput of a network analyzer used as a function generator. Near the termination, voltage

The results are summarized in TABLE 4 and FIG.22 below. Note that the reference measurements were done at the 50 Ω load with the wire disconnected, in order to calibrate the readings with respect to the effect of the oscilloscope probe capacitance and

k) 5.120

1 3.640 3.640 3.644 0 10 0.896 0.912 2

Tit must be know to within 1%. Unfortunavbetween the two voltages, measurements were done on a simple prototype and PSPICE simulations were performed. Some steps have been taken to correct the discrepancy. A rudimentary set-up has been produced on a test bench to approximate the channel for asingle electrode (FIG.21). The set-up involves a terminated coaxial cable connected toois sampled from a T-piece. The voltage is delivered to a 60 cm long copper wire secured 1 cm above the ground plane and ending with a small copper plate simulating the electrode. Voltage readings were taken with an oscilloscope at different points of the copper wire for several frequencies in the 100 kHz to 70 MHz range.

the 1kΩ resistor connected in series with the probe. TABLE 4 Results of voltage measurements on the test set-up. Frequency reference at electrode half way at 50 ohm

MHz V (Pk-Pk) V (Pk-Pk) V (Pk-Pk) V (Pk-P0.1 5.120 5.120 5.120

3.640.91 0.904

70 0.214 0.382 0.356 0.252

24

Voltage At Different Points Of The Test Set-Up vs. Frequency

0.1

1

10

0.1 1 10 100

Frequency (MHz)

Volta

ge (V

pk-

pk)

REF at electrode half way at 50 ohm

FIG.22 Voltage measurements on the test set-up.

FIG.22 shows the transformer effect of the network at higher frequencies: the voltage increases towards the end of the wire. PSPICE simulations of this network suggest the insertion of a resistor in series with the wire in order to reduce the transformer effect by lowering the Q-value of the LC equivalent. Further measurements showed that 150 Ω is the optimal resistance value. FIG.23 is a graph of the fractional correction of the voltages by this resistor relative to the reference voltages. The transformer effect is almost completely removed.

25

Voltage Correction By 150 Ohm vs. Frequency

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0 10 20 30 40 50 60 70 80

Frequency (MHz)

V/Vr

ef

at electrode corrected

FIG.23 Electrode voltage correction by 150 ohm resistor on the test set-up.

Note that this is a very rough investigation of the network behaviour and does not take into account coupling to the other channels. Also, the re-created geometry is not exact. Better simulations involving the whole system can be found in the Integration section.

26

GENERATORS The RF generators are purchased items. These are Agilent 33250A arbitrary waveform generators that operate up to 80 MHz (see FIG.24, datasheet in Appendix F). The amplitude on the generators is set to the required value prior to the run. During the run, frequency is modulated by and external signal from the control system. The frequency scan is a step function in time within a narrow frequency range. For more details on the frequency scanning parameters for various experiments, contact Vladimir Ryjkov.

FIG.24 Agilent 80MHz arbitrary waveform generator.

Note that the generators can either be frequency-modulated or amplitude-modulated, but not both at once. This is the reason for external switching / amplitude modulation implemented for pulsed RF.

27

180 SPLITTER MODULE I/ Design Concept The conceptual diagram of the 180 Splitter Module is shown in FIG.25. There are two RF inputs. The first RF switch selects one of the inputs (the other input is terminated in 50 Ω within the switch). The second RF switch either enables the input, connecting it to the input of the splitter (shown in red), or disables it. In both cases, the input is terminated in 50 Ω; the input impedance of the splitter is very high. Note that the generator signal is always dissipated in a load to avoid reflection of the power back to the source. The 180° phase splitter is a differential output amplifier. Each of the outputs goes to a 2-way Wye resistive power splitter [9]. Then, each of the four channels is amplified by a low-power RF amplifier (shown in green) and split 2 ways once again by a resistive Owen splitter [10]. As a result, there are 4 outputs at 0° phase RF and 4 outputs at 180° phase RF, well-isolated from each other due to the Owen splitters, allowing any number to be used without affecting the performance.

FIG.25 180 Splitter Module conceptual diagram.

II/ Design Details And Implementation The detailed schematic and PCB layout for the 180 Splitter Module can be found in Appendix B. The two switches are SA630 single-pole double-throw RF switches (datasheet in Appendix F). Unused inputs/outputs are terminated internally in 50 Ω, providing OFF matching. According to the manufacturer, the loss is below 1 dB and the off channel isolation is better than 60 dB. The switches are wideband and perform to the specifications mentioned above in the DC to 100 MHz frequency range. The specified switching time is 20 ns. The switching is controlled by TTL logic signals. External power supply required is +5V. The differential output amplifier is an AD8015 device (datasheet in Appendix F). The specified frequency range is up to 240 MHz. The device provides a differential output as a function of the input current. The output impedance is 50 Ω and the input impedance is

28

increased by a series 3.3 kΩ resistor to limit the input current. The RF signal is still terminated in 50 Ω prior to the input. The external power supply required is +5V. The Wye splitters have a –6 dB attenuation and provide a 50 Ω match. The low-power RF amplifiers are Gali-55+ monolithic amplifiers from Mini-Circuits (datasheet in Appendix F) specified for DC to 4 GHz frequency range and a typical gain of 20 dB at lower frequencies. The IC (Integrated Circuit) itself requires no external power supply, but the output is biased from a 12 V source through a 187.5 Ω resistor. This resistor was chosen to lower the saturation point in order to protect the high-power RF amplifiers after the 180 Splitter Module (discussed later). The Owen splitter gives a –9.6 dB attenuation, -9.6 dB port-to-port isolation and a 50 Ω match. The RF path through the module joining the devices described above consists of 50 Ω impedance tracks for best matching. Also, the RF input and output of every IC contains a 0.2 μF DC blocking capacitor, which passes all frequencies above 100 kHz (see FIG.26). This is required because the device inputs and outputs are internally biased.

FIG.26 DC blocking characteristics of 0.2 μF capacitor in a 50 Ω impedance system: voltage passing from a 1V AC source vs. frequency.

The module has been built on the PCB (Appendix B) and installed in a NIM bin (see FIG.27). It gets power from a +12 V NIM power supply. The +5 V rail is provided by an L7805 fixed voltage regulator (datasheet in Appendix F). The RF inputs and outputs are SMA jacks. The two TTL logic inputs for the switches are LEMO jacks. The module is equipped wLEDs to indicate power and switching status; they are driven by a 74LS04 hex inverting buffer (datasheet in Appendix F).

ith

FIG.27 180 Splitter Module complete inside the NIM bin.

29

III/ Performance Characteristics 1. Power Characteristics The high-power amplifiers from AR following the splitter will give a maximum output of 25 W at 1 mW input (0 dBm). A much bigger input can damage these amplifiers. The Gali-55+ low-power amplifiers can give up to +20 dBm output in the required frequency range. Since the Owen splitters have a –10 dB attenuation, this leaves +10 dBm potentially going to the high-power amplifiers. The biasing resistor at the output of the Gali-55+ was increased from the optimum value of 150 Ω to 187.5 Ω in order to set the 1 dB compression point to around +10 dBm (output) as to provide 0 dBm at the Splitter output. The gain compression plot at different frequencies for the overall 180 Splitter Module is shown in FIG.28. The 1 dB compression point has been set slightly higher than required, at around +1.3 dBm, in order to still operate in the linear region at maximum output of the high-power amplifiers, while still protecting them from a much higher input. Note that for 0 dBm output, the input RF amplitude is 280 mVpp, which has been marked as the maximum limit on the RF generators.

Gain Compression Curve Of 180 Splitter Module

-30

-25

-20

-15

-10

-5

0

5

10

-40 -30 -20 -10 0 10 20

Input Power (dBm)

Out

put P

ower

(dB

m)

10 MHz 30 MHz 70 MHz

High-power RF amplifiers input for max (25 W) output

P1dB

FIG.28 180 Splitter Module gain compression plot for different frequencies.

The –10 dB output to output isolation has also been verified. 2. Phase Characteristics The phase difference between opposite phase channels was measured to be 180±1°. The phase difference between same-phase channels was measured to be 0±1°. Amplitude difference of opposite-phase channels: < 16 mV across frequency range

and 340 mVpp input

30

3. Switching Characteristics

Slew rate: < 40 μs across frequency range. Overshoot: +200 mV Reflection when “Freq. Select” switch OFF: < -18 dB across frequency range Reflection when “Freq. Select” switch ON and “Enable” switch OFF: < -15 dB

across frequency range Reflection when both switches ON: < -20 dB across frequency range

31

RF AMPLIFIERS I/ Description And Performance The amplifiers are 25W class A power amplifiers from Amplifier Research, model KMA1020M11 (part # 1-60-633-011). (The serial numbers of the two units currently installed are 10289-1,-2.). AR datasheets can be found in Appendix F. Maximum power output is 25 W, at approximately 1 mW input (0 dBm). Input power limiting is provided within the 180 Splitter Module to avoid over-driving. However, caution by the operator is also required since the saturation point of the 180 Splitter is just over 3 dBm, which would correspond to 50 W output if the high-power amplifier did not saturate. An input of 3 dBm could damage this amplifier. The input and output impedance is 50 Ω. The output mismatch tolerance is 3:1. This means that the amplifier SHOULD NEVER BE TURNED ON UNLESS THE OUTPUT IS TERMINATED IN 50 Ω. Turning on the power when the output is left open may irreversibly damage the amplifier. Follow the detailed turn-on procedure, which can be found in Appendix A. The frequency range of operation is 100 kHz to 70 MHz with gain flatness within ±1.5dB. Results for gain measurements at different power levels across the frequency range are shown in FIG. 29.

Amps 1&2: Gain vs. Frequency At Different Power

4041424344454647484950

0 20 40 60 80 10Frequency (MHz)

Gai

n (d

B)

0

AMP1: 24W out, w/ fan AMP2: 24W out, w/ fanAMP1: 12.5W out, w/ fan AMP2: 12.5W out, w/ fanAMP1: 1W out, w/ fan AMP2: 1W out, w/ fan

FIG.29 Gain measurement results for the two RF amplifiers.

32

The gain figures were obtained by measuring transmission with a network analyzer through a –40 dB coupler with coupler attenuation calibrated out without the amplifier. A different calibration was done for the 25-60 MHz frequency range measurements, which means that the sudden rise in gain in this range for both amplifiers is probably due to calibration error. The measurements shown are therefore rough and do not represent exact gain values or gain flatness. They serve as a rough check of the manufacturer claims; test data provided by AR is shown in FIG. 30. Note that there is very little gain compression towards the maximum rated power. Note also that the gain changes with temperature. The data in FIG.29 is for 28°C, the equilibrium temperature in the air-cooled set-up described in the “Auxiliary Systems” section below. Note also that the data in FIG.29 is inaccurate for frequencies below 1 MHz due to very high coupler attenuation (order of –70 dB). Separate measurements were performed for the 100 kHz – 1 MHz frequency range by driving the input with an RF generator and reading the voltage prior to the 50 Ω terminator with an oscilloscope. The gain was found to be +45.4 dB at 12.3 W output for both amplifiers.

Gain vs. Frequency Data Provided By AR

40

41

42

43

44

45

46

47

48

49

50

0 10 20 30 40 50 60 70

Frequency (MHz)

Gai

n (d

B)

AMP1 25W out AMP1 12.5W out AMP2 25W out AMP2 12.5W out

FIG.30 Gain test results provided by AR for the two amplifiers.

33

II/ Auxiliary Systems 1. Thermal Protection The RF amplifier heats during operation. Overheating may cause irreversible damage. It is recommended to keep the case temperature below 60°C. Each amplifier is mounted on a heat sink and cooled by a 340 CFM fan (TRIUMF stores part # 3-1/01002). The fans run off 115 VAC. Amplifier heat-up was observed with and without the air cooling. The results are shown in FIG.31. The tests were done at maximum output power; note that it decreases with temperature. With air cooling, the equilibrium temperature is 28°C, which is much lower than the upper limit.

s an extra precaution for the case where the fans stop working, a thermal switch has

e

50°C,

25W RF Amplifier Heat-Up @ Full Power Operation

20

25

30

35

40

45

50

55

60

0 5 10 15 20 25

Time (minutes)

Tem

pera

ture

(deg

C)

Amplif ier 1 no fan Amplif ier 2 no fan Amplif ier 1 w / fan Amplif ier 2 w / fan

20.0W out

22.5W out

23.5W out

24.5W out

FIG.31 Amplifier heat-up graphs with and without fans.

Aalso been installed. The switch is clamped to the amplifier case (thermalloy comound added) with one terminal connected to the ground pin an the other to the BIAS pin. Thvoltage on the latter pin is 9 V when the switch is open, which is its normal state. At around 70°C, the switch closes and grounds the BIAS pin, disabling the RF and preventing the amplifier from burning. When the amplifier cools down to aroundthe switch opens again and RF is restored.

34

2. Gain Control

IG. 29 and 30 show that the two amplifiers do not have the same gain within the 1%

he amplifier gain can be controlled by means of a built-in PIN-diode attenuator. The

gain control circuit has been installed on each e PIN-

9.3 V

,

mit and

lo

Famplitude requirement (this corresponds to approximately 0.08 dB) at all frequencies. This leads to the need to perform gain balancing of the different channels. Tdependence of the amplifier gain on voltage at the “PIN-DIODE” pin is shown in FIG.32. The currents into the pin are shown in red at several points.

Amplifier #1 Gain vs. Voltage To PIN-DIODE

05

101520253035404550

0 5 10 15 20 25

Ave

rage

Gai

n 25

-60M

Hz

(dB

)

Aamplifier for manually changing the voltage to thDIODE attenuator. The schematic is shown in FIG. 33. Depending on the position of the toggle switch, the potentiometer allows to manually set the voltage divider either between 0 V and 2.7 V or between 1and 20.3 V. The voltage level is buffered by an LM358 Op Amp (datasheet in Appendix F); it serves to provide the required current to the PIN-diode. The gain is thus regulated between +45 dB and +32 dB or between +14dB and +13 dB. The lower gain range is needed when low-amplitude RF is used for stable nuclei. This optionhowever, is undesirable because the PIN-diode attenuator is noisy at its maximum attenuation lisensitive to a variety of factors such as temperature. A different solution for low-amplitude RF is discussed be w.

Voltage To Pin-Diode Attenuator (V)1.34m

5.65mA 13.00mA 20.48mA 28.05mA A

FIG.32 Amplifier #1 gain control with PIN-diode attenuator.

FIG.33 Gain control circuit for a single channel.

35

3. Input Attenuation The amplifiers have a very high gain, meaning that if low amplitudes are needed at the

signal-

. Power Supply

o power up the RF amplifiers, external 30V-10A power supplies from Xantrex are used

ce

s 50

electrodes, a very small signal must come from the generator. As a result, the signal-to-noise ratio at the input is low. When both the signal and the noise get amplified, a very “rough” signal results at the amplifier output, which at 10 Vpp is worse than the 1% requirement. To remedy this, a -10 dB attenuator is installed at the input of each amplifier. As a result, much higher amplitude signal can be given, then attenuatedtogether with the noise that is picked up prior to the amplifiers, thus increasing the to-noise ratio. 4 T(model HPD30-10GPIB). The +30 V rail is the requirement of the amplifiers, and it also serves the gain control circuit (see FIG.33). Although the amplifiers are specified to drawup to 7 A from the supply, they have been tested and draw below 5 A, allowing to use one supply for every two amplifiers. The one supply powering the two amplifiers in plais mounted in the bottom right corner of the Penning trap rack. The current drawn from it by both amplifiers and the gain control circuits (the latter draw almost no current) is 9.4A. Turning on this supply turns on the amplifiers, so remember to have their inputΩ terminated. Observe the turn-on procedure outlined in Appendix A.

36

TERMINATIONS / DescriptionI

ach termination is a 50 Ω resistor rated for

h

I/ Performance

E100 W and installed on a 50 W heatsink (with thermalloy compound applied). Sucpower rating gives enough room above the maximum of 25 W that will be dissipated. An SMA jack is also mounted for the cableattachment. The assembly is shown in FIG.34. I

. Matching

he match has been confirmed to be 50±2 Ω

at 42 MHz.

. Heat-Up

he resistor heat-up has been measured over time with no air cooling and 25 W m at

to

1 T across the frequency range, as determined by network analyzer measurements. Maximum reflected power is–35.5 dB 2 Tdissipated. The results are shown in FIG.35. The temperature comes to equilibriuaround 72°C. For the 11Li experiment, these termination heat sinks have been installedget air cooling from the 340 CFM fans already cooling the RF amplifiers. In this assembly, temperature does not rise above 30°C.

RF cableRF cable 50W heat sink50W heat sink 50 resistor50 resistor

FIG.34 Termination and heat sink mounting.

Termination Temperature vs. Time

0

10

20

30

40

50

60

70

80

0 5 10 15 20

Time (min)

Tem

pera

ture

(deg

C)

FIG.35 Termination heat sink heat-up.

37

DC BIASING MODULE

he DC Biasing Module has

every of a

t the RF input end, there is

a

he 140 Ω resistor in series with the RF path to the electrodes serves two purposes: ion)

he circuit with 8 channels is built on a PCB, which sits directly on the feedthrough pins,

his set-up sits inside a cylindrical shield with a lid (mechanical drawings in Appendix .

.

ll the 8 DC inputs are used; every electrode can still be biased individually. A special

IG.37 is a picture of the DC Biasing Module installed on the feedthroughs (cylindrical

DC Input<1kHz

T8 channels, one corresponding toelectrode. The schematicsingle channel is shown in FIG.36. Aa DC blocking capacitor of 33 nF. All frequencies above100 kHz pass unattenuated. At the DC input side, there isa low-pass filter due to the 1300 pF capacitance of the D-sub connector used for DCinputs. This filter passes all frequencies below 1 kHz andthese filters were chosen using PSPICE simulations (see Integration section).

ttenuates all signals above 10 kHz. The components for

Tvoltage correction at the electrodes (as is discussed in the RF Electrode Network sectand attenuation of the reflected power. The value of 140 Ω has been chosen based on post-amplifier network simulations (see Integration section). Twithout any electrical contact. Each 140 Ω resistor consists of two 70 Ω resistors in series soldered to the PCB at one end and connected to the appropriate feedthrough pin by means of set-screws at the other end. TD). There are 8 SMA jacks on the lid for RF inputs and a 9-way D-sub for the DC inputsNote that currently, only 2 of the 8 RF inputs are being used: one is connected to all the “X” channels at the input, and the other is connected to all the “Y” channels. This is the temporary configuration for the quadrupole excitation while only two amplifiers are usedSimple re-wiring will restore the full 8-channel capability of the module. SMA TEE pieces are used to sample the voltage from the cable going to the terminations. Acable has been made for the DC inputs, with a male 9-way D-sub at one end and 8 BNCplugs at the other. The detailed specs for this cable can be found in Appendix E. Fshield removed, 2 RF inputs connected to X- and Y- channel).

C14

0.1u

R5100

.

C15

33n

RF toelectrodes

RF Input>100kHz

.

R6140

.

R7 500

R3

1k

C16

1300p

FIG.36 Single channel inside the DC Biasing Module.

38

DC biasing input cable

SMA TEE piece: RF input (voltage sampling point)

Vacuum feedthrus

DC biasing PCB

RF from amplifiers To terminations

Ground wire

70 Ω resistor

DC input wire

FIG.37 DC Biasing Module installed on feedthroughs.

39

PEAK DETECTOR DIAGNOSTIC I/ Description

FIG.38 Peak detector mounted near the termination.

Peak detector circuit The peak detector circuit for each channel is installed on a PCB near the termination, with a short length of wire connecting the input of the detector right before the 50 Ω load (see FIG. 38). The output is a small differential DC level, which goes to an ADC. The green wire carries the positive peak readout and ranges between 0 V and +1.25 V. The red wire carries the negative peak readout that ranges between 0V and –1.25 V. (The currently set colour code should be switched.) The circuit is shown in FIG.39. On one branch, a diode cuts off the negative part of the wave, while positive voltages charge up the 0.01 μF capacitor through the 22 kΩ resistor. The RC time constant is long enough to hold a stable voltage level in the frequency range desired. A high-resistance voltage divider brings down the readout level to 1/11 of the voltage level across the capacitor to meet the ADC specification. The exact same thing happens on the other branch, but the negative voltage is read. The diodes used are SD101AW schottky diodes (datasheet in Appendix F). The series 5 kΩ resistors limit the current through these diodes to avoid burning them (15 mA maximum).

POS OUTPUT

D2

SD101AW

INPUT

C2

0.01u

NEG OUTPUTR7

22k

R8

100k

R10

10k

VR6

100k

R4

5k

C1

0.01u

R9

10kD1

SD101AW

R3

5k

VR5

22k

FIG.39 Peak detector circuit.

40

FIG.40 Peak detector output voltages (mV) vs. time (ms).

FIG. 40 shows a PSPICE simulation of the detector with 30 V amplitude 100 kHz RF input. The detector responds within 1 ms and stabilizes to ±600 mV levels with 20 mVpp oscillations (about 3%). As frequency goes up, the output becomes more stable and the level goes down. At 5 MHz and the same amplitude, the output levels are ±570 mV with 0.5 mVpp oscillations (about 0.1%), while at 50 MHz the output goes down to ±135 mV with completely insignificant oscillations. The peak detector output at different frequencies and different RF levels is to be calibrated. FIG. 41 shows the peak detector output for pulsed RF at 30 V amplitude and 100 kHz. The pulse width is 10 ms, which is typical for 11Li. Since ADC sampling is not timed with the pulse, the readout will give 0 V half of the time. This issue is yet to be resolved. Temporarily, large capacitors (1.01 μF) have been added to the detector in parallel with the 0.01 μF capacitors to increase the time constant. The simulated output for this slower detector version is shown in FIG. 42. The oscillations in the output level are not within the required error margin. Also, the level is much lower, requiring separate calibration.

41

FIG.41 Peak detector output voltages (mV) vs. time (ms) for pulsed RF.

FIG.42 Peak detector output voltages (mV) vs. time (ms) for pulsed RF, increased time constant.

42

II/ Calibration A calibration was performed for the detector currently installed (slow version) at 5 MHz CW. The results are shown in FIG. 43. Calibration for different frequencies and pulsed RF has not been performed because the detector is still being developed (see “Future Development” section in Conclusion).

Peak Detector Calibration

0

50

100

150

200

250

300

350

0 5 10 15 20 25 30

RF Input (Vpp)

Diff

eren

tial D

C O

uput

(mV)

0 Phase detector 180 Phase Dettector

FIG.43 Slow peak detector calibration for 5 MHz CW.

43

INTEGRATION

SIMULATIONS I/ RF Simulation FIG.44 is the schematic for the most complete PSPICE simulation of the RF system hardwired for quadrupole excitation. The AC voltage source with the 50 Ω series resistor represents the RF amplifier with its 50 Ω output impedance; it is set to give out the maximum requirement of 30 V amplitude. The next 50 Ω resistor is the termination. Note that one branch in the simulation is a perfect match, for reference. The other branch is the “post-amplifier network”, the behaviour of which is being simulated. The 5 pF immediately following is the connector capacitance. After the connector, four channels are wired to the same source (say, all the “X” electrodes). RF is coupled to each channel by the DC-blocking 33 nF capacitor. Each channel has the DC biasing circuit (the DC source itself has been excluded from the simulation). Note the 140 Ω resistor; the value was optimized to obtain the best electrode voltage correction. The second 5 pF capacitor is due to the feedthrough. The wire is simulated as a transmission line, each approximated by 10 LC sections. The total capacitance of the wire is 10 pF and the total inductance is 1 μH (slightly higher than the original estimate). Finally, the electrode contributes a 3 pF capacitor to the end of each channel.

Vacuum wire as transmission line

Electrode

50Ω RF source

REF

DC Biasing Circuit

FIG.44 PSPICE simulated schematic for the post-amplifier network.

44

Voltages are calculated at the points of interest: green is the reference (ideal match), red is the voltage seen across the 50 Ω load, blue is the voltage at the location of the DC source and pink is at the electrode. The simulation results are shown in FIG. 45, 46, 47. FIG. 45 Voltage

Vol

tage

(V)

Frequency (MHz)

FIG. 45 RF amplitude at the load (red), at the electrode (pink) and reference (green). Logarithmic frequency scale.

FIG. 46 RF amplitude at the load (red), at the electrode (yellow) and reference (green). Linear frequency scale.

Vol

tage

(V)

Frequency (MHz)

45

The resonance point corresponding to maximum attenuation at the 50 Ω load is 62 MHz. Note that the series 140 Ω resistor smoothes out the electrode voltage to give a maximum at around 78 MHz. While attenuation is observable at the load after 10 MHz, at the electrode, the response is flat up to 30 MHz. Note also that the real match is below 50 Ω due to the impedance of the electrode network, resulting in lower voltage than expected from ideal match. FIG. 47 shows that RF amplitude is attenuated to below –50 dB at the DC source, which is sufficient protection.

V

olta

ge w

rt so

urce

(dB

)

Frequency (MHz)

FIG. 47 RF amplitude at the DC source input (blue). Logarithmic frequency scale.

II. DC Biasing And Low-Frequency Simulation FIG.48 is the schematic for the PSPICE simulation of DC and low-frequency signal throughout the network coming from the DC biasing input. All the components are the same as in the RF simulation (FIG.44), except for the AC voltage source, which is now placed at the location of one of the DC biasing inputs. Simulation results are in FIG.49. The blue line is the source input (reference) and the red line is the voltage at the electrode corresponding to the DC input. There is not attenuation for DC-1 kHz, as expected; it becomes significant after 10 kHz. The green line is the voltage at another electrode, which is not being biased; the attenuation is below –40 dB. The same result holds for attenuation at the input of the other DC source (pink line) and at the RF amplifier input (orange line). These results are satisfactory.

46

FIG. 48 PSPICE simulated schematic for network driven from one DC biasing input.

FIG. 49 Amplitude (dB with respect to source) vs. Frequency (MHz) at different points in the network with input from the DC source point .

III/ Simulation Limitations

Coupling between transmission lines of the same phase and opposite phase has been omitted.

Transmission lines are only approximated by 10 LC sections, in which inductance and capacitance are only roughly estimated.

Exact electrode capacitance is not known (anywhere between 2 and 4 pF). Unwanted reactive elements within the DC Biasing Module not known. The behaviour of the 180 Splitter, the RF amplifiers and the cables has not been

simulated

47

TEST RESULTS I/ Low-Power (No RF Amplifiers) 1. Network Analyzer Measurements

reflection For these measurements, the network analyzer reflection port is connected to the X channel input of the DC Biasing Module wired for the quadrupole configuration. The termination is also connected at the input. The transmission port is connected either to the Y channel input (also with the termination), for channel coupling measurements (illustrated in FIG. 50), or to one of the DC biasing inputs, for DC source protection measurements. The results are shown in FIG. 51.

transmission DC Biasing Module

FIG. 50 Measurement set-up for reflection and channel coupling measurements.

Single Channel Drive Reflection, Transmission To Opposite Channel And DC Source Isolation vs. Frequency

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0 10 20 30 40 50 60 70 80Frequency (MHz)

Pow

er (d

B)

Reflection Transmission to opposite channel DC Source

FIG. 51 Network analyzer measurement results for single phase drive reflection and transmission to opposite channel and DC source.

48

Reflection to the source is quite flat across frequency range and stays below –10 dB, is

he maximum coupling between opposite-phase channels is –20 dB. Note that this is

aximum transmission to the DC source input is –30 dB, which is worse than the ctory

. Quadrupole Drive

or this measurement, RF signal is supplied from the generator with a frequency sweep

and DC

he 50 Ω termination) t and 70 Ω to the

- ughs

which is within the RF amplifier mismatch tolerance specification. No resonance peakobserved because the power is dissipated in the 140 Ω resistor. Tslightly better than the result without the DC Biasing Module, presented in the RF Electrode Network section. Msimulation showed due to unpredicted reactive elements in the module, but a satisfaprotection nonetheless. 2 Ffrom 0.100 to 80 MHz. The signal goes through the 180 Splitter and the X and Y channels are both driven from the splitter at opposite phase, with the terminations Biasing Module in place. Voltage is then measured by an oscilloscope with 10x attenuation on the probe at three points:

- At the point of sampling (across t- In the middle of the series resistor (70 Ω to the RF inpu

feedthroughs) At the feedthro

RF Signal vs. Frequency At Different Points In The DC Biasing Module

-0.04

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

0.04

0 20 40 60 8Frequency (MHz)

Volta

ge (V

)

0

Voltage Across Termination Voltage At 70 Ohm Point Voltage At Feedthrough

FIG. 52 RF signal observed at different points vs. frequency.

49

The absolute values of the voltages mean little; the purpose of these measurements is to

ite

r (it

I/ Full System Tests

observe relative attenuation as a function of frequency. The resonance point is seen at around 62 MHz at the feedthroughs, which is an indication that the RF simulation is quaccurate (it also predicted resonance at 62 MHz). Note that due to the series 140 Ω resistor the observed attenuation is less at the load; power is dissipated in the resistogets hot throughout the run at higher amplitudes). I

. Voltage Calibration

he following voltage calibration was done for the 11Li experiment. The system was run

nd

1 Tin its final configuration and with –10 dB attenuators at the RF amplifier inputs. RF amplitude was measured at the feedthroughs at different RF generator output levels akey frequencies used during the experiment (6Li, 7Li, 8Li, 9Li, 11Li resonant frequencies, which are 9.45, 8.10, 7.09, 6.30 and 5.15 MHz respectively). RF was supplied in CW mode and amplifier gains were balanced. The calibration results are shown in FIG.53.

RF Voltage On Feedthroughs vs. Generator Input

0

5

10

15

20

25

30

35

0 50 100 150 200 250 300 350

Generator Ampllitude (mVpp)

RF

Am

plitu

de O

n Fe

edth

roug

hs (V

pp)

5.15 MHz 6.3 MHz 7.09 MHz 8.10 MHz 9.45 MHz

FIG. 53 RF amplitude on feedthroughs vs. RF generator amplitude at key frequencies.

50

The response is nicely linear. Slight attenuation is seen towards 10 MHz, which can also be seen in the simulation. However, according to the simulation, the amplitude on the electrodes remains flat in this frequency range, so the 5 MHz calibration should be used for all frequencies. 2. Pulse Mode Response Voltage at the feedthroughs was also observed in pulse mode operation, with 10 ms pulse width. RF frequency used was 5.15 MHz. The results for two 280 mVpp input from the generator and for 50 mVpp input are shown on FIG. 54 and FIG. 55 respectively. The overshoot of the switch in the splitter module is amplified into a 20 V overshoot at the feedthrough (and the electrode) for each phase, independent of the actual RF amplitude. The RF levels stabilize within about 100 μs, which is longer than the time constant for the switch itself due to response delay of the RF amplifiers. However, the oscillations die down quickly enough with respect to the 10 ms pulse width that the effect can be neglected, especially since the envelope shape is repeatable from pulse to pulse. If RF phase can be synchronized with the pulsing phase, the RF waveform will also be repeatable from pulse to pulse, removing any concern over the switching overshoot.

51

5.15MHz 280mVpp Generator Input 10ms Pulse Width

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

-4.00E-05 1.00E-05 6.00E-05 1.10E-04 1.60E-04 2.10E-04 2.60E-04 3.10E-04 3.60E-04

Time (s)

Volta

ge (V

)0 Phase 180 Phase

FIG. 54 RF signal on the feedthroughs at switch time for pulse mode signal, 280 mVpp from generator.

5.15MHz 50mVpp Generator Input 10ms Pulse Width

-20

-15

-10

-5

0

5

10

15

20

25

-4.00E-05 1.00E-05 6.00E-05 1.10E-04 1.60E-04 2.10E-04 2.60E-04 3.10E-04 3.60E-04

Time (s)

Volta

ge (V

)

0 Phase 180 Phase

FIG. 55 RF signal on the feedthroughs at switch time for pulse mode signal, 50 mVpp from generator.

52

CONCLUSION

SYSTEM STATUS AND FIRST EXPERIMENT On August 24 through 27, 2007, TITAN conducted its first experiment. Masses of 6Li, 7Li, 8 9Li and Li isotopes were measured with high precision. These measurements will be used for calibrating the system for the 11Li measurement, which is the goal. Throughout the experiment, the RF system was successfully used to provide cyclotron quadrupole excitation for the mass measurement, as well as magnetron excitation through the DC - 1 kHz inputs of the DC Biasing Module and cyclotron dipole excitation with the DC Biasing Module temporarily removed. The latter was used for preliminary mass estimates using the depletion test. The system was found to perform to specifications. The system configuration which was used to drive the trap electrodes for the mass measurements involves one function generator, the 180 Splitter Module with a TTL signal from the PPG for pulsing, two RF amplifiers with –10 dB attenuators at inputs for driving the two phases, two terminations and the DC Biasing Module mounted on feedthroughs and hardwired for quadrupole excitation. The system is designed to expand to higher functionality to meet the complete set of requirements for future experiments; this is discussed in the next section.

FUTURE DEVELOPMENT I/ Multiple Excitation Modes Currently, the system is configured to only provide quadrupole excitation. In the future, multiple modes of excitation applied consecutively throughout a single pulse will be required. Typically, two modes of excitation will be applied: cyclotron dipole followed by cyclotron quadrupole (remember that magnetron excitation is applied throught he low-frequency channel). Two generators will therefore be required, one configured to scan around the appropriate frequency (reduced cyclotron frequency and the true cyclotron frequency, respectively). The two generators are available and the 180 Splitter Module has been built with two inputs. It is a matter of connecting the second generator and providing the 180 Splitter Module with another TTL signal from the PPG to switch between the two inputs. The 180 Splitter Module already has 4 outputs at 0° phase and 4 output at 180° phase, well isolated from each other (-10 dB). Currently, only two channels are used. All 8 channels can be used at any time. However, 8 amplifiers are needed to drive the 8 channels. This means purchasing more amplifiers from AR and installing all the auxiliary subsystems required to run them (power supply, air cooling, thermal switch, gain control, attenuators). Certainly, 8 terminations are also required, mounted on heat sinks and with individual peak detector diagnostics. The DC biasing module simply needs to have

53

jumpers removed, which connect all the “X” channels together and all the “Y” channels together. However, different excitation modes require different phase assignments to the electrodes, so a TTL-controlled RF switching matrix must be introduced on the low-power side of the RF amplifiers. Such a matrix can be purchased commercially. Due to an increased number of equipment, space issues must be considered as to the placement of the amplifiers and the terminations, as well as the power supplies and switching matrix. Some number of mechanical jobs are to be expected. Also, additional miscellaneous hardware will need to be procured such as the double-shielded calbes, SMA TEE pieces for the DC Biasing Module, etc. II/ Amplitude Modulation The overshoot due to switching can potentially cause an error in the mass measurement. One solution is to avoid using the switch within the 180 Splitter Module and introduce some form of amplitude modulation controlled by an analog signal from the DAQ. The amplitude modulation can be performed either at the low-power or the high-power side and will also avoid using the –10 dB attenuators. In fact, if amplitude modulation happens at the high-power side, an amplitude stabilization feedback loop can be introduced if ever the stability requirement becomes more stringent. Also, high-power attenuators can be put in, which have an advantage over the attenuators currently in place because they will also attenuate any noise introduced at the amplifier. IV/ Peak Detector Diagnostic The peak detector currently in place has several issues. Firstly, the output is largely frequency-dependent. Secondly, in pulse mode operation, it either reproduces the pulse shape or oscillates around a certain level, depending on capacitors installed. In the first case, ADC sampling is not synchronized to the pulse and will give erratic readout either at 0 V or at the true value expected, and occasionally somewhere in between. In the second case, the response of the detector is slow, meaning that any spikes in the RF envelope will go unnoticed. Also, due to the RC oscillations, the amplitude readout will not be precise within 1%. An alternative schematic for an active peak detector is being developed by Chris Owen. One version is shown in FIG.66. It has the following features:

Output equalization from 5 MHz to 70 MHz. A fast high bandwidth detector output for looking at RF pulse rising edge

characteristics on a scope. DC output with pulsed RF same as with CW RF.

The whole circuit and the 50 Ω load should be mounted in a metal box with filter connectors to prevent RF leakage.

54

FIG. 56 Active peak detector schematic.

V/ Resonance The reactive nature of the electrode and wire network in vacuum results in resonance in the middle of the frequency range requirement, at 62 MHz. For the 11Li experiment, this does not play a role because the frequency response is flat up to 10 MHz. However, if very light ions need to be measured in the future (hydrogen ion with cyclotron frequency 57 MHz), corrections to the system must be made. There are two possibilities. One possibility is to replace the wires with ultra-high vacuum-compatible coax cables to decrease the capacitance and mutual coupling. Another possibility is to work with the DC Biasing Module and introduce elements which will distort the frequency response as to equalize it at the desired points. This will not take out the inherent resonant effect due to the electrode and wire network, but a particular experiment can still be performed with frequencies in the 100 kHz – 70 MHz range. The DC Biasing Module in this case will have to be adapted to every particular experiment.

55

REFERENCES

1. TITAN website, http://titan.triumf.ca/ 2. Jim Al-Khalili, “An Introduction to Halo Nuclei”, Lect. Notes Phys. 651, 77-112

(2004) 3. Delheij et al., “The TITAN Mass Measurement Facility at TRIUMF-ISAC”, draft 4. Klaus Blaum, “High-accuracy mass spectrometry with stored ions”, Physics

Reports 425 (2006) 1-78 5. LEBIT website at NSCL, http://groups.nscl.msu.edu/lebit/ 6. Vladimir Ryjkov, “TITAN Penning trap DAQ / controls design”, draft 13 Oct

2005, TRIUMF 7. Iossel, Kochanov and Strunski, Calculating Electrical Capacitance, Energoiszdat,

Leningrad, 1981 8. Kalantarov, Tseitlin, Calculating Inductances, Energoatomizdat, Leningrad, 1986 9. “Resistive Power Splitters”, Microwave Encyclopedia, 24 Apr 2007,

http://www.microwaves101.com/encyclopedia/Resistive_splitters.cfm 10. “Owen Resistive Splitter”, Microwave Encyclopedia, 15 Aug 2007,

http://www.microwaves101.com/encyclopedia/Resistive_splitter2.cfm

56

APPENDICES

APPENDIX A SYSTEM TURN ON/OFF PROCEDURE

To turn the system ON: 1. Connect all the components of the system together in the desired configuration. 2. Make sure that no RF goes through to the RF Amplifier inputs (keep the “enable” switch in the 180 Splitter Module OFF). 2. Ensure that the RF Amplifier outputs are terminated in 50 Ω. If they are turned on without the outputs matched to 50 Ω, the RF Amplifiers WILL BE DAMAGED. 3. Turn ON the power supply to the RF Amplifiers. Ensure that the voltage is 30.0 V and the current drawn is around 9.4 A. If so, the RF amplifiers have been turned ON. The power supply is located at the bottom right corner of the Penning trap rack, on the platform. 4. Set up the RF generator as needed and enable the output. Remember to not exceed 280 mVpp if the generator output goes to the 180 Splitter Module. This corresponds to 0 dBm input to the RF Amplifiers, which results in the maximum of 25 W output. 5. Proceed with the run. To turn ON RF, give a positive TTL edge to the “enable” switch in the 180 Splitter Module. To turn the system OFF: 1. Turn OFF RF by giving a 0 TTL signal to the “enable” switch. 2. Turn OFF the power supply and wait for the voltage to ramp down to 0 V or until the display turns black.

APPENDIX B 180 Splitter Module Schematic And PCB Layout

Note the following changes to the schematic and the layout that must be made (they have been made in the module already):

A 0.2 μF capacitor must be added in series at the output of each Gali-55+ amplifier, after the biasing resistor junction.

All the 100 Ω and the 68 Ω resistors in the Owen splitters must be swapped. The biasing resistors must be changed from 150 Ω to 187.5 Ω (300 Ω and 500 Ω

in parallel)

C1 P0C101 P0C102

C2

P0C201 P0C202

C3 P0C301 P0C302

C4

P0C401 P0C402

C5

P0C501 P0C502

C6

P0C601 P0C602

C7 P0C701 P0C702

C8 P0C801 P0C802

C9

P0C901

P0C902

C10 P0C1001

P0C1002

C11 P0C1101

P0C1102

C12 P0C1201 P0C1202

C13 P0C1301 P0C1302

C14 P0C1401 P0C1402

C15

P0C1501 P0C1502

C16

P0C1601 P0C1602

C17 P0C1701 P0C1702

C18

P0C1801 P0C1802

C19

P0C1901 P0C1902

C20

P0C2001 P0C2002

C21

P0C2101

P0C2102

C22

P0C2201

P0C2202

C23

P0C2301

P0C2302

J1

P0J101

P0J102

J2

P0J201 P0J202

P0J203

P0J204 P0J205

J3

P0J301

P0J302

J4

P0J401 P0J402

P0J403

P0J404

P0J405

J5

P0J501

P0J502

J6

P0J601

P0J602

J7

P0J701

P0J702

J8

P0J801

P0J802

J9

P0J901

P0J902

J10

P0J1001

P0J1002

J11

P0J1101

P0J1102

J12

P0J1201

P0J1202

J13

P0J1301

P0J1302

LED1

P0LED10A

P0LED10K

LED2

P0LED20A

P0LED20K

LED3

P0LED30A

P0LED30K

LED4

P0LED40A

P0LED40K

LED5

P0LED50A

P0LED50K

LOGO

R1

P0R101 P0R102

R2

P0R201

P0R202

R3 P0R301 P0R302

R4

P0R401

P0R402

R5

P0R501 P0R502

R6

P0R601

P0R602

R7

P0R701

P0R702

R8

P0R801

P0R802

R9

P0R901

P0R902

R10

P0R1001 P0R1002

R11

P0R1101

P0R1102

R12

P0R1201

P0R1202

R13 P0R1301 P0R1302

R14

P0R1401

P0R1402

R15

P0R1501

P0R1502

R16

P0R1601

P0R1602

R17

P0R1701

P0R1702

R18 P0R1801 P0R1802

R19

P0R1901 P0R1902

R20

P0R2001

P0R2002

R21

P0R2101

P0R2102

R22

P0R2201 P0R2202

R23

P0R2301 P0R2302

R24

P0R2401

P0R2402

R25 P0R2501

P0R2502

R26

P0R2601 P0R2602

R27 P0R2701 P0R2702

R28

P0R2801 P0R2802

R29 P0R2901

P0R2902

R30

P0R3001

P0R3002

R31

P0R3101 P0R3102

R32

P0R3201 P0R3202

R33

P0R3301

P0R3302

R34 P0R3401 P0R3402

R35

P0R3501 P0R3502

R36

P0R3601

P0R3602

R37

P0R3701

P0R3702

R38

P0R3801 P0R3802

R39 P0R3901 P0R3902

R40 P0R4001 P0R4002

R41

P0R4101 P0R4102

R42

P0R4201

P0R4202

U1

P0U101 P0U102 P0U103 P0U104 P0U105 P0U106 P0U107 P0U108

P0U109 P0U1010 P0U1011 P0U1012 P0U1013 P0U1014

U2 P0U201

P0U202

P0U203

P0U204

U3 P0U301

P0U302

P0U303

P0U304

U4 P0U401 P0U402 P0U403 P0U404 P0U405

P0U406 P0U407 P0U408

U5 P0U501 P0U502 P0U503 P0U504 P0U505

P0U506 P0U507 P0U508

U6 P0U601 P0U602 P0U603 P0U604 P0U605

P0U606 P0U607 P0U608

U7 P0U701

P0U702

P0U703

P0U704

U8

P0U801

P0U802

P0U803

P0U804

U9 P0U901

P0U902

P0U903

P0U904

P0C301

P0C601

P0C1501 P0C1701

P0C2301

P0R301

P0R1101

P0R1801

P0R3901

P0U1014

P0U401 P0U501

P0U608

P0U803

P0C101

P0C401

P0C1301

P0C1901

P0C2101 P0C2201

P0J1201

P0R201

P0R2001

P0R2901

P0R3601

P0R4001

P0U801

P0J401

P0R1401 P0R1501 P0R1601 P0R1701 P0U1011

P0U404

P0C102

P0C302

P0C402

P0C602

P0C801

P0C1302

P0C1402

P0C1502

P0C1602

P0C1702

P0C1902

P0C2102 P0C2202 P0C2302

P0J102

P0J202

P0J203

P0J204 P0J205

P0J302

P0J402

P0J403

P0J404

P0J405

P0J502

P0J602

P0J702

P0J802

P0J902

P0J1002

P0J1102

P0J1202

P0J1302

P0LED40K

P0LED50K

P0R402

P0R602 P0R702 P0R802 P0R902

P0R1202

P0R1402 P0R1502 P0R1602 P0R1702

P0R2102

P0R2402

P0R2602

P0R2702

P0R3002

P0R3302

P0R3702

P0R4202

P0U101

P0U103

P0U105

P0U107

P0U202 P0U204

P0U302 P0U304

P0U402 P0U406

P0U502 P0U506

P0U605

P0U702 P0U704

P0U802

P0U804

P0U902 P0U904

P0C201 P0R502 P0C202

P0U201

P0C501 P0R2202 P0C502

P0U301

P0C701 P0J601 P0C702

P0U408

P0C802

P0U604

P0C901

P0U403

P0C902

P0U508

P0C1001

P0U503

P0C1002

P0C1101

P0R2701

P0C1102

P0R2501

P0C1201

P0J801

P0C1202

P0U405

P0C1401 P0U407 P0C1601

P0U507

P0C1801 P0R3102 P0C1802

P0U701

P0C2001 P0R3802 P0C2002

P0U901

P0J101 P0R102

P0R401

P0J301 P0R1002

P0R1201

P0J501 P0R1902

P0R2101

P0J701 P0R2302

P0R2401

P0J901 P0R2802

P0R3001

P0J1001 P0R3202

P0R3301

P0J1101

P0R3502

P0R3701

P0J1301 P0R4102

P0R4201

P0LED10A P0R302

P0LED10K

P0U1012

P0LED20A

P0R1102

P0LED20K

P0U109 P0U1010

P0LED30A P0R1802

P0LED30K

P0U108

P0LED40A

P0R4002

P0LED50A

P0R3902

P0R101

P0R202

P0R1001

P0U203

P0R501

P0R1302

P0R2201

P0R1301

P0U607

P0R1901

P0R2002

P0R2301

P0U303

P0R2502

P0U602

P0R2601 P0U505

P0R2801

P0R2902

P0R3201

P0U703

P0R3101

P0R3402

P0R3801

P0R3401

P0U606

P0R3501

P0R3602

P0R4101

P0U903

P0J201

P0R601 P0R701 P0R801 P0R901

P0U1013

P0U504

P0C301

P0C601

P0C1501 P0C1701

P0C2301

P0R301

P0R1101

P0R1801

P0R3901

P0U1014

P0U401 P0U501

P0U608

P0U803

P0C101

P0C401

P0C1301

P0C1901

P0C2101 P0C2201

P0J1201

P0R201

P0R2001

P0R2901

P0R3601

P0R4001

P0U801

P0J401

P0R1401 P0R1501 P0R1601 P0R1701 P0U1011

P0U404

Revision

Date:File:

Hubert Hui

Sheet #: of Size:

C:\Project\TITAN\Splitter Module\Splitter Module.SchDoc6/15/2007

B11

180 Degree Splitter ModuleTRIUMF4004 Wesbrook MallVancouver, B.C.CanadaV6T 2A3

0Drawing #:

1:51:54 PM

Drawn by:

J2LEMO-RA

J4LEMO-RA

84

51,3

26

7

U6AD8015AR

RF-IN1 RF-OUT 3

GN

D2

GN

D4

U2GALI 55+

GND 6

AC GND 7

VDD 1

IN/OUT 3

OUT/IN18

OUT/IN25

EN CH1 4

GND 2

U4

SA630

GND 6

AC GND 7

VDD 1

IN/OUT 3

OUT/IN18

OUT/IN25

EN CH1 4

GND 2

U5

SA630

C2

0.2uF

R5

18R

R2150R

C1

0.2uFR1

100R

R468R

GND

R10

100R

R1268R

GND

GND

+12V

GND

RF-IN1 RF-OUT 3

GN

D2

GN

D4

U3GALI 55+C5

0.2uF

R22

18R

R20150R

C4

0.2uFR19

100R

R2168R

GND

R23

100R

R2468R

GND

GND

+12V

GND

R13

18R

GND

GND

GND

GND

RF-IN1 RF-OUT 3

GN

D2

GN

D4

U7GALI 55+C18

0.2uF

R31

18R

R29150R

C13

0.2uFR28

100R

R3068R

GND

R32

100R

R3368R

GND

GND

+12V

GND

RF-IN1 RF-OUT 3

GN

D2

GN

D4

U9GALI 55+C20

0.2uF

R38

18R

R36150R

C19

0.2uFR35

100R

R3768R

GND

R41

100R

R4268R

GND

GND

+12V

GND

R34

18R

GND

GND

GND

GND

C6

0.2uF

+5V

GND

GND

C8

0.2uFGND

R25

3K3

C160.2uF

C11

0.2uF

C10

0.2uFR2750R

GND

+5V

GND

R26

50RGND

C9

0.2uF

C170.2uF

GND

C140.2uF

+5V

GND

C150.2uF

GND

C7

0.2uF

C12

0.2uF

GND

GND

DIPOLE IN

QUAD IN

R14200R

R15200R

R16200R

R17200R

GND

GEN-SEL

GND

R6200R

R7200R

R8200R

R9200R

GND

ON

THICK TRACKS ARE 50 OHM COATED MICROSTRIPS

GND

+5V

VIN1 VOUT 3

GN

D/T

AB

4

GN

D2

U8L7805A

+C2310uF

C220.1uF

+C2110uF

+12V

12

J12

CON2

J6SMA

J8SMA

J1SMA

J3SMA

J5SMA

J7SMA

J9SMA

J10SMA

J11SMA

J13SMA

LED5GREEN

R39470R

LED4GREEN

R401K2

GND

LED1

GREEN

R3

470R

+5V

LED2

GREEN

R11

470R

+5V

LED3

GREEN

R18

470R

+5VSELECT DIPOLE IN

SELECT QUAD IN

VCC 14

GND 7

ExternalPower

U1A

74LS04

1 2U1B

74LS04

3 4U1C

74LS04

5 6U1D

74LS04

9 8U1E

74LS04

11 10U1F

74LS04

13 12U1G

74LS04

C30.1uF

GND

+5V

GND

P0C101 P0C102

P0C201 P0C202

P0C301

P0C302

P0C401 P0C402

P0C501 P0C502

P0C601 P0C602

P0C701 P0C702

P0C801 P0C802

P0C901 P0C902

P0C1001 P0C1002 P0C1101 P0C1102

P0C1201 P0C1202

P0C1301 P0C1302

P0C1401

P0C1402 P0C1501

P0C1502 P0C1601

P0C1602 P0C1701

P0C1702

P0C1801 P0C1802

P0C1901 P0C1902

P0C2001 P0C2002

P0C2101

P0C2102 P0C2201

P0C2202 P0C2301

P0C2302

P0J101

P0J102

P0J201

P0J202

P0J203

P0J204

P0J205

P0J301

P0J302

P0J401

P0J402

P0J403

P0J404

P0J405

P0J501

P0J502

P0J601

P0J602

P0J701

P0J702

P0J801

P0J802

P0J901

P0J902

P0J1001

P0J1002

P0J1101

P0J1102

P0J1201

P0J1202

P0J1301

P0J1302

P0LED10A P0LED10K

P0LED20A P0LED20K

P0LED30A P0LED30K

P0LED40A

P0LED40K P0LED50A

P0LED50K

P0R101 P0R102

P0R201

P0R202

P0R301 P0R302

P0R401

P0R402

P0R501 P0R502

P0R601

P0R602

P0R701

P0R702

P0R801

P0R802

P0R901

P0R902

P0R1001 P0R1002

P0R1101 P0R1102 P0R1201

P0R1202

P0R1301 P0R1302

P0R1401

P0R1402

P0R1501

P0R1502

P0R1601

P0R1602

P0R1701

P0R1702

P0R1801 P0R1802

P0R1901 P0R1902

P0R2001

P0R2002 P0R2101

P0R2102

P0R2201 P0R2202

P0R2301 P0R2302

P0R2401

P0R2402

P0R2501 P0R2502

P0R2601 P0R2602 P0R2701

P0R2702

P0R2801 P0R2802

P0R2901

P0R2902 P0R3001

P0R3002

P0R3101 P0R3102

P0R3201 P0R3202

P0R3301

P0R3302

P0R3401 P0R3402

P0R3501 P0R3502

P0R3601

P0R3602 P0R3701

P0R3702

P0R3801 P0R3802

P0R3901

P0R3902

P0R4001

P0R4002

P0R4101 P0R4102

P0R4201

P0R4202

P0U107

P0U1014

P0U101 P0U102

P0U103 P0U104

P0U105 P0U106

P0U108 P0U109

P0U1010 P0U1011

P0U1012 P0U1013

P0U201

P0U202

P0U203

P0U204

P0U301

P0U302

P0U303

P0U304

P0U401

P0U402

P0U403

P0U404

P0U405

P0U406

P0U407

P0U408

P0U501

P0U502

P0U503

P0U504

P0U505

P0U506

P0U507

P0U508

P0U601

P0U602

P0U603

P0U604

P0U605

P0U606

P0U607

P0U608

P0U701

P0U702

P0U703

P0U704

P0U801

P0U802

P0U803

P0U804

P0U901

P0U902

P0U903

P0U904

P0C301

P0C601 P0C1501

P0C1701

P0C2301

P0R301

P0R1101

P0R1801

P0R3901

P0U1014

P0U401 P0U501

P0U608

P0U803

P0C101

P0C401

P0C1301

P0C1901

P0C2101

P0C2201

P0J1201

P0R201

P0R2001

P0R2901

P0R3601

P0R4001

P0U801

P0J401

P0R1401

P0R1501

P0R1601

P0R1701

P0U1011

P0U404

P0C102

P0C302

P0C402

P0C602

P0C801

P0C1302

P0C1402

P0C1502

P0C1602

P0C1702

P0C1902

P0C2102

P0C2202

P0C2302

P0J102

P0J202

P0J203

P0J204

P0J205

P0J302

P0J402

P0J403

P0J404

P0J405

P0J502

P0J602

P0J702

P0J802

P0J902

P0J1002

P0J1102

P0J1202

P0J1302

P0LED40K

P0LED50K

P0R402

P0R602

P0R702

P0R802

P0R902

P0R1202

P0R1402

P0R1502

P0R1602

P0R1702

P0R2102

P0R2402

P0R2602

P0R2702

P0R3002

P0R3302

P0R3702

P0R4202

P0U101

P0U103

P0U105

P0U107

P0U202

P0U204

P0U302

P0U304

P0U402

P0U406

P0U502

P0U506

P0U605

P0U702

P0U704

P0U802

P0U804

P0U902

P0U904

P0C201 P0R502 P0C202 P0U201

P0C501 P0R2202 P0C502 P0U301

P0C701 P0J601 P0C702

P0U408

P0C802 P0U604

P0C901

P0U403

P0C902 P0U508

P0C1001 P0U503

P0C1002 P0C1101

P0R2701

P0C1102 P0R2501

P0C1201 P0J801 P0C1202

P0U405

P0C1401 P0U407

P0C1601 P0U507

P0C1801 P0R3102 P0C1802 P0U701

P0C2001 P0R3802 P0C2002 P0U901

P0J101 P0R102

P0R401

P0J301 P0R1002

P0R1201

P0J501 P0R1902

P0R2101

P0J701 P0R2302

P0R2401

P0J901 P0R2802

P0R3001

P0J1001 P0R3202

P0R3301

P0J1101 P0R3502

P0R3701

P0J1301 P0R4102

P0R4201

P0LED10A P0R302 P0LED10K P0U1012

P0LED20A P0R1102 P0LED20K

P0U109

P0U1010

P0LED30A P0R1802 P0LED30K P0U108

P0LED40A

P0R4002

P0LED50A

P0R3902

P0R101

P0R202

P0R1001

P0U203 P0R501

P0R1302

P0R2201

P0R1301

P0U607

P0R1901

P0R2002

P0R2301

P0U303

P0R2502 P0U602

P0R2601 P0U505

P0R2801

P0R2902

P0R3201

P0U703 P0R3101

P0R3402

P0R3801

P0R3401

P0U606

P0R3501

P0R3602

P0R4101

P0U903

P0U102

P0U104

P0U106

P0U601 P0U603

P0J201

P0R601

P0R701

P0R801

P0R901

P0U1013

P0U504

APPENDIX C DC Biasing Module Schematic And PCB Layout

Note the following changes to the schematic and the layout that must be made (they have been made in the module already):

Two 68 Ω resistors in series must go in place of the 150 Ω resistors.

C1

P0C101 P0C102

C2

P0C201

P0C202

C3 P0C301

P0C302

C4

P0C401

P0C402

C5

P0C501

P0C502

C6

P0C601

P0C602

C7 P0C701

P0C702

C8

P0C801

P0C802

C9

P0C901

P0C902

C10

P0C1001

P0C1002

C11

P0C1101

P0C1102

C12 P0C1201

P0C1202

C13 P

0C1301

P0C1302

C14

P0C1401

P0C1402

C15 P0C1501

P0C1502

C16 P0C1601

P0C1602

PAD1

P0PAD101

PAD2

P0PAD201

PAD3

P0PAD301

PAD4

P0PAD401

PAD5

P0PAD501

PAD6

P0PAD601

PAD7

P0PAD701

PAD8

P0PAD801 PAD9

P0PAD901

PAD10

P0PAD1001

PAD11

P0PAD1101

PAD12

P0PAD1201

PAD13

P0PAD1301

PAD14

P0PAD1401

PAD15

P0PAD1501

PAD16 P0PAD1601

PAD17

P0PAD1701

PAD18

P0PAD1801

PAD19

P0PAD1901

PAD20 P0PAD2001

PAD21

P0PAD2101 PAD22

P0PAD2201

PAD23

P0PAD2301

PAD24

P0PAD2401

PAD25

P0PAD2501

R1

P0R101

P0R102

R2 P0R201

P0R202

R3

P0R301

P0R302

R4 P0R401

P0R402

R5

P0R501

P0R502

R6

P0R601

P0R602

R7

P0R701

P0R702

R8

P0R801

P0R802

R9

P0R901

P0R902

R10

P0R1001

P0R1002

R11

P0R1101

P0R1102

R12 P0R1201

P0R1202

R13

P0R1301

P0R1302

R14

P0R1401

P0R1402

R15

P0R1501

P0R1502

R16

P0R1601

P0R1602

R17

P0R1701

P0R1702

R18

P0R1801

P0R1802

R19

P0R1901

P0R1902

R20

P0R2001

P0R2002

R21

P0R2101

P0R2102

R22

P0R2201

P0R2202

R23

P0R2301

P0R2302

R24

P0R2401

P0R2402

LOGO

LOGO

Revision

Date:File:

Hubert Hui

Sheet #: of Size:

C:\Project\TITAN\Penning Trap Biasing Board\Penning Trap Biasing Board.SchDoc

6/12/2007

A11

TITAN Penning Trap Biasing BoardTRIUMF4004 Wesbrook MallVancouver, B.C.CanadaV6T 2A3

0Drawing #:

3:46:23 PM

Drawn by:

PAD1REF INPUT

PAD5

PAD9BIAS

C133nF

C50.1uF

R11K

R9

500R

R5100R

PAD25

GND

GND

GND

FEEDTHRU

150R

PAD2REF INPUT

PAD6

PAD10BIAS

C233nF

C60.1uF

R21K

R10

500R

R6100R

GND

GND

FEEDTHRU

150R

PAD3REF INPUT

PAD7

PAD11BIAS

C333nF

C70.1uF

R31K

R11

500R

R7100R

GND

GND

FEEDTHRU

150R

PAD4REF INPUT

PAD8

PAD12BIAS

C433nF

C80.1uF

R41K

R12

500R

R8100R

GND

GND

FEEDTHRU

150R

PAD13REF INPUT

PAD17

PAD21BIAS

C933nF

C130.1uF

R131K

R21

500R

R17100R

GND

GND

FEEDTHRU

150R

PAD14REF INPUT

PAD18

PAD22BIAS

C1033nF

C140.1uF

R141K

R22

500R

R18100R

GND

GND

FEEDTHRU

150R

PAD15REF INPUT

PAD19

PAD23BIAS

C1133nF

C150.1uF

R151K

R23

500R

R19100R

GND

GND

FEEDTHRU

150R

PAD16REF INPUT

PAD20

PAD24BIAS

C1233nF

C160.1uF

R161K

R24

500R

R20100R

GND

GND

FEEDTHRU

150R

P0C101 P0C102

P0C201 P0C202

P0C301 P0C302

P0C401 P0C402

P0C501 P0C502

P0C601 P0C602

P0C701 P0C702

P0C801 P0C802

P0C901 P0C902

P0C1001 P0C1002

P0C1101 P0C1102

P0C1201 P0C1202

P0C1301 P0C1302

P0C1401 P0C1402

P0C1501 P0C1502

P0C1601 P0C1602

P0PAD101

P0PAD201

P0PAD301

P0PAD401

P0PAD501

P0PAD601

P0PAD701

P0PAD801

P0PAD901

P0PAD1001

P0PAD1101

P0PAD1201

P0PAD1301

P0PAD1401

P0PAD1501

P0PAD1601

P0PAD1701

P0PAD1801

P0PAD1901

P0PAD2001

P0PAD2101

P0PAD2201

P0PAD2301

P0PAD2401

P0PAD2501

P0R101 P0R102

P0R201 P0R202

P0R301 P0R302

P0R401 P0R402

P0R501

P0R502

P0R601

P0R602

P0R701

P0R702

P0R801

P0R802

P0R901 P0R902

P0R1001 P0R1002

P0R1101 P0R1102

P0R1201 P0R1202

P0R1301 P0R1302

P0R1401 P0R1402

P0R1501 P0R1502

P0R1601 P0R1602

P0R1701

P0R1702

P0R1801

P0R1802

P0R1901

P0R1902

P0R2001

P0R2002

P0R2101 P0R2102

P0R2201 P0R2202

P0R2301 P0R2302

P0R2401 P0R2402

APPENDIX D Mechanical Drawings Of The DC Biasing Module Box

FRO

NT

VIE

W

3.2

5

3.5

0

REV

DA

TEREV

ISIO

N D

ESC

RIP

TIO

NBY

APP'D

A10/3

0/2

006

ORIG

INA

L IS

SU

EV

RJD

ITEM

REF No./DESCRIPTION

MATERIAL

QUAN

1Ø

3.5

"OD

X 3

.6", t

ub

e 0

.065" w

all

6061 A

lloy

1

TOP V

IEW

A

NO ALLOWANCE HAS BEEN MADE FOR MANUFACTURE.

DIMENSIONS QUOTED ARE FINISHED DIMENSIONS,

REM

OV

E A

LL B

URRS A

ND

SH

ARP E

DG

ES

2

dc

b

1 2 3

dc

b

a a

1 3

±

OF

FRACTIONS

TRIUMF LABORATORY OR ITS REPRESENTATIVES.

WHITHOUT EXPRESSED WRITTEN PERMISSION OF THE

REPRODUCED OR USED, IN WHOLE OR IN PART,

AND AS SUCH, SHALL NOT BE DISCLOSED, COPIED,

CONFIDENTIAL PROPERTY OF TRIUMF LABORATORY,

CONTAINED THEREIN, IS THE SOLE, EXCLUSIVE AND

THIS DRAWING, SUBJECT MATTER AND INFORMATION

SIZE

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

SHEET

PARTICLE AND NUCLEAR PHYSICS

CANADA'S NATIONAL LABORATORY FOR

THIRD-ANGLE PROJECTION

TRIUMF

4004 WESBROOK MALL

CANADA V6T-2A3

VANCOUVER, BRITISH COLUMBIA

REV

DWG NO.

µ inch

± ±±.XX

.XXX

DECIMALS

SURFACE FINISH

ANGULAR

DESIGNEDALL DIMS IN INCHES

TOLERANCES UNLESS OTHERWISE SPECIFIED

DATE

SCALE

CHECKED

REA #

TRI-DN-

DRAWN

NEXT ASSY:

GS

IEX0400

1250.005

0.5°

0.01

VR

A

Cover

TITAN Penning Trap

Multipin Feedthru Breakout

1:2

October 30, 2006

VR

IEX0399

11

621

B BBB

ISO

METR

IC V

IEW

SC

ALE

1:1

DETA

IL A

SC

ALE

4 : 1

0.1

3 T

HRU

1.5

5

3X

R

0.0

65

0.3

8

REV

DA

TEREV

ISIO

N D

ESC

RIP

TIO

NBY

APP'D

A10/3

0/2

006

ORIG

INA

L IS

SU

EV

RJD

ITEM

REF No./DESCRIPTION

MATERIAL

QUAN

1Ø

0.3

75" X 3

"6061 A

lloy

1

NO ALLOWANCE HAS BEEN MADE FOR MANUFACTURE.

DIMENSIONS QUOTED ARE FINISHED DIMENSIONS,

REM

OV

E A

LL B

URRS A

ND

SH

ARP E

DG

ES

2

dc

b

1 2 3

dc

b

a a

1 3

±

OF

FRACTIONS

TRIUMF LABORATORY OR ITS REPRESENTATIVES.

WHITHOUT EXPRESSED WRITTEN PERMISSION OF THE

REPRODUCED OR USED, IN WHOLE OR IN PART,

AND AS SUCH, SHALL NOT BE DISCLOSED, COPIED,

CONFIDENTIAL PROPERTY OF TRIUMF LABORATORY,

CONTAINED THEREIN, IS THE SOLE, EXCLUSIVE AND

THIS DRAWING, SUBJECT MATTER AND INFORMATION

SIZE

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

SHEET

PARTICLE AND NUCLEAR PHYSICS

CANADA'S NATIONAL LABORATORY FOR

THIRD-ANGLE PROJECTION

TRIUMF

4004 WESBROOK MALL

CANADA V6T-2A3

VANCOUVER, BRITISH COLUMBIA

REV

DWG NO.

µ inch

± ±±.XX

.XXX

DECIMALS

SURFACE FINISH

ANGULAR

DESIGNEDALL DIMS IN INCHES

TOLERANCES UNLESS OTHERWISE SPECIFIED

DATE

SCALE

CHECKED

REA #

TRI-DN-

DRAWN

NEXT ASSY:

1/16

GS

IEX0400

1250.005

0.5°

0.01

VR

A

Standoff Rod

TITAN Penning Trap

Multipin Feedthru Breakout

1:1

October 30, 2006

VR

IEX0397

11

621

B BBB

FRO

NT

VIE

W

3.0

0

A A

ISO

METR

IC V

IEW

SEC

TIO

N A

-A

SC

ALE

2 : 1

2X

0.0

90.3

75

4-4

0 IN

TERN

AL

THREA

D

0.2

5

ISOMETRIC VIEW

NO ALLOWANCE HAS BEEN MADE FOR MANUFACTURE.

DIMENSIONS QUOTED ARE FINISHED DIMENSIONS,

REMOVE ALL BURRS AND SHARP EDGES

±

OF

FRACTIONS

TRIUMF LABORATORY OR ITS REPRESENTATIVES.

WHITHOUT EXPRESSED WRITTEN PERMISSION OF THE

REPRODUCED OR USED, IN WHOLE OR IN PART,

AND AS SUCH, SHALL NOT BE DISCLOSED, COPIED,

CONFIDENTIAL PROPERTY OF TRIUMF LABORATORY,

CONTAINED THEREIN, IS THE SOLE, EXCLUSIVE AND

THIS DRAWING, SUBJECT MATTER AND INFORMATION

SIZE

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

CONTAINS PROPRIETARY INFORMATION

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

DO NOT COPY, THIS DOCUMENT

SHEET

PARTICLE AND NUCLEAR PHYSICS

CANADA'S NATIONAL LABORATORY FOR

THIRD-ANGLE PROJECTION

TRIUMF

4004 WESBROOK MALL

CANADA V6T-2A3

VANCOUVER, BRITISH COLUMBIA

REV

DWG NO.

µ inch

± ±±.XX

.XXX

DECIMALS

SURFACE FINISH

ANGULAR

DESIGNEDALL DIMS IN INCHES

TOLERANCES UNLESS OTHERWISE SPECIFIED

DATE

SCALE

CHECKED

REA #

TRI-DN-

DRAWN

NEXT ASSY:

1/16

GS

IEX0400

1250.005

0.5°

0.01

VR

A

Base Plate

TITAN Penning Trap

Multipin Feedthru Breakout

1:1

October 30, 2006

VR

IEX0398

11

621

B BBB

2

dc

b

1 2 3

dc

b

a a

1 3

TOP VIEW

0.125

REV

DATE

REVISION DESCRIPTION

BY

APP'D

A10/30/2006

ORIGINAL ISSUE

VR

JD

ITEM

REF No./DESCRIPTION

MATERIAL

QUAN

1Ø3.4" X 0.125"

S.S. 316

1

FRONT VIEW

1.89

2.312

.09 THRU

3.35

INTERNAL THREAD 4-40 UNC - 2B

3X

2.975

mounting holes

to match standard CF2.75" flange

equally spaced

6X 0.266 THRU

APPENDIX E DC Biasing Cable Specifications

CABLE: 9 twisted pairs, individually shielded, stranded annealed, AWG 22 TRIUMF STORES PART #: 3-5/02017 TYPE #: 8774 LENGTH: 210” ASSEMBLY: 1 conductor from each of 8 pairs soldered to the center conductor of a BNC male connector (8x) on one end and to a pin of a male 9-way D-type (part #: 241A27120X, housing part #: 165X02609XE from CONEC) on the other end. The second conductor from each pair goes to the respective BNC ground on one end and to the 9th pin (GND) of the 9-way D-type on the other end. Leave all shields floating. One twisted pair is left unused. PINOUT: D-SUB PIN # ELECTRODE

1 X2+ 2 Y2- 3 Y2+ 4 X1+ 5 X2- 6 Y1- 7 Y1+ 8 X1- 9 GND

APPENDIX F Datasheets

1. 2.

FUNCTIONAL BLOCK DIAGRAM

10kΩ

5

6

7

8

4

3

2

1AD8015

50Ω+1

NC

IIN

NC

VBYP –VS

–OUTPUT

+OUTPUT

+VS

G = 3G = 30

NC = NO CONNECT

50Ω+1

– + +VS

1.7V

25.0E+3

20.0E+3

000.E+010.0E+6 100.0E+6 1.0E+9

15.0E+3

10.0E+3

5.0E+3

FREQUENCY – Hz

X-R

ES

IST

AN

CE

– Ω

DIFFERENTIAL

SINGLE-ENDED

Figure 1. Differential/Single-Ended Transimpedance vs.Frequency

5.0

4.5

4.0

3.5

3.0

2.5

2.0100.0E+620.0E+6000.0E+0 80.0E+660.0E+640.0E+6

FREQUENCY – Hz

EQ

UIV

AL

EN

T IN

PU

T C

UR

RE

NT

NO

ISE

– p

A√ H

z

3.0pF

2.0pF

1.5pF

1.0pF0.5pF

Figure 2. Noise vs. Frequency (SO-8 Package withAdded Capacitance)REV. A

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

a Wideband/Differential OutputTransimpedance Amplifier

AD8015FEATURES

Low Cost, Wide Bandwidth, Low Noise

Bandwidth: 240 MHz

Pulse Width Modulation: 500 ps

Rise Time/Fall Time: 1.5 ns

Input Current Noise: 3.0 pA/√Hz @ 100 MHz

Total Input RMS Noise: 26.5 nA to 100 MHz

Wide Dynamic Range

Optical Sensitivity: –36 dBm @ 155.52 Mbps

Peak Input Current: 6350 mA

Differential Outputs

Low Power: 5 V @ 25 mA

Wide Operating Temperature Range: –408C to +858C

APPLICATIONS

Fiber Optic Receivers: SONET/SDH, FDDI, Fibre Channel

Stable Operation with High Capacitance Detectors

Low Noise Preamplifiers

Single-Ended to Differential Conversion

I-to-V Converters

PRODUCT DESCRIPTIONThe AD8015 is a wide bandwidth, single supply transimpedanceamplifier optimized for use in a fiber optic receiver circuit. It is acomplete, single chip solution for converting photodiode currentinto a differential voltage output. The 240 MHz bandwidth enablesAD8015 application in FDDI receivers and SONET/SDHreceivers with data rates up to 155 Mbps. This high bandwidthsupports data rates beyond 300 Mbps. The differential outputsdrive ECL directly, or can drive a comparator/ fiber optic postamplifier.

In addition to fiber optic applications, this low cost, silicon al-ternative to GaAs-based transimpedance amplifiers is ideal forsystems requiring a wide dynamic range preamplifier or single-ended to differential conversion. The IC can be used with astandard ECL power supply (–5.2 V) or a PECL (+5 V) powersupply; the common mode at the output is ECL compatible.The AD8015 is available in die form, or in an 8-pin SOICpackage.

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, 02062-9106, U.S.A.

Tel: 617/329-4700 Fax: 617/326-8703

AD8015–SPECIFICATIONS

REV. A–2–

(SO Package @ TA = +258C and VS = +5 V, unless otherwise noted)

AD8015ARParameter Conditions Min Typ Max Units

DYNAMIC PERFORMANCEBandwidth 3 dB 180 240 MHzPulse Width Modulation 10 µA to 200 µA Peak 500 psRise and Fall Time 10% to 90% 1.5 nsSettling Time1 to 3%, 0.5 V Diff Output Step 3 ns

INPUTLinear Input Current Range ±2.5%, Nonlinearity ±25 ±30 µAMax Input Current Range Saturation ±200 ±350 µAOptical Sensitivity 155 Mbps, Avg Power –36 dBmInput Stray Capacitance Die, by Design 0.2 pF

SOIC, by Design 0.4 pFInput Bias Voltage +VS to IIN and VBYP 1.6 1.8 2.0 V

NOISE Die, Single Ended at POUT,or Differential (POUT–NOUT),CSTRAY = 0.3 pF

Input Current Noise f = 100 MHz 3.0 pA/√HzTotal Input RMS Noise DC to 100 MHz 26.5 nA

TRANSFER CHARACTERISTICSTransresistance Single Ended 8 10 12 kΩ

Differential 16 20 24 kΩPower Supply Single Ended 37.0 dBRejection Ratio Differential 40 dB

OUTPUTDifferential Offset 6 20 mVOutput Common-Mode Voltage From Positive Supply –1.5 –1.3 –1.1 VVoltage Swing (Differential) Positive Input Current, RL = ∞ 1.0 V p-p

Positive Input Current, RL = 50 Ω 600 mV p-pOutput Impedance 40 50 60 Ω

POWER SUPPLY TMIN to TMAXOperating Range Single Supply +4.5 +5 +11 V

Dual Supply ±2.25 ±5.5 VCurrent 25 26 mA

NOTES1Settling Time is defined as the time elapsed from the application of a perfect step input to the time when the output has entered and remained within a specified errorband symmetrical about the final value. This parameter includes propagation delay, slew time, overload recovery, and linear settling times.Specifications subject to change without notice.

WARNING!

ESD SENSITIVE DEVICE

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD8015 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS1

Supply Voltage (+VS to –VS). . . . . . . . . . . . . . . . . . . . . . . 12 VInternal Power Dissipation2

Small Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 WattsOutput Short Circuit Duration . . . . . . . . . . . . . . . Indefinite

Maximum Input Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mAStorage Temperature Range . . . . . . . . . . . . –65°C to +125°COperating Temperature Range (TMIN to TMAX)

AD8015ACHIP/AR . . . . . . . . . . . . . . . . . . –40°C to +85°CMaximum Junction Temperature . . . . . . . . . . . . . . . . . +165°CLead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

NOTES1Stresses above those listed under “Absolute Maximum Ratings” may causepermanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions above those indicated in theoperational section of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.

2Specification is for device in free air: 8-pin SOIC package: θJA = 155°C/W.

ORDERING GUIDE

Temperature Package PackageModel Range Description Option

AD8015AR –40°C to +85°C 8-Pin Plastic SOIC SO-8AD8015ACHIPS –40°C to +85°C Die Form

AD8015

REV. A –3–

.

V1

+VS

CLOCKRECOVERYLPF:

3dB@0.7 x F

LPF:3dB@0.7 x F

QUANTIZER

R > 40ΩC1 >100pF4.5V < VS < 11V

CLK DATA

RR

C1

10kΩ

5

6

7

8

4

3

2

1AD8015

50Ω+1

G = 3G = 30

50Ω+1

– + +VS

1.7V

1.7V

+VS

Figure 3. Fiber Optic Receiver Application: PhotodiodeReferred to Positive Supply

PHOTODIODE REFERRED TO NEGATIVE SUPPLYFigure 4 shows the AD8015 used in a circuit where the photo-diode is referred to the negative supply. This results in a largerback bias voltage than when referring the photodiode to thepositive supply. The larger back bias voltage on the photodiodedecreases the photodiode’s capacitance thereby increasing itsbandwidth. The R2, C2 network shown in Figure 4 is added todecouple the photodiode to the positive supply. This improvesPSRR.

+VS

1.7V

+VS

R2

C2

R > 40ΩC1 >100pF4.5V < VS < 11VR2 AND C2 OPTIONALFOR IMPROVED PSRR

V1

+VS

CLOCKRECOVERYLPF:

3dB@0.7 x F

LPF:3dB@0.7 x F

QUANTIZER

CLK DATA

RR

C1

10kΩ

5

6

7

8

4

3

2

1AD8015

50Ω+1

G = 3G = 30

50Ω+1

– + +VS

1.7V

Figure 4. Fiber Optic Receiver Application: PhotodiodeReferred to Negative Supply

FIBER OPTIC SYSTEM NOISE PERFORMANCEThe AD8015 maintains 26.5 nA referred to input (RTI) to 100MHz. Calculations below translate this specification into mini-mum power level and bit error rate specifications for SONETand FDDI systems. The dominant sources of noise are: 10 kΩfeedback resistor current noise, input bipolar transistor basecurrent noise, and input voltage noise.

The AD8015 has dielectrically isolated devices and bond padsthat minimize stray capacitance at the IIN pin. Input voltagenoise is negligible at lower frequencies, but can become thedominant noise source at high frequencies due to IIN pin straycapacitance. Minimizing the stray capacitance at the IIN pin iscritical to maintaining low noise levels at high frequencies. Thepins surrounding the IIN pin (Pins 1 and 3) have no internalconnection and should be left unconnected in an application.This minimizes IIN pin package capacitance. It is best to have noground plane or metal runs near Pins 1, 2, and 3 and to mini-mize capacitance at the IIN pin.

The AD8015AR (8-pin SOIC) IIN pin total stray capacitance is0.4 pF without the photodiode. Photodiodes used for SONETor FDDI systems typically add 0.3 pF, resulting in roughly0.7 pF total stray capacitance.

PIN CONFIGURATION

10kΩ

5

6

7

8

4

3

2

1AD8015

50Ω+1

NC

IIN

NC

VBYP –VS

–OUTPUT

+OUTPUT

+VS

G = 3G = 30

NC = NO CONNECT

50Ω+1

– + +VS

1.7V

METALIZATION PHOTOGRAPHDimensions shown in microns. Not to scale.

FIBER OPTIC RECEIVER APPLICATIONSIn a fiber optic receiver, the photodiode can be placed from theIIN pin to either the positive or negative supply. The AD8015converts the current from the photodiode to a differential volt-age in these applications. The voltage at the VBYP pin is ≈1.8 Vbelow the positive supply. This node must be bypassed with acapacitor (C1 in Figures 3 and 4 below) to the signal ground. Iflarge levels of power supply noise exist, then connecting C1 to+VS is recommended for improved noise immunity. For opti-mum performance, choose C1 such that C1 > 1/(2 π × 1000 ×fMIN); where fMIN is the minimum usefulfrequency in Hz.

PHOTODIODE REFERRED TO POSITIVE SUPPLYFigure 3 shows the AD8015 used in a circuit where the photo-diode is referred to the positive supply. The back bias voltage onthe photodiode is ≈1.8 V. This method of referring the photo-diode provides greater power supply noise immunity (PSRR)than referring the photodiode to the negative supply. The signalpath is referred to the positive rail, and the photodiode capaci-tance is not modulated by high frequency noise that may existon the negative rail.

OPTIONAL+VS CONNECTION

+OUTPUT

–OUTPUT

IIN

VBYP

973µ

998µ

+VS

838µ

–VS813µ

NOTE:FOR BEST PERFORMANCE ATTACH PACKAGESUBSTRATE TO +VS.MATERIAL AT BACK OF DIE IS SILICON. USE OF+VS OR –VS FOR DIE ATTACH IS ACCEPTABLE.

REV. A–4–

AD8015

SONET OC-3 SENSITIVITY ANALYSISOC-3 Minimum Bandwidth = 0.7 × 155 MHz ≈ 110 MHz

Total Current Noise = (π/2) × 26.5 nA

= 42 nA (assuming single pole response)

To maintain a BER < 1 × 10–10 (1 error per 10 billion bits):

Minimum current level needs to be > 13 × Total Current Noise= 541 nA (peak)

Assume a typical photodiode current/power conversion ratio = 0.85 A/W

Sensitivity (minimum power level) = 541/0.85 nW

= 637 nW (peak)

= –32.0 dBm (peak)

= –35.0 dBm (average)

The SONET OC-3 specification allows for a minimum powerlevel of –31 dBm peak, or –34 dBm average. Using the AD8015provides 1 dB margin.

FDDI SENSITIVITY ANALYSISFDDI Minimum Bandwidth = 0.7 × 125 MHz ≈ 88 MHz

Total Current Noise = (π / 2) ×88 MHz

100 MHz× 26.5 nA

= 39 nA (assuming single pole response)

To maintain a BER < 2.5 × 10–10 (1 error per 4 billion bits):

Minimum current level needs to be > 12.6 × Total Current Noise= 492 nA (peak)

Assume a typical photodiode current/power conversion ratio= 0.85 A/W

Sensitivity (minimum power level) = 492/0.85 nW

= 579 nW (peak)

= –32.4 dBm (peak)

= –35.4 dBm (average)

The FDDI specification allows for a minimum power level of–28 dBm peak, or –31 dBm average. Using the AD8015 pro-vides 4.4 dB margin.

THEORY OF OPERATIONThe simplified schematic is shown in Figure 5. Q1 and Q3 makeup the input stage, with Q3 running at 300 µA and Q1 runningat 2.7 mA. Q3 runs essentially as a grounded emitter. A largecapacitor (0.01 µF) placed from VBYP to the positive supplyshorts out the noise of R17, R21, and Q16. The first stage of theamplifier (Q3, R2, Q4, and C1) functions as an integrator, inte-grating current into the IIN pin. The integrator drives a differen-tial stage (Q5, Q6, R5, R3, and R4) with gains of +3 and –3.The differential stage then drives emitter followers (Q41, Q42,Q60 and Q61). The positive output of the differential stage pro-vides the feedback by driving RFB. The differential outputs arebuffered using Q7 and Q8.

The bandwidth of the AD8015 is set to within +20% of thenominal value, 240 MHz, by factory trimming R5 to 60 Ω. Thefollowing formula describes the AD8015 bandwidth:

Bandwidth = 1/(2 π × C1 × RFB × (R5 + 2 re)/R4)

where re (of Q5 and Q6) = 9 Ω each, constant over temperature,and RFB/R4 = 43.5, constant over temperature.

The bandwidth equation simplifies, and the bandwidth dependsonly on the value of C1:

Bandwidth = 1/(2 π × 3393 × C1).

Q3

INPUTCLAMPS

Q1 IIN

Q16

R17635

R1300

R211.8k

VBYP

R23k

+VS

I100.75MA

C1 0.2pF

Q4

Q5

Q56

I11.5MA

I23MA

R5 60

R3230

Q41

RFB

Q6

R4230

Q7

+VS

Q42

Q8

330

330

–VS

+OUTPUTR44 50

R43 50

I31MA

I43MA

I53MA

I61MA

I71MA

I81MA

I91MA

10k

Q61

Q60

–OUTPUT

Figure 5. AD8015 Simplified Schematiic

AD8015

REV. A –5–

1.5

–1.5100

0

–1.0

–80

–0.5

–100

1.0

0.5

8040200 60–20–40–60

INPUT CURRENT – µA

OU

TP

UT

VO

LT

AG

E –

Vo

lts – 40°C

+ 25°C

+85°C

Figure 6. Differential Output vs. Input Current

0

–2.5100

–1.0

–2.0

–80

–1.5

–100

–0.5

806040200–20–40–60

INPUT CURRENT – µA

OU

TP

UT

VO

LT

AG

E –

Vo

lts PIN 7

PIN 6

+85°C+25°C

–40°C

+85°C+25°C

–40°C

Figure 7. Single-Ended Output vs. Input Current

300

20080

230

210

–30

220

–40

260

240

250

270

280

290

706050403020100–10–20

TEMPERATURE – °C

BA

ND

WID

TH

– M

Hz

Figure 8. Bandwidth vs. Temperature

9

1 10 100 1000

5

0

4k

AD8015

VOUT

IN

GA

IN –

dB

FREQUENCY – MHz

+85°C

–40°C AND 0°C

50Ω

Figure 9. Gain vs. Frequency

10

0

10 100 1000

5V, +25°C

FREQUENCY – MHz

GR

OU

P D

EL

AY

– n

s

Figure 10. Group Delay vs. Frequency

9.0

7.0

5.010.0E+6 100.0E+6 1.0E+9

6.5

6.0

5.5

7.5

8.0

8.5

FREQUENCY – Hz

GA

IN –

dB

11.0V

5.0V4.5V

Figure 11. Differential Gain vs. Supply

REV. A–6–

AD8015100

50

1 10 100 1000

FREQUENCY – MHz

0

5V, +25°C

PIN 7

PIN 6

IMP

ED

AN

CE

– Ω

Figure 12. Output Impedance vs. Frequency

100

–100200

0

10

TIME – ns

VO

LT

AG

E –

mV

Figure 13. Small Signal Pulse Response

2

0

–1210.0E+6 100.0E+6 1.0E+9

–2

–4

–6

–8

–10

0pF

1pF

3pF

5pF

8pF

FREQUENCY – Hz

GA

IN –

dB

Figure 14. Differential Gain vs. Input Capacitance

APPLICATION155 Mbps Fiber Optic ReceiverThe AD8015 and AD807 can be used together for a complete155 Mbps Fiber Optic Receiver (Transimpedance Amplifier,Post Amplifier with Signal Detect Output, and Clock Recoveryand Data Retiming) as shown in Figure 16.

The PIN diode front end is connected to a single mode, 1300 nmlaser source. The PIN diode has 3.3 V reverse bias, 0.8 A/Wresponsivity, 0.7 pF capacitance, and 2.5 GHz bandwidth.

The AD8015 outputs (POUT and NOUT) drive a differential, con-stant impedance (50 Ω) low-pass π filter with a 3 dB cutoff of100 MHz. The outputs of the low-pass filter are ac coupled tothe AD807 inputs (PIN and NIN). The AD807 PLL dampingfactor is set at 10 using a 0.22 µF capacitor.

The entire circuit was enclosed in a shielded box. Table I sum-marizes results of tests performed using a 223–1 PRN sequence,and varying the average power at the PIN diode.

The circuit acquires and maintains lock with an average inputpower as low as –39.25 dBm.

80

0

20

10

200.

000E

+6

40

30

50

60

70

80

0

20

10

40

30

50

60

70

90

100

205.

000E

+6

215.

000E

+622

0.00

0E+6

225.

000E

+623

0.00

0E+6

235.

000E

+624

0.00

0E+6

245.

000E

+625

0.00

0E+6

255.

000E

+626

0.00

0E+6

265.

000E

+627

0.00

0E+6

275.

000E

+628

0.00

0E+6

285.

000E

+629

0.00

0E+6

295.

000E

+630

0.00

0E+6

210.

000E

+6

30 DEVICES, 2 LOTS:(+OUT, –OUT) × (25°C, –40°C, 85°C) × (5V, 4.5V, 11.0V)

FREQUENCY – Hz

PO

PU

LA

TIO

N –

Par

ts

CU

MU

LA

TIV

E –

%Figure 15. Bandwidth Distribution Matrix

AD8015

REV. A –7–

NC = NO CONNECT

1

2

3

4

8

7

6

5

1

2

5

6

7

3

4

8

16

15

12

11

10

14

13

9

VEE

SDOUT

AVCC

PIN

NIN

AVCC

THRADJ

AVEEAD807

NC

IIN

NC

VBYP

+VS

+OUT

–VS

–OUT

R10154

R11154

R6 100

C7

R5 100R1

100R2

100

C10.1µF

C20.1µF

C30.1µF

DATAOUTN

DATAOUTP

CLKOUTN

CLKOUTP

C40.1µF

C60.1µF

R4100

R8 100

R7 100

R3100

C8

R12154

TP1

TP2DAMPING

CAP,0.22µF

R11154

C50.1µF

CD

TP8 TP7SDOUT

C1100pF

C11

TP6

TP5

100pF

R13THRADJ

C910µF

C10

GNDTP4

R1450

R1550

R16301

R173.65k

C130.1µF

5VTP3

AD8015

C150.1µF

15pF

10µF

0.1µF

15pF

0.1µF 0.01µF

ABB HAFO1A227

FC HOUSING

0.8 A/W, 0.7pF2.5GHz

NOTES1. ALL CAPS ARE CHIP, 15pF ARE MICA.2. 150 nH ARE SMT

C140.1µF

50ΩLINE

50ΩLINE

C122.2µF

150nH

150nH

DATAOUTN

DATAOUTP

VCC2

CLKOUTN

CLKOUTP

VCC1

CF1

CF2

Figure 16. 155 Mbps Fiber Optic Receiver Schematic

Table I. AD8015, AD807 Fiber Optic Receiver Circuit:Output Bit Error Rate & Output Jitter vs. Average Input Power

Average Optical Output Bit Output JitterInput Power (dBm) Error Rate (ps rms)

–6.4 Loses Lock–6.45 1.2 × 10–2

–6.50 7.5 × 10–3

–6.60 9.4 × 10–4

–6.70 1 × 10–14

–7.0 to 1 × 10–14 < 40–35.50–36.00 3.0 × 10–12 < 40

–36.50 4.8 × 10–10

–37.00 2.8 × 10–8

–37.50 8.2 × 10–7

–38.00 1.3 × 10–5

–38.50 1.1 × 10–4

–39.00 1.0 × 10–3

–39.1 1.3 × 10–3

–39.20 1.9 × 10–3

–39.25 2.2 × 10–3

–39.30 Loses Lock

REV. A–8–

AD8015

PR

INT

ED

IN U

.S.A

.C

1973

–6–1

/96

AC COUPLED PHOTODIODE APPLICATION FORIMPROVED DYNAMIC RANGEAC coupling the photodiode current input to the AD8015 (Fig-ure 17) extends fiber optic receiver overload by 3 dB while sacri-ficing only 1 dB of sensitivity (increasing receiver dynamic rangeby 2 dB). This application results in typical overload of –4 dBm,

and typical sensitivity of –35 dBm. AC coupling the input alsoresults in improved pulse width modulation performance.

Careful attention to minimize parasitic capacitance at theAD8015 input (from the photodetector input), RAC and CAC arecritical for sensitivity performance in this application. Note thatCAC of 0.01 µF was chosen for a low frequency cutoff equal to2.2 kHz.

OUTLINE DIMENSIONSDimensions shown in inches and (mm).

8-Lead Small Outline IC Package (SO-8)

0.1968 (5.00)

0.1890 (4.80)

8 5

41

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0688 (1.75)

0.0532 (1.35)

SEATINGPLANE

0.0098 (0.25)

0.0040 (0.10)

0.020 (0.51)

0.013 (0.33)0.0500(1.27)BSC

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°0°

0.0196 (0.50)

0.0099 (0.25)x 45°

0.2440 (6.20)

0.2284 (5.80)

V1

+VS

CLOCKRECOVERYLPF:

3dB@0.7 x F

LPF:3dB@0.7 x F

QUANTIZER

R > 40ΩC1 >100pF4.5V < VS < 11V

CLK

DATA

RR

C1

10kΩ

5

6

7

8

4

3

2

1AD8015

50Ω+1

G = 3G = 30

50Ω+1

– + +VS

1.7V

+VS

CAC

0.01µFRAC7k

Figure 17. AC Coupled Photodiode Application for Improved Dynamic Range

Surface Mount

Monolithic Amplifier

Page 1 of 4

ISO 9001 ISO 14001 CERTIFIEDMini-Circuits®

P.O. Box 350166, Brooklyn, New York 11235-0003 (718) 934-4500 Fax (718) 332-4661 For detailed performance specs & shopping online see Mini-Circuits web site

The Design Engineers Search Engine Provides ACTUAL Data Instantly From MINI-CIRCUITS At: www.minicircuits.com

RF/IF MICROWAVE COMPONENTS

minicircuits.comALL NEW

simplified schematic and pin description

Function Pin Number Description

RF IN 1 RF input pin. This pin requires the use of an external DC blocking capacitor chosen for the frequency of operation.

RF-OUT and DC-IN 3

RF output and bias pin. DC voltage is present on this pin; therefore a DC blocking capacitor is necessary for proper operation. An RF choke is needed to feed DC bias without loss of RF signal due to the bias connection, as shown in “Recommended Application Circuit”.

GND 2,4 Connections to ground. Use via holes as shown in “Suggested Layout for PCB Design” to reduce ground path inductance for best performance.

General DescriptionGali 55+ (RoHS compliant) is a wideband amplifier offering high dynamic range. Lead finish is SnAgNi. It has repeatable performance from lot to lot, and is enclosed in a SOT-89 package. It uses patented Tran-sient Protected Darlington configuration and is fabricated using InGaP HBT technology. Expected MTBF is 8,500 years at 85°C case temperature. Gali 55+ is designed to be rugged for ESD and supply switch-on transients.

GROUND

RF IN

RF-OUT and DC-IN

REV. Q M108520D60129EE-7974QGALI-55+RS/YB/FL070119

DC-4 GHz

CASE STYLE: DF782PRICE: $1.29 ea. QTY. (25)

Gali 55+

+ RoHS compliant in accordance with EU Directive (2002/95/EC)

The +Suffix has been added in order to identify RoHS Compliance. See our web site for RoHS Compliance methodologies and qualifications.

3 RF-OUT & DC-IN

2 GROUND

1 RF-IN

4

Features• InGaP HBT microwave amplifier• Miniature SOT-89 package• Frequency range, DC to 4 GHz• Output power, 15.0 dBm typ.• Excellent package for heat dissipation, exposed metal bottom• Low thermal resistance for high reliability• Aqueous washable• Protected by US Patent 6,943,629

Applications• Cellular• PCS• Communication receivers & transmitters

Monolithic InGaP HBT MMIC Amplifier

ISO 9001 ISO 14001 CERTIFIEDMini-Circuits®

P.O. Box 350166, Brooklyn, New York 11235-0003 (718) 934-4500 Fax (718) 332-4661 For detailed performance specs & shopping online see Mini-Circuits web site

The Design Engineers Search Engine Provides ACTUAL Data Instantly From MINI-CIRCUITS At: www.minicircuits.com

RF/IF MICROWAVE COMPONENTS

minicircuits.comALL NEW

Page 2 of 4

Electrical Specifications at 25°C and 50mA, unless notedParameter Min. Typ. Max. Units

Frequency Range* DC 4 GHz

Gain f=0.1 GHz 21.9 GHz

f=1 GHz 20.6

f=2 GHz 17 18.5

f=3 GHz 17.0

f=4 GHz 15.5

f=6 GHz 15.7

Input Return Loss f= DC to 3 GHz 19 dB

f= 3 to 4 GHz 16.5

Output Return Loss f= DC to 3 GHz 17.5 dB

f= 3 to 4 GHz 14

Output Power @ 1 dB compression f=1 GHz 13.5 15.0 dBm

Output IP3 f=1 GHz 28.5 dBm

Noise Figure f=1 GHz 3.3 dB

Recommended Device Operating Current 50 mA

Device Operating Voltage 3.8 4.3 4.8 V

Thermal Resistance, junction-to-case1 100 °C/W

Note: Permanent damage may occur if any of these limits are exceeded. These ratings are not intended for continuous normal operation.1Case is defined as ground leads.*Based on typical case temperature rise 3°C above ambient.

Absolute Maximum Ratings

Gali 55+

Parameter Ratings

Operating Temperature* -45°C to 85°C

Storage Temperature -65°C to 150°C

Operating Current 65mA

Input Power 13dBm

*Guaranteed specification DC-4 GHz. Low frequency cut off determined by external coupling capacitors.

Monolithic InGaP HBT MMIC Amplifier

ISO 9001 ISO 14001 CERTIFIEDMini-Circuits®

P.O. Box 350166, Brooklyn, New York 11235-0003 (718) 934-4500 Fax (718) 332-4661 For detailed performance specs & shopping online see Mini-Circuits web site

The Design Engineers Search Engine Provides ACTUAL Data Instantly From MINI-CIRCUITS At: www.minicircuits.com

RF/IF MICROWAVE COMPONENTS

minicircuits.comALL NEW

Page 3 of 4

R BIAS

Vcc “1%” Res. Values (ohms)for Optimum Biasing

7 52.38 71.59 90.9

10 11011 13012 15013 16914 19115 21516 23217 24918 27419 28720 309

Gali 55+

55

Recommended Application Circuit

4

2

3

1

Cblock

IN

Cblock

Ibias

OUTVd

RFC (Optional)

Cbypass

VccRbias (Required)

Test Board includes case, connectors, and components (in bold) soldered to PCB

Case Style: DF782

Suggested Layout for PCB Design: PL-019

Plastic package, exposed paddle, lead finish: tin/silver/nickel

Evaluation Board: TB-409-55+

Tape & Reel: F55

Additional Detailed Technical InformationAdditional information is available on our web site. To access this information enter the model number on our web site home page.

Environmental Ratings: ENV08T2

Performance data, graphs, s-parameter data set (.zip file)

Product Marking

Monolithic InGaP HBT MMIC Amplifier

ISO 9001 ISO 14001 CERTIFIEDMini-Circuits®

P.O. Box 350166, Brooklyn, New York 11235-0003 (718) 934-4500 Fax (718) 332-4661 For detailed performance specs & shopping online see Mini-Circuits web site

The Design Engineers Search Engine Provides ACTUAL Data Instantly From MINI-CIRCUITS At: www.minicircuits.com

RF/IF MICROWAVE COMPONENTS

minicircuits.comALL NEW

Page 4 of 4

ESD RatingHuman Body Model (HBM): Class 1B (500v to < 1000v) in accordance with ANSI/ESD STM 5.1 - 2001

Machine Model (MM): Class M1 (< 100v) in accordance with ANSI/ESD STM 5.2 - 1999

No. Test Required Condition Standard Quantity

1 Visual Inspection Low Power MicroscopeMagnification 40x

MIP-IN-0003(MCT spec) 45 units

2 Electrical Test Room Temperature SCD(MCL spec) 45 units

3 SAM Analysis Less than 10% growth in term of delamination

J-Std-020C(Jedec Standard) 45 units

4 Moisture SensitivityLevel 1

Bake at 125°C for 24 hoursSoak at 85°C/85%RH for 168 hoursReflow 3 cycles at 260°C peak

J-Std-020C(Jedec Standard) 45 units

VisualInspection

Electrical Test SAM Analysis

Reflow 3 cycles,260°C

Soak85°C/85RH168 hours

Bake at 125°C,24 hours

VisualInspection Electrical Test SAM Analysis

Start

MSL Test Flow Chart

MSL RatingMoisture Sensitivity: MSL1 in accordance with IPC/JEDECJ-STD-020C

Gali 55+

L7800SERIES

POSITIVE VOLTAGE REGULATORS

November 2000

OUTPUT CURRENT UP TO 1.5 A OUTPUT VOLTAGESOF 5; 5.2; 6; 8; 8.5; 9;

12; 15; 18; 24V THERMAL OVERLOAD PROTECTION SHORT CIRCUIT PROTECTION OUTPUT TRANSITION SOA PROTECTION

DESCRIPTIONThe L7800 series of three-terminal positiveregulators is available in TO-220 TO-220FP TO-3and D2PAK packages and several fixed outputvoltages, making it useful in a wide range ofapplications.These regulators can provide localon-card regulation, eliminating the distributionproblems associated with single point regulation.Each type employs internal current limiting,thermal shut-down and safe area protection,making it essentially indestructible. If adequateheat sinking is provided, they can deliver over 1Aoutput current. Although designed primarily asfixed voltage regulators, these devices can beused with external components to obtainadjustable voltages and currents.

12

TO-3

TO-220 TO-220FP

D2PAK

BLOCK DIAGRAM

1/25

CONNECTION DIAGRAM AND ORDERING NUMBERS (top view)

TO-220 & TO-220FP TO-3D2PAK

THERMAL DATASymbol Parameter D 2PAK TO-220 TO-220FP TO-3 Unit

Rthj- ca se

Rthj-amb

Thermal Resistance Junction-case MaxThermal Resistance Junction-ambient Max

362.5

350

560

435

oC/WoC/W

Type TO-220 D2PAK (*) TO-220FP TO-3 Output Voltage

L7805L7805CL7852CL7806L7806CL7808L7808CL7885CL7809CL7812L7812CL7815L7815CL7818L7818CL7820L7820CL7824L7824C

L7805CVL7852CV

L7806CV

L7808CVL7885CVL7809CV

L7812CV

L7815CV

L7818CV

L7820CV

L7824CV

L7805CD2TL7852CD2T

L7806CD2T

L7808CD2TL7885CD2TL7809CD2T

L7812CD2T

L7815CD2T

L7818CD2T

L7820CD2T

L7824CD2T

L7805CPL7852CP

L7806CP

L7808CPL7885CPL7809CP

L7812CP

L7815CP

L7818CP

L7820CP

L7824CP

L7805TL7805CTL7852CTL7806TL7806CTL7808TL7808CTL7885CTL7809CTL7812TL7812CTL7815TL7815CTL7818TL7818CTL7820TL7820CTL7824TL7824CT

5V5V

5.2V6V6V8V8V

8.5V9V

12V12V15V15V18V18V20V20V24V24V

(*) AVAILABLE IN TAPE AND REEL WITH ”-TR” SUFFIX

ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value Unit

Vi DC Input Voltage (for VO = 5 to 18V)(forVO = 20, 24V)

3540

VV

Io Output Current Internally limited

Ptot Power Dissipation Internally limited

Top Operating Junction Temperature Range (for L7800)(for L7800C)

-55 to 1500 to 150

oCoC

Tstg Storage Temperature Range -65 to 150 oC

L7800

2/25

APPLICATION CIRCUIT

SCHEMATIC DIAGRAM

L7800

3/25

TEST CIRCUITS

Figure 3 : Ripple Rejection.

Figure 2 : Load Regulation.Figure 1 : DC Parameter

L7800

4/25

ELECTRICAL CHARACTERISTICS FOR L7806 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 15V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 5.75 6 6.25 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 9 to 21 V

5.65 6 6.35 V

∆Vo* Line Regulation Vi = 8 to 25 V Tj = 25 oCVi = 9 to 13 V Tj = 25 oC

6030

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

10030

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 9 to 25 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 0.7 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 9 to 19 V f = 120Hz 65 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 19 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A

ELECTRICAL CHARACTERISTICS FOR L7805 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 10V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 4.8 5 5.2 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 8 to 20 V

4.65 5 5.35 V

∆Vo* Line Regulation Vi = 7 to 25 V Tj = 25 oCVi = 8 to 12 V Tj = 25 oC

31

5025

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

10025

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 8 to 25 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 0.6 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 8 to 18 V f = 120Hz 68 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 17 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

5/25

ELECTRICAL CHARACTERISTICS FOR L7812 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 19V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 11.5 12 12.5 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 15.5 to 27 V

11.4 12 12.6 V

∆Vo* Line Regulation Vi = 14.5 to 30 V Tj = 25 oCVi = 16 to 22 V Tj = 25 oC

12060

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

10060

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 15 to 30 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 1.5 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 15 to 25 V f = 120 Hz 61 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 18 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A

ELECTRICAL CHARACTERISTICS FOR L7808 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 14V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 7.7 8 8.3 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 11.5 to 23 V

7.6 8 8.4 V

∆Vo* Line Regulation Vi = 10.5 to 25 V Tj = 25 oCVi = 11 to 17 V Tj = 25 oC

8040

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

10040

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 11.5 to 25 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 1 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 11.5 to 21.5 V f = 120 Hz 62 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 16 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

6/25

ELECTRICAL CHARACTERISTICS FOR L7818 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 26V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 17.3 18 18.7 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 22 to 33 V

17.1 18 18.9 V

∆Vo* Line Regulation Vi = 21 to 33 V Tj = 25 oCVi = 24 to 30 V Tj = 25 oC

18090

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

18090

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 22 to 33 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 2.3 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 22 to 32 V f = 120 Hz 59 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 22 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A

ELECTRICAL CHARACTERISTICS FOR L7815 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 23V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 14.4 15 15.6 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 18.5 to 30 V

14.25 15 15.75 V

∆Vo* Line Regulation Vi = 17.5 to 30 V Tj = 25 oCVi = 20 to 26 V Tj = 25 oC

15075

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

15075

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 18.5 to 30 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 1.8 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 18.5 to 28.5 V f = 120 Hz 60 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 19 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

7/25

ELECTRICAL CHARACTERISTICS FOR L7824 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 33V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 23 24 25 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 28 to 38 V

22.8 24 25.2 V

∆Vo* Line Regulation Vi = 27 to 38 V Tj = 25 oCVi = 30 to 36 V Tj = 25 oC

240120

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

240120

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 28 to 38 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 3 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 28 to 38 V f = 120 Hz 56 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 28 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A

ELECTRICAL CHARACTERISTICS FOR L7820 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 28V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 19.2 20 20.8 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 24 to 35 V

19 20 21 V

∆Vo* Line Regulation Vi = 22.5 to 35 V Tj = 25 oCVi = 26 to 32 V Tj = 25 oC

200100

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

200100

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 24 to 35 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 2.5 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 24 to 35 V f = 120 Hz 58 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 24 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

8/25

ELECTRICAL CHARACTERISTICS FOR L7852C (refer to the test circuits, Tj = 0 to 125 oC, Vi = 10V,Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 5.0 5.2 5.4 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 8 to 20 V

4.95 5.2 5.45 V

∆Vo* Line Regulation Vi = 7 to 25 V Tj = 25 oCVi = 8 to 12 V Tj = 25 oC

31

10552

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

10552

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 7 to 25 V 1.3 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -1.0 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 42 µV

SVR Supply Voltage Rejection Vi = 8 to 18 V f = 120Hz 61 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 17 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 750 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.2 A

ELECTRICAL CHARACTERISTICS FOR L7805C (refer to the test circuits, Tj = 0 to 125 oC,Vi = 10V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 4.8 5 5.2 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 7 to 20 V

4.75 5 5.25 V

∆Vo* Line Regulation Vi = 7 to 25 V Tj = 25 oCVi = 8 to 12 V Tj = 25 oC

31

10050

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

10050

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 7 to 25 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -1.1 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV

SVR Supply Voltage Rejection Vi = 8 to 18 V f = 120Hz 62 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 17 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 750 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.2 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

9/25

ELECTRICAL CHARACTERISTICS FOR L7808C (refer to the test circuits, Tj = 0 to 125 oC, Vi = 14V,Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 7.7 8 8.3 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 10.5 to 25 V

7.6 8 8.4 V

∆Vo* Line Regulation Vi = 10.5 to 25 V Tj = 25 oCVi = 11 to 17 V Tj = 25 oC

16080

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

16080

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 10.5 to 25 V 1 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -0.8 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 52 µV

SVR Supply Voltage Rejection Vi = 11.5 to 21.5 V f = 120 Hz 56 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 16 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 450 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.2 A

ELECTRICAL CHARACTERISTICS FOR L7806C (refer to the test circuits, Tj = 0 to 125 oC,Vi = 11V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 5.75 6 6.25 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 8 to 21 V

5.7 6 6.3 V

∆Vo* Line Regulation Vi = 8 to 25 V Tj = 25 oCVi = 9 to 13 V Tj = 25 oC

12060

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

12060

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 8 to 25 V 1.3 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -0.8 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 45 µV

SVR Supply Voltage Rejection Vi = 9 to 19 V f = 120Hz 59 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 19 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 550 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.2 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

10/25

ELECTRICAL CHARACTERISTICS FOR L7809C (refer to the test circuits, Tj = 0 to 125 oC, Vi = 15V,Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 8.65 9 9.35 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 11.5 to 26 V

8.55 9 9.45 V

∆Vo* Line Regulation Vi = 11.5 to 26 V Tj = 25 oCVi = 12 to 18 V Tj = 25 oC

18090

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

18090

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 11.5 to 26 V 1 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -1.0 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 70 µV

SVR Supply Voltage Rejection Vi = 12 to 23 V f = 120 Hz 55 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 17 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 400 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.2 A

ELECTRICAL CHARACTERISTICS FOR L7885C (refer to the test circuits, Tj = 0 to 125 oC, Vi =14.5V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 8.2 8.5 8.8 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 11 to 26 V

8.1 8.5 8.9 V

∆Vo* Line Regulation Vi = 11 to 27 V Tj = 25 oCVi = 11.5 to 17.5 V Tj = 25 oC

16080

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

16080

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 11 to 27 V 1 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -0.8 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 55 µV

SVR Supply Voltage Rejection Vi = 12 to 22 V f = 120 Hz 56 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 16 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 450 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.2 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

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ELECTRICAL CHARACTERISTICS FOR L7815C (refer to the test circuits, Tj = 0 to 125 oC, Vi = 23V,Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 14.4 15 15.6 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 17.5 to 30 V

14.25 15 15.75 V

∆Vo* Line Regulation Vi = 17.5 to 30 V Tj = 25 oCVi = 20 to 26 V Tj = 25 oC

300150

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

300150

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 17.5 to 30 V 1 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -1 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 90 µV

SVR Supply Voltage Rejection Vi = 18.5 to 28.5 V f = 120 Hz 54 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 19 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 230 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.1 A

ELECTRICAL CHARACTERISTICS FOR L7812C (refer to the test circuits, Tj = 0 to 125 oC, Vi = 19V,Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 11.5 12 12.5 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 14.5 to 27 V

11.4 12 12.6 V

∆Vo* Line Regulation Vi = 14.5 to 30 V Tj = 25 oCVi = 16 to 22 V Tj = 25 oC

240120

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

240120

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 14.5 to 30 V 1 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -1 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 75 µV

SVR Supply Voltage Rejection Vi = 15 to 25 V f = 120 Hz 55 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 18 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 350 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.2 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

12/25

ELECTRICAL CHARACTERISTICS FOR L7820C (refer to the test circuits, Tj = 0 to 125 oC, Vi = 28V,Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 19.2 20 20.8 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 23 to 35 V

19 20 21 V

∆Vo* Line Regulation Vi = 22.5 to 35 V Tj = 25 oCVi = 26 to 32 V Tj = 25 oC

400200

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

400200

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 23 to 35 V 1 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -1 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 150 µV

SVR Supply Voltage Rejection Vi = 24 to 35 V f = 120 Hz 52 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 24 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 180 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.1 A

ELECTRICAL CHARACTERISTICS FOR L7818C (refer to the test circuits, Tj = 0 to 125 oC, Vi = 26V,Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 17.3 18 18.7 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 21 to 33 V

17.1 18 18.9 V

∆Vo* Line Regulation Vi = 21 to 33 V Tj = 25 oCVi = 24 to 30 V Tj = 25 oC

360180

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

360180

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 21 to 33 V 1 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -1 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 110 µV

SVR Supply Voltage Rejection Vi = 22 to 32 V f = 120 Hz 53 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 22 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 200 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.1 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

L7800

13/25

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into accountseparately. Pulce testing with low duty cycle is used.

ELECTRICAL CHARACTERISTICS FOR L7824C (refer to the test circuits, Tj = 0 to 125 oC, Vi = 33V,Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 23 24 25 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 27 to 38 V

22.8 24 25.2 V

∆Vo* Line Regulation Vi = 27 to 38 V Tj = 25 oCVi = 30 to 36 V Tj = 25 oC

480240

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

480240

mVmV

Id Quiescent Current Tj = 25 oC 8 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 27 to 38 V 1 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA -1.5 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 170 µV

SVR Supply Voltage Rejection Vi = 28 to 38 V f = 120 Hz 50 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V

Ro Output Resistance f = 1 KHz 28 mΩ

Is c Short Circuit Current Vi = 35 V Tj = 25 oC 150 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.1 A

L7800

14/25

Figure 8 : Output Impedance vs. Frequency. Figure 9 : Quiescent Current vs. JunctionTemperature.

Figure 4 : Dropout Voltage vs. JunctionTemperature.

Figure 5 : Peak Output Current vs. Input/outputDifferential Voltage.

Figure 6 : Supply Voltage Rejection vs.Frequency.

Figure 7 : Output Voltage vs. JunctionTemperature.

L7800

15/25

Figure 12 : Quiescent Current vs. InputVoltage.

Figure 13 : Fixed Output Regulator. Figure 14 : Current Regulator.

Figure 10 : Load Transient Response. Figure 11 : Line Transient Response.

NOTE:1. To specify an output voltage, substitute voltage value for ”XX”.2. Although no output capacitor is need for stability, it doesimprove transient response.3. Required if cregulator is locate an appreciable distance frompower supply filter.

IO =V XX

R 1+ I d

L7800

16/25

Figure 15 : Circuit for Increasing OutputVoltage.

Figure 16 : Adjustable Output Regulator(7 to 30V).

Figure 17 : 0.5 to 10V Regulator. Figure 18 : High Current Voltage Regulator.

IR1 ≥ 5 Id

VO = V XX (1 + R 2

R 1) + I d R 2

VO = V XXR 4

R 1

R1 =V BEQ1

I REQ −I Q1

β Q1

IO = I REG + Q 1 (I REG −V BEQ1

R 1)

L7800

17/25

Figure 19 : High Output Current with ShortCircuit Protection.

Figure 20 : Tracking Voltage Regulator.

Figure 21 : Split Power Supply (± 15V – 1A). Figure 22 : Negative Output Voltage Circuit.

Figure 23 : Switching Regulator. Figure 24 : High Input Voltage Circuit.

VIN = Vi - (VZ + VBE)

* Against potential latch-up problems.

RSC =V BEQ2

I SC

L7800

18/25

Figure 27 : High Input and Output Voltage. Figure 28 : Reducing Power Dissipation withDr opping Resistor.

Figure 29 : Remote Shutdown.

Figure 25 : High Input Voltage Circuit. Figure 26 : High Output Voltage Regulator.

VO = VXX + VZ1 R =V i(min) − V XX − V DROP(max)

I O(max) + I d(max)

L7800

19/25

Figure 30 : Power AM Modulator (unity voltagegain, Io < 1A).

Figure 31 : Adjustable Output Voltage withTemperatureCompensation.

NOTE: The circuit performs well up to 100KHz NOTE: Q2 is connected as a diode in order to compensate thevariation of the Q1 VBE with the temperature. C allows a slow rise-time of the Vo

Figure 32 : Light Controllers (Vo min = Vxx + VBE).

Figure 33 : Protection against Input Short-circuitwith High Capacitance Loads.

Application with high capacitance loads and an output voltagegreater than 6 volts need an external diode (see fig. 33) to protectthe deviceagainst input short circuit. In this case the input voltagefalls rapidly while the output voltage decrease slowly. Thecapacitance dischrges by means of the Base-Emitter junction ofthe series pass transistor in the regulator. If the energy issufficently high, the transistor may be destroyed. The externaldiode by-passes the current from the IC to ground.

VO falls when the light goes up VO rises when the light goes up

VO = V XX (1 +R 2

R 1) + V BE

L7800

20/25

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 11.7 0.460

B 0.96 1.10 0.037 0.043

C 1.70 0.066

D 8.7 0.342

E 20.0 0.787

G 10.9 0.429

N 16.9 0.665

P 26.2 1.031

R 3.88 4.09 0.152 0.161

U 39.50 1.555

V 30.10 1.185

E

B

R

C

DAP

G

N

VU

O

P003N

TO-3 (R) MECHANICAL DATA

L7800

21/25

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.40 4.60 0.173 0.181

C 1.23 1.32 0.048 0.051

D 2.40 2.72 0.094 0.107

D1 1.27 0.050

E 0.49 0.70 0.019 0.027

F 0.61 0.88 0.024 0.034

F1 1.14 1.70 0.044 0.067

F2 1.14 1.70 0.044 0.067

G 4.95 5.15 0.194 0.203

G1 2.4 2.7 0.094 0.106

H2 10.0 10.40 0.393 0.409

L2 16.4 0.645

L4 13.0 14.0 0.511 0.551

L5 2.65 2.95 0.104 0.116

L6 15.25 15.75 0.600 0.620

L7 6.2 6.6 0.244 0.260

L9 3.5 3.93 0.137 0.154

DIA. 3.75 3.85 0.147 0.151

L6

A

C D

E

D1

F

G

L7

L2

Dia.

F1

L5

L4

H2

L9

F2

G1

TO-220 MECHANICAL DATA

P011C

L7800

22/25

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.4 4.6 0.173 0.181

B 2.5 2.7 0.098 0.106

D 2.5 2.75 0.098 0.108

E 0.45 0.7 0.017 0.027

F 0.75 1 0.030 0.039

F1 1.15 1.7 0.045 0.067

F2 1.15 1.7 0.045 0.067

G 4.95 5.2 0.195 0.204

G1 2.4 2.7 0.094 0.106

H 10 10.4 0.393 0.409

L2 16 0.630

L3 28.6 30.6 1.126 1.204

L4 9.8 10.6 0.385 0.417

L6 15.9 16.4 0.626 0.645

L7 9 9.3 0.354 0.366

Ø 3 3.2 0.118 0.126

L2

A

B

D

E

H G

L6

¯ F

L3

G1

1 2 3

F2

F1

L7

L4

P011G4/B

TO-220FP MECHANICAL DATA

L7800

23/25

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.4 4.6 0.173 0.181

A1 2.49 2.69 0.098 0.106

B 0.7 0.93 0.027 0.036

B2 1.14 1.7 0.044 0.067

C 0.45 0.6 0.017 0.023

C2 1.23 1.36 0.048 0.053

D 8.95 9.35 0.352 0.368

E 10 10.4 0.393 0.409

G 4.88 5.28 0.192 0.208

L 15 15.85 0.590 0.624

L2 1.27 1.4 0.050 0.055

L3 1.4 1.75 0.055 0.068

L2 L3L

B2 B

GE

A

C2

D

C

A1

DETAIL”A”DETAIL”A”

A2

P011P6/F

TO-263 (D2PAK) MECHANICAL DATA

L7800

24/25

Information furnished isbelieved to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication aresubject to change without notice. Thispublication supersedes and replaces all information previously supplied. STMicroelectronics productsare not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

2000 STMicroelectronics – Printed in Italy – All Rights ReservedSTMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com.

L7800

25/25

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

© 2000 Fairchild Semiconductor Corporation DS006345 www.fairchildsemi.com

August 1986

Revised March 2000

DM

74LS

04 Hex In

verting

Gates

DM74LS04Hex Inverting Gates

General DescriptionThis device contains six independent gates each of whichperforms the logic INVERT function.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function TableY = A

H = HIGH Logic LevelL = LOW Logic Level

Order Number Package Number Package Description

DM74LS04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS04SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Input Output

A Y

L H

H L

www.fairchildsemi.com 2

DM

74L

S04 Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.

Recommended Operating Conditions

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typicals are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics at VCC = 5V and TA = 25°C

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

TA Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions MinTyp

Max Units(Note 2)

VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max,2.7 3.4 V

Output Voltage VIL = Max

VOL LOW Level VCC = Min, IOL = Max,0.35 0.5

Output Voltage VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max VCC = Max, VI = 7V 0.1 mA

Input Voltage

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.36 mA

IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA

ICCH Supply Current with Outputs HIGH VCC = Max 1.2 2.4 mA

ICCL Supply Current with Outputs LOW VCC = Max 3.6 6.6 mA

RL = 2 kΩ

Symbol Parameter CL = 15 pF CL = 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time3 10 4 15 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time3 10 4 15 ns

HIGH-to-LOW Level Output

3 www.fairchildsemi.com

DM

74LS

04Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 NarrowPackage Number M14A

www.fairchildsemi.com 4

DM

74L

S04 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M14D

5 www.fairchildsemi.com

DM

74LS

04 Hex In

verting

Gates

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.

2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

©2002 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.2

Features• Internally Frequency Compensated for Unity Gain• Large DC Voltage Gain: 100dB• Wide Power Supply Range:

LM258/LM258A, LM358/LM358A: 3V~32V (or ±1.5V ~ 16V)LM2904 : 3V~26V (or ±1.5V ~ 13V)

• Input Common Mode Voltage Range Includes Ground• Large Output Voltage Swing: 0V DC to Vcc -1.5V DC• Power Drain Suitable for Battery Operation.

DescriptionThe LM2904,LM358/LM358A, LM258/LM258A consist oftwo independent, high gain, internally frequency compensated operational amplifiers which were designedspecifically to operate from a single power supply over awide range of voltage. Operation from split power suppliesis also possible and the low power supply current drain isindependent of the magnitude of the power supply voltage.Application areas include transducer amplifier, DC gainblocks and all the conventional OP-AMP circuits which nowcan be easily implemented in single power supply systems.

8-DIP

8-SOP

1

1

Internal Block Diagram

-+

+

-

1

2

3

4 5

6

7

8 VCC

OUT2

IN2 (-)

IN2 (+)

OUT1

IN1 (-)

IN1 (+)

GND

LM2904,LM358/LM358A,LM258/LM258ADual Operational Amplifier

LM2904,LM358/LM358A,LM258/LM258A

2

Schematic Diagram(One section only)

Absolute Maximum RatingsParameter Symbol LM258/LM258A LM358/LM358A LM2904 UnitSupply Voltage VCC ±16 or 32 ±16 or 32 ±13 or 26 VDifferential Input Voltage VI(DIFF) 32 32 26 VInput Voltage VI -0.3 to +32 -0.3 to +32 -0.3 to +26 VOutput Short Circuit to GNDVCC≤15V, TA = 25°C(One Amp) - Continuous Continuous Continuous -

Operating Temperature Range TOPR -25 ~ +85 0 ~ +70 -40 ~ +85 °CStorage Temperature Range TSTG -65 ~ +150 -65 ~ +150 -65 ~ +150 °C

Q8

Q7

Q6Q5

Q4

Q3Q2

Q1

Q9

Q10

Q11

Q12

Q14

Q15

Q16

Q18

Q19

Q20

R2

Q21

C1R1

GND

OUTPUTIN(+)

IN(-)

VCC

Q13

Q17

LM2904,LM358/LM358A,LM258/LM258A

3

Electrical Characteristics(Vcc = 5.0V, VEE = GND, TA = 25°C, unless otherwise specified)

Note:1. This parameter, although guaranteed, is not 100% tested in production.

Parameter Symbol ConditionsLM258 LM358 LM2904

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Input Offset Voltage VIO

VCM = 0V to VCC-1.5VVO(P) = 1.4V, RS = 0Ω

- 2.9 5.0 - 2.9 7.0 - 2.9 7.0 mV

Input Offset Current IIO - - 3 30 - 5 50 - 5 50 nA

Input Bias Current IBIAS - - 45 150 - 45 250 - 45 250 nA

Input Voltage Range VI(R)

VCC = 30V(LM2904, VCC=26V) 0 - Vcc

-1.5 0 -Vcc-1.5 0 -

Vcc-1.5 V

Supply Current ICC

RL = ∞, VCC = 30V(LM2904, VCC=26V) - 0.8 2.0 - 0.8 2.0 - 0.8 2.0 mA

RL = ∞, VCC = 5V - 0.5 1.2 - 0.5 1.2 - 0.5 1.2 mA

Large SignalVoltage Gain GV

VCC = 15V, RL= 2kΩVO(P) = 1V to 11V

50 100 - 25 100 - 25 100 - V/mV

Output Voltage Swing

VO(H) VCC=30V(VCC =26V for LM2904)

RL = 2kΩ 26 - - 26 - - 22 - - VRL=10kΩ 27 28 - 27 28 - 23 24 - V

VO(L) VCC = 5V, RL= 10kΩ - 5 20 - 5 20 - 5 20 mVCommon-ModeRejection Ratio CMRR - 70 85 - 65 80 - 50 80 - dB

Power SupplyRejection Ratio PSRR - 65 100 - 65 100 - 50 100 - dB

Channel Separation CS f = 1kHz to 20kHz

(Note1) - 120 - - 120 - - 120 - dB

Short Circuit to GND ISC - - 40 60 - 40 60 - 40 60 mA

Output Current

ISOURCE

VI(+) = 1V, VI(-) = 0VVCC = 15V, VO(P) = 2V

20 30 - 20 30 - 20 30 - mA

ISINK

VI(+) = 0V, VI(-) = 1V, VCC = 15V, VO(P) = 2V

10 15 - 10 15 - 10 15 - mA

VI(+) = 0V,VI(-) =1V , VCC = 15V, VO(P) = 200mV

12 100 - 12 100 - - - - µA

Differential Input Voltage VI(DIFF) - - - VCC - - VCC - - VCC V

LM2904,LM358/LM358A,LM258/LM258A

4

Electrical Characteristics (Continued)

(VCC= 5.0V, VEE = GND, unless otherwise specified)The following specification apply over the range of -25°C ≤ TA ≤ +85°C for the LM258; and the 0°C ≤ TA ≤ +70°C for the LM358; and the -40°C ≤ TA ≤ +85°C for the LM2904

Parameter Symbol ConditionsLM258 LM358 LM2904

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Input Offset Voltage VIO

VCM = 0V to VCC -1.5VVO(P) = 1.4V, RS = 0Ω

- - 7.0 - - 9.0 - - 10.0 mV

Input Offset Voltage Drift ∆VIO/∆T RS = 0Ω - 7.0 - - 7.0 - - 7.0 - µV/°C

Input Offset Current

IIO - - - 100 - - 150 - 45 200 nA

Input Offset Current Drift ∆IIO/∆T - - 10 - - 10 - - 10 - pA/°C

Input Bias Current IBIAS - - 40 300 - 40 500 - 40 500 nA

Input Voltage Range VI(R)

VCC = 30V(LM2904 , VCC = 26V)

0 - Vcc-2.0 0 -

Vcc -2.0 0 -

Vcc -2.0 V

Large Signal Voltage Gain GV

VCC = 15V, RL =2.0kΩVO(P) = 1V to 11V

25 - - 15 - - 15 - - V/mV

Output Voltage Swing

VO(H)

VCC=30V(VCC = 26V for LM2904)

RL = 2kΩ 26 - - 26 - - 22 - - V

RL=10kΩ 27 28 - 27 28 - 23 24 - V

VO(L) VCC = 5V, RL=10kΩ - 5 20 - 5 20 - 5 20 mV

Output Current

ISOURCE

VI(+) = 1V, VI(-) = 0VVCC = 15V, VO(P) = 2V

10 30 - 10 30 - 10 30 - mA

ISINK

VI(+) = 0V, VI(-) = 1VVCC = 15V, VO(P) = 2V

5 8 - 5 9 - 5 9 - mA

Differential Input Voltage VI(DIFF) - - - VCC - - VCC - - VCC V

LM2904,LM358/LM358A,LM258/LM258A

5

Electrical Characteristics (Continued)

(VCC = 5.0V, VEE = GND, TA = 25°C, unless otherwise specified)

Note:1. This parameter, although guaranteed, is not 100% tested in production.

Parameter Symbol ConditionsLM258A LM358A

UnitMin. Typ. Max. Min. Typ. Max.

Input Offset Voltage VIOVCM = 0V to VCC -1.5VVO(P) = 1.4V, RS = 0Ω - 1.0 3.0 - 2.0 3.0 mV

Input Offset Current IIO - - 2 15 - 5 30 nAInput Bias Current IBIAS - - 40 80 - 45 100 nA

Input Voltage Range VI(R) VCC = 30V 0 - VCC-1.5 0 - VCC

-1.5 V

Supply Current ICCRL = ∞,VCC = 30V - 0.8 2.0 - 0.8 2.0 mARL = ∞, VCC = 5V - 0.5 1.2 - 0.5 1.2 mA

Large Signal Voltage Gain GV

VCC = 15V, RL= 2kΩVO = 1V to 11V 50 100 - 25 100 - V/mV

Output Voltage SwingVOH VCC = 30V

RL = 2kΩ 26 - - 26 - - VRL =10kΩ 27 28 - 27 28 - V

VO(L) VCC = 5V, RL=10kΩ - 5 20 - 5 20 mVCommon-Mode Rejection Ratio CMRR - 70 85 - 65 85 - dB

Power Supply Rejection Ratio PSRR - 65 100 - 65 100 - dB

Channel Separation CS f = 1kHz to 20kHz (Note1) - 120 - - 120 - dBShort Circuit to GND ISC - - 40 60 - 40 60 mA

Output Current

ISOURCEVI(+) = 1V, VI(-) = 0VVCC = 15V, VO(P) = 2V 20 30 - 20 30 - mA

ISINK

VI(+) = 1V, VI(-) = 0VVCC = 15V, VO(P) = 2V 10 15 - 10 15 - mA

Vin + = 0V, Vin (-) = 1VVO(P) = 200mV 12 100 - 12 100 - µA

Differential Input Voltage VI(DIFF) - - - VCC - - VCC V

LM2904,LM358/LM358A,LM258/LM258A

6

Electrical Characteristics (Continued)

(VCC = 5.0V, VEE = GND, unless otherwise specified)The following specification apply over the range of -25°C ≤ TA ≤ +85°C for the LM258A; and the 0°C ≤ TA ≤ +70°C for the LM358A

Parameter Symbol ConditionsLM258A LM358A

UnitMin. Typ. Max. Min. Typ. Max.

Input Offset Voltage VIOVCM = 0V to VCC -1.5VVO(P) = 1.4V, RS = 0Ω - - 4.0 - - 5.0 mV

Input Offset Voltage Drift ∆VIO/∆T - - 7.0 15 - 7.0 20 µV/°CInput Offset Current IIO - - - 30 - - 75 nAInput Offset Current Drift ∆IIO/∆T - - 10 200 - 10 300 pA/°CInput Bias Current IBIAS - - 40 100 - 40 200 nAInput Common-ModeVoltage Range VI(R) VCC = 30V 0 - Vcc

-2.0 0 - Vcc-2.0 V

Output Voltage SwingVO(H) VCC = 30V

RL = 2kΩ 26 - - 26 - - VRL = 10kΩ 27 28 - 27 28 - V

VO(L) VCC = 5V, RL=10kΩ - 5 20 - 5 20 mV

Large Signal Voltage Gain GVVCC = 15V, RL=2.0kΩVO(P) = 1V to 11V 25 - - 15 - - V/mV

Output Current ISOURCE

VI(+) = 1V, VI(-) = 0VVCC = 15V, VO(P) = 2V 10 30 - 10 30 - mA

ISINKVI(+) = 1V, VI(-) = 0VVCC = 15V, VO(P) = 2V 5 9 - 5 9 - mA

Differential Input Voltage VI(DIFF) - - - VCC - - VCC V

LM2904,LM358/LM358A,LM258/LM258A

7

Typical Performance Characteristics

Figure 1. Supply Current vs Supply Voltage Figure 2. Voltage Gain vs Supply Voltage

Figure 3. Open Loop Frequency Response Figure 4. Large Signal Output Swing vs Frequency

Figure 5. Output Characteristics vs Current Sourcing Figure 6. Output Characteristics vs Current Sinking

LM2904,LM358/LM358A,LM258/LM258A

8

Typical Performance Characteristics (Continued)

Figure 7. Input Voltage Range vs Supply Voltage Figure 8. Common-Mode Rejection Ratio

Figure 9. Output Current vs Temperature (Current Limiting) Figure 10. Input Current vs Temperature

Figure 11. Voltage Follower Pulse Response Figure 12. Voltage Follower Pulse Response (Small Signal)

LM2904,LM358/LM358A,LM258/LM258A

9

Mechanical DimensionsPackage

Dimensions in millimeters

6.40 ±0.20

3.30 ±0.30

0.130 ±0.012

3.40 ±0.20

0.134 ±0.008

#1

#4 #5

#8

0.252 ±0.008

9.20

±0.

20

0.79

2.54

0.10

0

0.03

1(

)

0.46

±0.

10

0.01

8 ±0

.004

0.06

0 ±0

.004

1.52

4 ±0

.10

0.36

2 ±0

.008

9.60

0.37

8M

AX

5.080.200

0.330.013

7.62

0~15°

0.300

MAX

MIN

0.25+0.10–0.05

0.010+0.004–0.002

8-DIP

LM2904,LM358/LM358A,LM258/LM258A

10

Mechanical Dimensions (Continued)

PackageDimensions in millimeters

4.92

±0.

20

0.19

4 ±0

.008

0.41

±0.

10

0.01

6 ±0

.004

1.27

0.05

0

5.720.225

1.55 ±0.20

0.061 ±0.008

0.1~0.250.004~0.001

6.00 ±0.30

0.236 ±0.012

3.95 ±0.20

0.156 ±0.008

0.50 ±0.20

0.020 ±0.008

5.13

0.20

2M

AX

#1

#4 #5

0~8°

#8

0.56

0.02

2(

)

1.800.071

MA

X0.

10M

AX

0.00

4

MAX

MIN

+0.10

-0.050.15

+0.004

-0.0020.006

8-SOP

LM2904,LM358/LM358A,LM258/LM258A

11

Ordering InformationProduct Number Package Operating Temperature

LM358N8-DIP

0 ~ +70°CLM358ANLM358M

8-SOPLM358AMLM2904N 8-DIP

-40 ~ +85°CLM2904M 8-SOPLM258N

8-DIP-25 ~ +85°C

LM258ANLM258M

8-SOPLM258AM

LM2904,LM358/LM358A,LM258/LM258A

8/26/02 0.0m 001Stock#DSxxxxxxxx

2002 Fairchild Semiconductor Corporation

LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

SD101AW - SD101CW SCHOTTKY BARRIER SWITCHING DIODE

Features • Low Forward Voltage Drop • Guard Ring Construction for Transient Protection • Negligible Reverse Recovery Time • Very Low Reverse Capacitance • Lead Free/RoHS Compliant (Note 3)

Mechanical Data • Case: SOD-123 • Case Material: Molded Plastic. UL Flammability

Classification Rating 94V-0 • Moisture Sensitivity: Level 1 per J-STD-020C • Leads: Solderable per MIL-STD-202, Method

208 • Lead Free Plating (Matte Tin Finish annealed

over Alloy 42 leadframe) • Polarity: Cathode Band • Marking: Date Code & Type Code, See Page 3 • Type Codes: SD101AW S1 or SK

SD101BW S2 or SK SD101CW S3 or SK

• Ordering Information: See Page 3 • Weight: 0.01 grams (approximate)

SOD-123 Dim Min Max

A 3.55 3.85

B 2.55 2.85

C 1.40 1.70

D — 1.35

0.45 0.65 E

0.55 Typical

G 0.25 —

H 0.11 Typical

J — 0.10

α 0° 8°

All Dimensions in mm

Maximum Ratings @TA = 25°C unless otherwise specified

Characteristic Symbol SD101AW SD101BW SD101CW Unit Peak Repetitive Reverse Voltage Working Peak Reverse Voltage DC Blocking Voltage

VRRMVRWM

VR

60 50 40 V

RMS Reverse Voltage VR(RMS) 42 35 28 V Forward Continuous Current (Note 1) IFM 15 mA Non-Repetitive Peak Forward Surge Current @ t ≤ 1.0s @ t = 10μs IFSM

50 2.0

mA A

Power Dissipation (Note 1) Pd 400 mW Thermal Resistance, Junction to Ambient Air (Note 1) RθJA 300 °C/W Operating and Storage Temperature Range Tj, TSTG -65 to +125 °C

Electrical Characteristics @TA = 25°C unless otherwise specified

Characteristic Symbol Min Max Unit Test Condition Reverse Breakdown Voltage (Note 2) SD101AW SD101BW SD101CW

V(BR)R

60 50 40

⎯ V IR = 10μA IR = 10μA IR = 10μA

Forward Voltage Drop SD101AW SD101BW SD101CW SD101AW SD101BW SD101CW

VFM ⎯

0.41 0.40 0.39 1.00 0.95 0.90

V

IF = 1.0mA IF = 1.0mA IF = 1.0mA IF = 15mA IF = 15mA IF = 15mA

Peak Reverse Current (Note 2) SD101AW SD101BW SD101CW

IRM ⎯ 200 nA VR = 50V VR = 40V VR = 30V

Total Capacitance SD101AW SD101BW SD101CW

CT ⎯ 2.0 2.1 2.2

pF VR = 0V, f = 1.0MHz

Reverse Recovery Time trr ⎯ 1.0 ns IF = IR = 5.0mA, Irr = 0.1 x IR, RL = 100Ω

Notes: 1. Part mounted on FR-4 board with recommended pad layout, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. 2. Short duration pulse test used to minimize self-heating effect. 3. No purposefully added lead.

DS11012 Rev. 17 - 2

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SD101AW-SD101CW © Diodes Incorporated

DS11012 Rev. 17 - 2

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SD101AW-SD101CW © Diodes Incorporated

Ordering Information (Note 4)

Device Packaging Shipping SD101xW-7-F SOD-123 3000/Tape and Reel

SD101xW-13-F SOD-123 10,000/Tape and Reel Notes: 4. For Packaging Details, go to our website at http://www.diodes.com/datasheets/ap02007.pdf.

Marking Information

XX = Product Type Marking Code, See Page 1

YM = Date Code Marking Y = Year (ex: T = 2006) M = Month (ex: 9 = September)

Date Code Key

Year 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 Code J K L M N P R S T U V W X Y Z

Month Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Code 1 2 3 4 5 6 7 8 9 O N D

IMPORTANT NOTICE Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to any product herein. Diodes Incorporated does not assume any liability arising out of the application or use of any product described herein; neither does it convey any license under its patent rights, nor the rights of others. The user of products in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on our website, harmless against all damages.

LIFE SUPPORT Diodes Incorporated products are not authorized for use as critical components in life support devices or systems without the expressed written approval of the President of Diodes Incorporated.

DS11012 Rev. 17 - 2

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SD101AW-SD101CW © Diodes Incorporated