87
The Physical Placement Problem in Integrated Circuits Prof. Kurt Keutzer EECS University of California Berkeley, CA Thanks to Prof. A. Kahng

The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

  • Upload
    others

  • View
    4

  • Download
    0

Embed Size (px)

Citation preview

Page 1: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Th

e P

hysic

al P

lacem

en

t P

rob

lem

in

In

teg

rate

d C

ircu

its

Pro

f. K

urt

Ke

utz

er

EE

CS

Un

ive

rsit

y o

f C

ali

forn

ia

Be

rke

ley,

CA

Th

an

ks

to

Pro

f. A

. K

ah

ng

Page 2: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

2K

urt

Keu

tzer

Sch

em

ati

c E

ntr

y D

esig

n F

low

sch

em

ati

ced

ito

r

netl

ist

Lib

rary

ph

ysic

al

desig

n

layo

ut

a b

s

q0 1

d

clk

a b

s

q0 1

d

clk lo

gic

sim

ula

tor

Des

ign

er d

esig

ns

the

circ

uit

on

nap

kin

s an

d b

lack

bo

ard

Gat

e-le

vel d

etai

ls o

f th

e

circ

uit

are

en

tere

d in

a

sch

emat

ic e

ntr

y to

ol

Vec

tors

are

gen

erat

ed t

o

veri

fy t

he

circ

uit

Wh

en lo

gic

is c

orr

ect

the

net

list

is p

asse

d o

ff t

o

ano

ther

gro

up

to

lay

ou

t

Au

tom

ated

pla

ce a

nd

ro

ute

too

ls c

reat

e la

you

t

Page 3: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

RT

L D

esig

n F

low

RT

LS

yn

thesis

HD

L

netl

ist

log

ico

pti

miz

ati

on

netl

ist

Lib

rary

/m

od

ule

gen

era

tors

ph

ysic

al

desig

n

layo

ut

man

ual

desig

n

a b

s

q0 1

d

clk

a b

s

q0 1

d

clk

Page 4: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

4K

urt

Keu

tzer

Th

e N

etl

ist

Wh

en

we f

inis

hed

syn

thesis

or

sch

em

ati

c e

ntr

y w

e

pro

du

ced

a n

etl

ist:

�F

un

cti

on

ally c

orr

ect

�C

orr

ect

tim

ing

rela

tive t

o t

he m

od

els

we u

sed

No

w w

e w

ish

to

tu

rn t

hat

into

a c

orr

ectl

y f

un

cti

on

ing

pla

cem

en

t

55

5

44

4

2

L A T C H

L A T C H

32

11

21

32

1

22

22

19

19

Page 5: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Ph

ys

ica

l D

es

ign

: O

ve

rall

Co

nc

ep

tua

l F

low

Rea

d N

etli

st

Init

ial

Pla

cem

ent

Pla

cem

ent

Imp

rovem

ent

Cost

Est

imati

on

Rou

tin

g R

egio

n

Def

init

ion

Glo

bal

Rou

tin

g

Inp

ut

Pla

cem

ent

Rou

tin

g

Ou

tpu

tC

om

pact

ion

/cle

an

-up

Rou

tin

g R

egio

n

Ord

erin

g

Det

ail

ed R

ou

tin

g

Cost

Est

imati

on

Rou

tin

g

Imp

rovem

ent

Wri

te L

ay

ou

t D

ata

base

Flo

orp

lan

nin

gF

loorp

lan

nin

g

Page 6: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Fo

rmu

lati

on

of

the P

lacem

en

t P

rob

lem

Giv

en

:

�A

ne

tlis

t o

f cell

s f

rom

a p

re-d

efi

ned

se

mic

on

du

cto

r li

bra

ry

�A

ma

the

mati

cal

exp

ressio

n o

f th

at

netl

ist

as a

vert

ex-,

ed

ge

-w

eig

hte

d g

rap

h

�C

on

str

ain

ts o

n p

in-l

ocati

on

s e

xp

ressed

as c

on

str

ain

ts o

n v

ert

ex

locati

on

s /

asp

ect

rati

o t

ha

t th

e p

lacem

en

t n

eed

s t

o f

it in

to

�O

ne

or

mo

re o

f th

e f

oll

ow

ing

: c

hip

-le

ve

l ti

min

g c

on

str

ain

ts,

a l

ist

of

cri

tical

ne

ts,

ch

ip-l

eve

l p

ow

er

co

nstr

ain

ts

Fin

d: �

Cell/v

ert

ex l

oca

tio

ns t

o m

inim

ize p

lace

men

t o

bje

cti

ve

su

bje

ct

toco

nstr

ain

ts

Ob

jec

tives

:

�m

inim

al

dela

y (

faste

st

cycle

tim

e)

�m

inim

al

are

a (

least

die

are

a/c

os

t

�o

ther

nic

eti

es

: e.g

. p

ow

er

Page 7: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

7K

urt

Keu

tzer

Co

ns

tra

int-

dri

ve

n d

es

ign

Wh

en

we f

inis

hed

syn

thesis

or

sch

em

ati

c e

ntr

y w

e b

elieved

that

ou

r cir

cu

it m

et

its t

imin

g c

on

str

ain

ts b

ased

on

exp

ecte

d v

alu

es o

f in

terc

on

nect

dela

ys

We w

an

t d

ow

nstr

eam

ph

ysic

al d

esig

n t

oo

ls t

o h

on

or

tho

se

co

nstr

ain

ts!!

!

55

5

44

4

2

L A T C H

L A T C H

32

11

21

32

1

22

22

19

19

Page 8: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

8K

urt

Keu

tzer

Resu

lts o

f P

lacem

en

t

A b

ad

pla

cem

ent

A g

oo

d p

lace

men

t

A. K

ah

ng

Wh

at’

s g

oo

d a

bo

ut

a g

oo

d p

lacem

en

t?W

hat’

s b

ad

ab

ou

t a b

ad

pla

cem

en

t?

Page 9: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

9K

urt

Keu

tzer

Resu

lts o

f P

lacem

en

t

Bad

pla

ce

men

t c

au

ses r

ou

tin

g

co

ng

esti

on

res

ult

ing

in

:

•In

cre

ases

in

cir

cu

it a

rea (

co

st)

an

d w

irin

g

•L

on

ge

r w

ires � ���

mo

re c

ap

ac

itan

ce

�L

on

ger

dela

y

�H

igh

er

dyn

am

ic p

ow

er

dis

sip

ati

on

Go

od

pla

cm

en

t

•Cir

cu

it a

rea

(co

st)

an

d w

irin

g

decre

ases

•S

ho

rter

wir

es � ���

less c

ap

acit

an

ce

�S

ho

rter

dela

y

�L

ess d

yn

am

ic p

ow

er

dis

sip

ati

on

Page 10: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

10

Ku

rt K

eu

tzer

Wh

y c

an

’t P

D o

be

y c

on

str

ain

ts?

Hig

h level (s

yn

thesis

, sch

em

ati

c e

ntr

y)

esti

mate

s o

f w

ire

dela

y m

ay b

e v

ery

naïv

e

As in

terc

on

nect

dela

y in

cre

ases r

ela

tive t

o g

ate

dela

y a

nd

beco

mes less p

red

icta

ble

it

may b

e im

po

ssib

le t

o p

lace

an

d r

ou

te a

cir

cu

it in

a w

ay t

hat

ho

no

rs in

itia

l co

nstr

aIn

ts

55

5

44

4

2

L A T C H

L A T C H

32

11

21

32

1

22

22

19

19

Page 11: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

11

Ku

rt K

eu

tzer

Tim

ing

an

d P

D

How

do w

e get

[re

flec

t] t

he

del

ay n

um

ber

s on

th

e H

ow

do w

e get

[re

flec

t] t

he

del

ay n

um

ber

s on

th

e

gate

/in

terc

on

nec

t?gate

/in

terc

on

nec

t?

Sta

n C

how

Am

mocore

Andre

w B

. K

ahng U

CS

DM

ajid

Sarr

afz

adeh U

CLA

KK

: W

e h

ave

a f

ew

ch

oic

es a

bo

ut

wh

at

to d

o w

ith

th

e n

etl

ist

du

rin

g p

lacem

en

t:

•L

eave it

exactl

y t

he s

am

e

•Resiz

e g

ate

s a

nd

ad

d b

uff

ers

as w

e g

o

•R

e-f

acto

r/d

up

licate

lo

gic

55

5

44

4

2

L A T C H

L A T C H

32

11

21

32

1

22

22

19

19

Page 12: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

12

Ku

rt K

eu

tzer

Tim

ing

an

d P

D -

2

How

do w

e get

[re

flec

t] t

he

del

ay n

um

ber

s on

th

e H

ow

do w

e get

[re

flec

t] t

he

del

ay n

um

ber

s on

th

e

gate

/in

terc

on

nec

t?gate

/in

terc

on

nec

t?

Sta

n C

how

Am

mocore

Andre

w B

. K

ahng U

CS

DM

ajid

Sarr

afz

adeh U

CLA

KK

: W

e h

ave

a f

ew

ch

oic

es a

bo

ut

wh

at

to d

o w

ith

th

e n

etl

ist

du

rin

g p

lacem

en

t:

•L

eave it

exactl

y t

he s

am

e –

sim

plify

ing

assu

mp

tio

n

•Resiz

e g

ate

s a

nd

ad

d b

uff

ers

as w

e g

o

•R

e-f

acto

r/d

up

licate

lo

gic

55

5

44

4

2

L A T C H

L A T C H

32

11

21

32

1

22

22

19

19

Page 13: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Go

rdia

n P

lacem

en

t F

low

Co

mp

lexit

ysp

ace:

O

(m)

ti

me:

Q

( m

1.5

log

2m

)F

inal p

lacem

en

t•s

tan

dard

cell •m

acro

-cell &

SO

G

Glo

ba

l O

pti

miz

ati

on

m

inim

iza

tio

n

o

f

wir

e len

gth

Part

itio

nin

g

of

the m

od

ule

set

an

d d

issecti

on

of

the p

lace

men

t re

gio

n

Fin

al

P

lacem

en

t

ad

ap

tio

no

f s

tyle

d

ep

en

den

t

co

nstr

ain

ts

mo

du

le c

oo

rdin

ate

s

po

sit

ion

co

nstr

ain

ts

mo

du

le

co

ord

inate

s

Reg

ion

s

w

ith

≤ ≤≤≤k

mo

du

les

Data

flo

w in

th

e p

lacem

en

t p

roced

ure

GO

RD

IAN

Page 14: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Gord

ian: A

Quadra

tic P

lacem

ent A

ppro

ach

•G

lob

al o

pti

miz

ati

on

:

so

lves a

seq

uen

ce o

f q

uad

rati

c

pro

gra

mm

ing

pro

ble

ms

•P

art

itio

nin

g:

en

forc

es t

he n

on

-overl

ap

co

nstr

ain

ts

Page 15: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

15

Ku

rt K

eu

tzer

GO

RD

IAN

(q

uad

rati

c +

part

itio

nin

g)

Par

titi

on

and R

epla

ce

Init

ial

Pla

cem

ent

A. K

ah

ng

Page 16: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Go

rdia

n P

lacem

en

t F

low

J. K

lein

hau

s, G

. S

igl, F

. Jo

han

nes, K

. A

ntr

eic

h,

GO

RD

IAN

: V

LS

I P

lacem

en

t b

y Q

uad

rati

c

Pro

gra

mm

ing

an

d S

licin

g O

pti

miz

ati

on

, IE

EE

Tra

ns. o

n C

AD

, M

arc

h, 1991, p

p. 356 -

365

Page 17: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Lib

rary

Co

nta

ins f

or

each

cell:

�F

un

cti

on

al in

form

ati

on

: c

ell =

a *

b *

c

�T

imin

g in

form

ati

on

: fu

ncti

on

of

�in

pu

t sle

w

�in

trin

sic

dela

y

�o

utp

ut

cap

acit

an

ce

no

n-l

inear

mo

dels

used

in

tab

ula

r ap

pro

ach

�P

hysic

al fo

otp

rin

t (a

rea)

�P

ow

er

ch

ara

cte

risti

cs

Wir

e-l

oad

mo

dels

-fu

ncti

on

of

�B

lock s

ize

�W

irin

g

Lib

rary

Page 18: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Lib

rary

/m

od

ule

gen

era

tors

a b

s

q0 1

d

clk

Siz

e a

nd

asp

ect

rati

o o

f co

re d

ie

Netl

ist

->

100K

->

10M

cells f

rom

lib

rary

Lib

rary

, N

etl

ist,

an

d A

sp

ect

Rati

o

Page 19: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Sett

ing

up

Glo

bal O

pti

miz

ati

on

Page 20: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

GO

RD

IAN

: G

lob

al P

lacem

en

t

We w

an

t to

op

tim

ize t

he d

ela

y o

f cri

tical

path

s

Inste

ad

we:

�o

pti

miz

e t

he s

um

of

sq

uare

s o

f n

et-

len

gth

s t

imes a

sta

tic w

eig

ht

Glo

bal p

lacem

en

t b

y q

uad

rati

c w

ire-l

en

gth

op

tim

izati

on

�P

rob

lem

is c

om

pu

tati

on

all

y t

racta

ble

an

d w

ell b

eh

aved

�G

lob

al co

nn

ecti

vit

y i

s c

on

sid

ere

d a

t all

sta

ges

�A

n i

ncre

asin

g n

um

ber

of

co

nstr

ain

ts i

s i

mp

osed

�G

lob

al p

lacem

en

t o

f m

od

ule

s i

s o

bta

ined

sim

ult

an

eo

usly

fo

r all

su

b-p

rob

lem

s

�N

o d

ep

en

den

ce o

n p

rocessin

g s

eq

uen

ce

Qu

ad

rati

c p

lacem

en

t clu

mp

s c

ell

s i

n c

en

ter

Part

itio

nin

g s

pre

ad

s c

ell

s a

nd

im

po

ses n

ew

co

nstr

ain

ts o

n f

urt

her

op

tim

izati

on

Page 21: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Intu

itiv

e f

orm

ula

tio

n

Giv

en

a s

eri

es o

f p

oin

ts x

1, x2, x3, …

xn

an

d a

co

nn

ecti

vit

y m

atr

ix C

descri

bin

g t

he c

on

necti

on

s

betw

een

th

em

(If

cij

= 1

th

ere

is a

co

nn

ecti

on

betw

een

xi an

d x

j)

Fin

d a

lo

cati

on

fo

r each

xjth

at

min

imiz

es t

he t

ota

l su

m o

f

all s

pri

ng

ten

sio

ns b

etw

een

each

pair

<xi, x

j>

xj

xi

Pro

ble

m h

as a

n o

bvio

us (

triv

ial)

so

luti

on

–w

hat

is it?

Page 22: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Imp

rovin

g t

he in

tuit

ive f

orm

ula

tio

n

To

avo

id t

he t

rivia

l so

luti

on

ad

d c

on

str

ain

ts:

Hx=

b

�T

hese m

ay b

e v

ery

natu

ral -

e.g

. en

dp

oin

ts (

pad

s)

To

in

teg

rate

th

e n

oti

on

of

``cri

tical n

ets

’’

�A

dd

weig

hts

w

ijto

nets

xj

xi

wij

-so

me

sp

rin

gs h

ave

mo

re t

en

sio

nsh

ou

ld p

ull

asso

cia

ted

vert

ices c

loser

x1

xn

wij

Page 23: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Mo

delin

g t

he N

et’

s W

ire L

en

gth

∑ ∑∑∑( (((

) )))( (((

) )))[ [[[

] ]]]y

yx

xL

Mu

vu

vv

uv

vv

− −−−+ +++

− −−−= === ← ←←←

22

mo

du

leu

(xv,y

v) )))

(xu

,yu

) ))))

,(

vuvu

η ηηηξ ξξξ

vup

in

vu lv

net

nod

e

x

yco

nn

ecti

on

to

o

ther

mo

du

les

( x

uv=

=

=

=

xu+ +++

uv

;ξ ξξξ

y uv

=

=

=

= y

u+ +++

y

)vu

Th

e l

en

gth

Lv

of

a n

et

v i

s m

easu

red

by t

he s

qu

are

d d

ista

nces f

rom

its

p

oin

ts t

o t

he n

et’

s c

en

ter

Wh

at

ab

ou

tm

ult

iterm

inal

nets

?

Page 24: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Wh

at

do

we r

eally w

an

t to

op

tim

ize?

Fo

r h

igh

-perf

orm

an

ce c

ircu

its, w

e w

an

t to

min

imiz

e lo

ng

est

path

th

rou

gh

netw

ork

•In

ad

dit

ion

to

to

tal w

ire len

gth

Ap

pro

xim

ate

dela

y m

inim

izati

on

by m

inim

izati

on

of

sq

uare

d w

ire len

gth

•P

en

alizes lo

ng

wir

es

Page 25: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Qu

ad

rati

c O

bje

cti

ve F

un

cti

on

Ob

jecti

ve f

un

cti

on

: w

eig

hte

d s

um

of

the s

qu

are

d n

et

len

gth

s

Wh

ere

N i

s n

ets

set,

wv

is n

et

weig

ht,

an

d L

vis

th

e m

ea

su

re o

f

net

len

gth

Can

re-f

orm

ula

te i

t in

term

s o

f b

lock c

oo

rdin

ate

s (

in o

ne 1

-D)

�xi

-lo

cati

on

s o

f vert

ices (

mo

du

les)

�w

ij -

ed

ge w

eig

hts

(n

et

weig

hts

)

�C

-th

e s

yste

m m

atr

ix

Gen

era

lize t

o 2

-D

νν

ν∈Ν

Φ=

∑L

w

Φ=

−=

∑2

Tij

ij

(x)

w(x

x)

0.5

xC

x

Φ=

−+

−=

+∑

22

TT

iji

ji

j(x

,y)

w[(

xx

)(y

y)

]0

.5x

Cx

0.5

yC

y

Page 26: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Fo

rmu

lati

ng

Op

tim

izati

on

Pro

ble

m

Fo

r sim

plicit

y, w

e’ll co

nsid

er

a 1

-D f

orm

ula

tio

n

Need

to

ad

d a

term

to

acco

un

t fo

r fi

xed

mo

du

les

Th

e v

ecto

r d

is c

on

str

ucte

d b

ased

co

ord

inate

s o

f th

e f

ixed

mo

du

les

an

d p

in c

oo

rdin

ate

s o

f all m

od

ule

s

Als

o n

eed

to

co

nstr

ain

t p

lacem

en

t s.t

. cen

ter-

of-

gra

vit

y (

the a

rea

weig

hte

d m

ean

of

all c

oo

rdin

ate

s)

co

rresp

on

ds t

o t

he c

en

ter

of

pla

cem

en

t re

gio

n:

Th

e v

ecto

r u

co

nta

ins g

eo

metr

ic c

en

ters

of

pla

cem

en

t re

gio

ns, th

e

matr

ix A

refl

ects

th

e a

ssig

nm

en

t o

f m

od

ule

s t

o p

lacem

en

t re

gio

ns

Φ=

+T

T(x

)0

.5x

Cx

dx

=A

xu

Page 27: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

27

Ku

rt K

eu

tzer

Cost

=(x

1−

100)2

+(x

1−

x2)2

+(x

2−

200)2

�x 1

Cost

=2(x

1−

100)+

2(x

1−

x2)

�x 2

Cost

=−

2(x

1−

x2

)+

2(x

2−

200)

sett

ing

the

par

tial der

ivat

ives

= 0

we

solv

e fo

r th

e m

inim

um

Cost

:

Ax

+ B

= 0

=

04

−2

−2

4

x1

x2

+−200

−400

= 0

2−1

−1

2

x1

x2

+−100

−200

x1=

400/3

x

2=

500/3

x2

x1

x=

100

x=

200

Toy

Exam

ple

:

D. P

an

Page 28: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

ρ ρρρ

Qu

ad

rati

c O

pti

miz

ati

on

Pro

ble

m

D

E

F

AB C

),

('

'ρ ρρρ

vu

= ===

M MMML LLLL LLLM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

*0

*0

*0

00

0*

**

')

(

ρ ρρρρ ρρρl

A

GF

ED

CB

A

�L

inearl

y c

on

str

ain

ed

qu

ad

rati

c p

rog

ram

min

g p

rob

lem

)(

{m

inT

T

Rx

x }

dx

Cx

xm

+ +++= ===

Φ ΦΦΦ∈ ∈∈∈

ρ ρρρ)

,(

ρ ρρρv

u

s.t.

)(

)(

ll

ux

A= ===

Wir

e-l

en

gth

fo

r m

ovab

le m

od

ule

s

Ac

co

un

ts f

or

fix

ed

mo

du

les

Cen

ter-

of-

gra

vit

y c

on

str

ain

ts

Pro

ble

m i

s c

om

pu

tati

on

all

y t

racta

ble

, an

d w

ell b

eh

aved

Co

mm

erc

ial

so

lvers

avail

ab

le:

mo

ste

k

Page 29: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

29

Ku

rt K

eu

tzer

Wh

at

do

I n

eed

to

kn

ow

ab

ou

t Q

P?

•G

et

an

in

tuit

ive s

en

se o

f w

hat

qu

ad

rati

c p

rog

ram

min

g is t

ryin

g

to s

olv

e

�C

reate

a g

oo

d p

lacem

en

t o

f th

e n

etl

ist

by p

lacin

g c

ell

s s

o

as t

o m

inim

ize t

he s

qu

are

s o

f th

e w

irele

ng

ths

in t

he n

etl

ist

•U

nd

ers

tan

d s

tren

gth

s a

nd

weakn

es

ses o

f th

e f

orm

ula

tio

n

�S

tren

gth

-o

pti

mal

so

luti

on

!

�W

eakn

ess –

�q

uad

rati

c v

s.

lin

ear

wir

ele

ng

ths

�N

eve

r kn

ow

s (

or

op

tim

izes)

the l

en

gth

of

a p

ath

-o

nly

th

e i

nd

ivid

ual 2-p

in n

ets

•D

on

’t n

eed

to

un

ders

tan

d t

he u

nd

erl

yin

g m

ath

em

ati

cs

Page 30: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Glo

bal O

pti

miz

ati

on

Usin

g Q

uad

rati

c

Pla

cem

en

t

Qu

ad

rati

c p

lacem

en

t clu

mp

s c

ells in

cen

ter

Part

itio

nin

g d

ivid

es c

ells in

to t

wo

reg

ion

s

�P

lacem

en

t re

gio

n is a

lso

div

ided

in

to t

wo

reg

ion

s

New

cen

ter-

of-

gra

vit

y c

on

str

ain

ts a

re a

dd

ed

to

th

e

co

nstr

ain

t m

atr

ix t

o b

e u

sed

on

th

e n

ext

level o

f g

lob

al

op

tim

izati

on

�G

lob

al co

nn

ecti

vit

y is s

till c

on

serv

ed

Page 31: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Sett

ing

up

Glo

bal O

pti

miz

ati

on

Page 32: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Layo

ut

Aft

er

Glo

bal O

pti

miz

ati

on

A. K

ah

ng

Page 33: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Part

itio

nin

g

Page 34: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

34

Ku

rt K

eu

tzer

Part

itio

nin

g

In G

OR

DIA

N, p

art

itio

nin

g is u

sed

to

co

nstr

ain

t th

e m

ovem

en

t

of

mo

du

les r

ath

er

than

red

uce p

rob

lem

siz

e

By p

erf

orm

ing

part

itio

nin

g, w

e c

an

ite

rati

vely

im

po

se a

new

set

of

co

nstr

ain

ts o

n t

he g

lob

al o

pti

miz

ati

on

pro

ble

m

�A

ssig

n m

od

ule

s t

o a

part

icu

lar

blo

ck

Part

itio

nin

g is d

ete

rmin

ed

by

�R

esu

lts o

f g

lob

al p

lacem

en

t –

init

ial sta

rtin

g p

oin

t

�S

pati

al (x

,y)

dis

trib

uti

on

of

mo

du

les

�P

art

itio

nin

g c

ost

�W

an

t a m

in-c

ut

part

itio

n

Page 35: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

35

Ku

rt K

eu

tzer

Part

itio

nin

g d

ue t

o G

lob

al O

pti

miz

ati

on

So

rt t

he m

od

ule

s b

y t

heir

x c

oo

rdin

ate

(fo

r a v

ert

ical cu

t)

Ch

oo

se a

cu

t lin

e s

uch

th

at

are

a is a

pp

roxim

ate

ly e

qu

al

betw

een

tw

o s

ides o

f cu

t

∈ ∈∈∈

∑ ∑∑∑∑ ∑∑∑

∈ ∈∈∈∈ ∈∈∈

≈ ≈≈≈= ===

∈ ∈∈∈≤ ≤≤≤→ →→→

Mu

uM

uu

pp

uu

pp

p

FF

Mu

Mu

xx

MM

M

pp

α ααα0.5

'',

',

''

'''

'''

'''

Page 36: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

∈ ∈∈∈

Part

itio

nin

g Im

pro

vem

en

t -

I

∑ ∑∑∑

∑ ∑∑∑∑ ∑∑∑

∈ ∈∈∈

∈ ∈∈∈∈ ∈∈∈

= ===

≈ ≈≈≈= ===

∈ ∈∈∈≤ ≤≤≤→ →→→

Nc

v

v

Mu

uM

uu

pp

uu

pp

p

C

FF

Mu

Mu

xx

MM

M

pp

wα ααα

α ααα

)(

:cu

t valu

e

0.5

'',

',

p

''

'''

'''

'''

0.0

0

.25

0.5

0.7

5

1

.0

0

40

30

20

10

Cp(α ααα

)

•T

he c

ost

of

init

ial p

art

itio

n m

ay b

e t

oo

hig

h

•C

an

ch

an

ge p

osit

ion

of

the c

ut

to r

ed

uce t

he c

ost

•P

lot

the c

ost

fun

cti

on

, ch

oo

se “

best”

po

sit

ion

Page 37: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Layo

ut

aft

er

Min

-cu

t

No

w g

lob

al p

lacem

en

t p

rob

lem

will b

e s

olv

ed

ag

ain

w

ith

tw

o a

dd

itio

nal cen

ter_

of_

gra

vit

y c

on

str

ain

ts

Page 38: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Ad

din

g P

osit

ion

ing

Co

nstr

ain

ts

•P

art

itio

nin

g g

ives u

s t

wo

n

ew

“cen

ter

of

gra

vit

y”

co

nstr

ain

ts

•S

imp

ly u

pd

ate

co

nstr

ain

t m

atr

ix

•S

till a

sin

gle

glo

bal

op

tim

izati

on

pro

ble

m

•P

art

itio

nin

g is n

ot

“ab

so

lute

”•

mo

du

les c

an

mig

rate

b

ack d

uri

ng

op

tim

izati

on

•m

ay n

eed

to

re-p

art

itio

n

Page 39: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Co

nti

nu

e t

o Ite

rate

Page 40: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

GO

RD

IAN

Pro

ced

ure

Go

rdia

nl:

=1;

glo

bal-

op

tim

ize(l

);

wh

ile(∃ ∃∃∃

|Ml|>

k)

for

each

ρ ρρρ∈ ∈∈∈

R(l

)p

art

itio

n(ρ ρρρ

,ρ ρρρ’,

ρ ρρρ”);

en

dfo

rl:

=l+

1;

setu

p-c

on

str

ain

ts(l

);g

lob

al-

op

tim

ize(l

);/*

extr

as

rep

art

itio

n(l

); *

/en

dw

hile

fin

al-

pla

cem

en

t(l)

;en

dp

roced

ure

Page 41: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

41

Ku

rt K

eu

tzer

Fir

st

Itera

tio

n

A. K

ah

ng

Page 42: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

42

Ku

rt K

eu

tzer

Seco

nd

Ite

rati

on

A. K

ah

ng

Page 43: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

43

Ku

rt K

eu

tzer

Th

ird

Ite

rati

on

A. K

ah

ng

Page 44: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

44

Ku

rt K

eu

tzer

Fo

urt

h Ite

rati

on

A. K

ah

ng

Page 45: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

45

Ku

rt K

eu

tzer

GO

RD

IAN

(q

uad

rati

c +

part

itio

nin

g)

Par

titi

on

and R

epla

ce

Init

ial

Pla

cem

ent

A. K

ah

ng

Page 46: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

46

Ku

rt K

eu

tzer

An

oth

er

Se

rie

s o

f G

ord

ian

(a)

Glo

ba

l p

lac

em

en

t w

ith

1 r

eg

ion

(b)

Glo

ba

l p

lac

em

en

t w

ith

4 r

eg

ion

(c)

Fin

al

pla

cem

en

ts

D. P

an

–U

of

Texas

Page 47: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Fin

al P

lacem

en

t

Page 48: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

48

Ku

rt K

eu

tzer

Fin

al P

lacem

en

t -

1

Earl

ier

ste

ps h

ave b

roken

do

wn

th

e p

rob

lem

in

to a

man

ag

eab

le

nu

mb

er

of

ob

jects

Tw

o a

pp

roach

es:

�F

inal p

lacem

en

t fo

r sta

nd

ard

cells/g

ate

arr

ay –

row

assig

nm

en

t

�F

inal p

lacem

en

t fo

r la

rge, ir

reg

ula

rly s

ized

macro

-blo

cks –

slicin

g –

loo

k o

ver

in “

Extr

a”

slid

es a

t th

e e

nd

Page 49: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Fin

al P

lacem

en

t –

Sta

nd

ard

Cell D

esig

ns

Th

is p

rocess co

nti

nu

es u

nti

l th

ere

are

o

nly

a

few

cells in

each

gro

up

( ≈ ≈≈≈

6 )

each

gro

up

h

as ≤ ≤≤≤

6cells

gro

up

: sm

allest

part

itio

n

As

sig

n

cells

in

each

g

rou

p c

lose t

og

eth

er

in

the s

am

e r

ow

or

nearl

y

in a

dja

cen

t ro

ws

A.

E.

Du

nlo

p, B

. W

. K

ern

igh

an

, A

pro

ced

ure

fo

r p

lacem

en

t o

f s

tan

dard

-cell V

LS

I cir

cu

its, IE

EE

Tra

ns. o

n C

AD

, V

ol. C

AD

-4,

Jan

, 1

985,

pp

. 92-

98

Page 50: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

50

Ku

rt K

eu

tzer

Sta

nd

ard

Cell L

ayo

ut

Page 51: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Fin

al P

lacem

en

t –

Cre

ati

ng

Ro

ws

11

11,2

1,2

1,2

1,2

22

2,3

2,3

2,3

2,3

33

3

3,4

3,4

3,4

3,4

44

44

5

55

5

5

5

4,5

4,5

a f

ou

r-ro

w

sta

nd

ard

cell

d

esig

n

Part

itio

nin

g o

f cir

cu

it in

to 32 g

rou

ps.

Each

g

rou

p is

eit

her

assig

ned

to

a sin

gle

ro

w o

r d

ivid

ed

in

to 2

ro

ws

Page 52: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Fin

al P

lacem

en

t –

Cre

ati

ng

Ro

ws

�P

art

itio

nin

g m

ust

be d

on

e b

read

th-f

irst

no

t d

ep

th f

irst

Cre

ati

ng

Ro

ws

C1

C2

C3

Ro

w 1

Ro

w 2

Ro

w 3

Ro

w 4

cells in

C1→ →→→

row

1

cells in

C3→ →→→

row

1

cells in

C2

C2

α ααα β βββ

α ααα+

β βββ=

1R

ow

1R

ow

2

Ch

oo

se α ααα

an

d β

β

β

β

pre

fera

bly

to

bala

nce r

ow

to

b

ala

nce r

ow

len

gth

(D

uri

ng

re-a

rran

gem

en

t )

Page 53: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

53

Ku

rt K

eu

tzer

Fin

al P

lacem

en

t

Earl

ier

ste

ps h

ave b

roken

do

wn

th

e p

rob

lem

in

to a

man

ag

eab

le

nu

mb

er

of

ob

jects

Tw

o a

pp

roach

es:

�F

inal p

lacem

en

t fo

r sta

nd

ard

cells –

row

assig

nm

en

t

�F

inal p

lacem

en

t fo

r la

rge, ir

reg

ula

rly s

ized

macro

-blo

cks –

slicin

g –

see E

xtr

as

Page 54: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Gen

era

tin

g F

inal P

lacem

en

t

Page 55: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Exam

ple

Fin

al P

lacem

en

t

Page 56: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Su

mm

ary

of

sta

tus o

n p

lacem

en

t

Mo

st

pla

ce a

nd

ro

ute

to

ols

use

a s

eri

es o

f ``

half

-tru

ths’’

reg

ard

ing

tim

ing

mo

de

lin

g a

nd

dela

y c

on

str

ain

ts

No

t u

nch

ara

cte

risti

call

y,

the G

ord

ian

ap

pro

ach

uses t

hre

e d

iffe

ren

t ap

pro

ac

hes

to a

ttack t

he

pro

ble

m -

eac

h a

pp

roach

makes a

nu

mb

er

of

dif

fere

nt

sim

pli

ficati

on

s

Cu

rren

t g

ate

-le

vel p

lacem

en

t to

ols

(e.g

. A

po

llo

) are

ab

le t

o p

lac

e a

nd

ro

ute

hu

nd

red

s o

f th

ou

san

ds � ���

mil

lio

ns o

f ce

lls

fla

t (w

ith

ou

t h

iera

rch

y)

Desp

ite

th

e l

ack

of

dir

ec

t co

rre

lati

on

be

tween

th

e in

tern

al

tim

ing

mo

de

l an

d t

he

actu

al

inte

gra

ted

cir

cu

it t

imin

g -

tim

ing

clo

su

re b

etw

een

syn

thesis

an

d

ph

ys

ical

desig

n is i

mp

rovin

g b

ut

sti

ll a

pro

ble

m

Pri

ncip

all

y d

ue t

o:

•B

ett

er

de

lay e

sti

ma

tio

n i

n s

yn

thesis

•B

ett

er

de

lay c

alc

ula

tio

n i

n p

hys

ical

desig

n

•A

uto

ma

ted

bu

ffer

insert

ion

in

ro

uti

ng

Page 57: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

57

Ku

rt K

eu

tzer

To

day’s

hig

h-p

erf

log

ical/p

hysic

al fl

ow

1)

op

tim

ize u

sin

g

esti

mate

d o

r

extr

acte

d

cap

acit

an

ces

2)

re-p

lace a

nd

re-

rou

te

3)i

f d

esig

n f

ails t

o

meet

co

nstr

ain

ts

du

e t

o p

oo

r

esti

mati

on

-re

peat

1 +

2-

netl

ist

Lib

rary

user

co

nstr

ain

ts

layo

ut

RC

extr

acti

on

dela

ym

od

el

gen

era

tor

rou

tin

g

tech

file

s

pla

cem

en

t

log

ico

pti

miz

ati

on

/ti

min

g v

eri

f

SD

Fcell/w

ire

dela

ys

Page 58: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

58

Ku

rt K

eu

tzer

To

p-d

ow

n p

rob

lem

s in

th

e f

low

netl

ist

Lib

rary

user

co

nstr

ain

ts

layo

ut

RC

extr

acti

on

dela

ym

od

el

gen

era

tor

rou

tin

g

tech

file

s

pla

cem

en

t

log

ico

pti

miz

ati

on

/ti

min

g v

eri

f

SD

Fcell/w

ire

dela

ys

init

ial ca

pacit

an

ce

esti

ma

tes i

nacc

ura

te

inab

ilit

y t

o t

ake t

op

-d

ow

n t

imin

g

co

nstr

ain

ts

inaccu

rate

in

tern

al

tim

ing

mo

del

Page 59: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

59

Ku

rt K

eu

tzer

Itera

tio

n p

rob

lem

s in

th

e f

low

netl

ist

Lib

rary

user

co

nstr

ain

ts

layo

ut

RC

extr

acti

on

dela

ym

od

el

gen

era

tor

rou

tin

g

tech

file

s

pla

cem

en

t

log

ico

pti

miz

ati

on

/ti

min

g v

eri

f

SD

Fcell/w

ire

dela

ys

up

da

ted

cap

acit

an

ces

cau

se s

ign

ific

an

t ch

an

ges i

n

op

tim

izati

on

lim

ited

-in

cre

men

tal

cap

ab

ilit

y

resu

ltin

g i

tera

tio

n m

ay

no

t b

rin

g c

loser

to

co

nverg

en

ce

Page 60: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Researc

h o

pp

ort

un

itie

s in

pla

cem

en

t

•B

ett

er

dela

y e

sti

mati

on

an

d m

od

elin

g in

syn

thesis

•B

ett

er

dela

y c

alc

ula

tio

n in

ph

ysic

al d

esig

n

•A

uto

mate

d r

esyn

thesis

du

rin

g p

lacem

en

t

•A

uto

mate

d s

izin

g a

nd

bu

ffer

insert

ion

in

ro

uti

ng

Page 61: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

61

Ku

rt K

eu

tzer

Inte

gra

tin

g S

yn

thesis

an

d P

lacem

en

t

resi

zing

buff

erin

g

clonin

gre

stru

cturi

ng

Sta

n C

how

Am

mocore

Andre

w B

. K

ahng U

CS

DM

ajid

Sarr

afz

adeh U

CLA

Page 62: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

62

Ku

rt K

eu

tzer

Oth

er

Ele

men

ts o

f In

du

str

ial F

low

Def

init

ion

s:•C

ell:

a c

ircu

it c

om

po

nen

t to

be

pla

ced

o

n t

he

chip

are

a.

In p

lace

men

t, t

he

fun

ctio

na

lity

of

the c

om

po

nen

t is

ig

no

red

.•N

et:

spec

ifyin

g a

su

bse

t o

f te

rmin

als

, t

o

con

nec

t se

vera

l ce

lls.

•Net

list

: a

set

of

net

s w

hic

h c

on

tain

s th

e co

nn

ecti

vit

y in

form

ati

on

of

the c

ircu

it.

Glo

ba

l P

lacem

en

t

Deta

il P

lacem

en

t

Clo

ck T

ree S

yn

thes

is

an

d R

ou

tin

g

Glo

ba

l R

ou

tin

g

Deta

il R

ou

tin

g

Po

wer/

Gro

un

d

Str

ipe

s, R

ing

s R

ou

tin

g

Extr

ac

tio

n a

nd

D

ela

y C

alc

. T

imin

g

Veri

fic

ati

on

IO P

ad

Pla

cem

en

t

A. K

ah

ng

Page 63: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

63

Ku

rt K

eu

tzer

Extr

as

•Wo

rked

ou

t exa

mp

le f

or

qu

ad

rati

c p

rog

ram

min

g –

D. P

an

, U

of

Texas

•Bri

ef

su

rve

y o

f ap

pro

ach

es

•Mo

re o

n q

uad

rati

c p

lace

men

t

•Usin

g s

lic

ing

to

han

dle

macro

-blo

cks

Page 64: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

64

Ku

rt K

eu

tzer

Cost

=(x

1−

100)2

+(x

1−

x2)2

+(x

2−

200)2

�x 1

Cost

=2(x

1−

100)+

2(x

1−

x2)

�x 2

Cost

=−

2(x

1−

x2

)+

2(x

2−

200)

sett

ing

the

par

tial der

ivat

ives

= 0

we

solv

e fo

r th

e m

inim

um

Cost

:

Ax

+ B

= 0

=

04

−2

−2

4

x1

x2

+−200

−400

= 0

2−1

−1

2

x1

x2

+−100

−200

x1=

400/3

x

2=

500/3

x2

x1

x=

100

x=

200

Toy

Exam

ple

:

D. P

an

Page 65: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

65

Ku

rt K

eu

tzer

settin

g th

e pa

rtia

l der

ivat

ives

= 0

we

solv

e fo

r th

e m

inim

um C

ost:

Ax

+ B

= 0

=

04

−2

−24

x 1 x 2+

−200

−400

= 0

2−1

−12

x 1 x 2+

−100

−200

x1=40

0/3

x2=

500/

3

x2

x1

x=

100

x=

200

Inte

rpre

tation o

f m

atr

ices A

and B

:

The d

iagonal valu

es A

[i,i] corr

esp

ond to t

he n

um

ber

of connections to x

i

The o

ff d

iagonal valu

es A

[i,j] are

-1 if obje

ct i is

connecte

d to o

bje

ct j, 0

oth

erw

ise

The v

alu

es B

[i] corr

espond to t

he s

um

of

the locations o

f fixed o

bje

cts

connecte

d to o

bje

ct i

Exam

ple

:

D. P

an

Page 66: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

66

Ku

rt K

eu

tzer

Tra

dit

ion

al A

pp

roach

es

•Q

uad

rati

c P

lacem

en

t

•S

imu

late

d A

nn

ealin

g

•B

i-P

art

itio

nin

g

•Q

uad

risecti

on

•F

orc

e D

irecte

d P

lacem

en

t

•H

yb

rid

Page 67: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Overv

iew

of G

ord

ian P

ackag

e

Pro

ced

ure

Go

rdia

nl:

=1;

glo

bal-

op

tim

ize(l

);

wh

ile(∃ ∃∃∃

|Ml|>

k)

for

each

ρ ρρρ∈ ∈∈∈

R(l

)p

art

itio

n(ρ ρρρ

,ρ ρρρ’,

ρ ρρρ”);

en

dfo

rl:

=l+

1;

setu

p-c

on

str

ain

ts(l

);g

lob

al-

op

tim

ize(l

);re

part

itio

n(l

);en

dw

hile

fin

al-

pla

cem

en

t(l)

;en

dp

roced

ure

GO

RD

IAN

wit

h r

ep

art

itio

nin

g p

roced

ure

Page 68: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Cost F

unction

TT

XX

Χ ΧΧΧd

Cx

+ +++= ===

)(

φ φφφ

YY

XX

Χ ΧΧΧY

dC

dC

yx

T yT

T xT

+ ++++ +++

+ +++= ===

),

(φ φφφ

uv

ξ ξξξ

1∑ ∑∑∑

Lv

Nv

v= ===

∈ ∈∈∈2

wφ φφφO

ve

rall

ob

jecti

ve

Page 69: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

�T

he c

en

ter

of

gra

vit

y c

on

str

ain

ts

At

level l, c

hip

is d

ivid

ed

in

to q

( ≤ ≤≤≤2

l )

reg

ion

s

Fo

r re

gio

n p

. th

e c

en

ter

co

ord

inate

s:

(up,

vp)

(Mp

: set

of

mo

du

les in

reg

ion

p)

Matr

ix f

orm

fo

r all r

eg

ion

s

Glo

bal P

lacem

ent and C

onstr

ain

ts

∑ ∑∑∑∑ ∑∑∑

∈ ∈∈∈∈ ∈∈∈

= ===

pp

Mu

up

uM

uu

Fu

xF

:s

con

stra

int

0

,)(

)(

∑ ∈ ∈∈∈= ===

= ===p

Mi

ii

pu

ll

FF

au

XA

If i

∈ ∈∈∈M

p

oth

erw

ise

Page 70: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

ρ ρρρ

Pro

ble

m F

orm

ula

tion

D

E

F

AB C

),

('

'ρ ρρρ

vu

= ===

M MMML LLLL LLLM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

M MMMM MMM

*0

*0

*0

00

0*

**

')

(

ρ ρρρρ ρρρl

A

GF

ED

CB

A

�L

inearl

y c

on

str

ain

ed

qu

ad

rati

c p

rog

ram

min

g p

rob

lem

}s.

t.)

({

min

:L

QP

)(

)(

ll

TT

Rx

uX

AX

dX

CX

xm

= ===+ +++

= ===Φ ΦΦΦ

∈ ∈∈∈

ρ ρρρ)

,(

ρ ρρρv

u

Page 71: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Solu

tion M

eth

od

[ [[[] ]]]

[ [[[] ]]]

0

11

11

)(

0

,

xZ

Xu

DX

I

BD

X

uD

BX

DX

uXX

BD

BD

A

i

id

id

qm

qq

qm

q

+ +++= ===

+ +++

− −−−= ===

+ +++− −−−

= ===

= ===

= ===

− −−−− −−−

− −−−− −−−

− −−−× ×××

× ×××× ×××

Xd

dep

en

den

t vari

ab

les

Xi

ind

ep

en

den

t vari

ab

les

un

co

nstr

ain

ed

qu

ad

rati

c p

rog

ram

min

g p

rob

lem

)(C

})

({

min

:U

QP

0

Td

CX

XC

CZ

XZ

Xx

iT

TT i

iR

xq

mi

+ +++= ===

+ +++= ===

− −−−∈ ∈∈∈

ψ ψψψ

So

lved

by c

on

jug

ate

--g

rad

ien

t m

eth

od

Page 72: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

p

Term

ina

l P

ropag

atio

n

L1

L2

R1

R2

Pre

fer

to h

ave

all o

f th

em

in

R1

RL

1

L2

net

s

�W

e s

ho

uld

use t

he f

act

that

s is in

L1!

Fic

titi

ou

s c

ell

o

f n

et

s

L1

L2

R1

R2

As

su

min

g

locate

d a

t cen

ter

L1

L2

R1

R2

pL

1

L2

R1

R2

p

hig

her

co

st

low

er

co

st

p w

ill

sta

y i

n R

1fo

r th

e r

est

of

part

itio

nin

g

Page 73: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

73

Ku

rt K

eu

tzer

Macro

Pla

cem

en

t b

y S

licin

g

Page 74: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Co

nstr

ain

ing

Pla

cem

en

t o

f M

acro

s

Insert

yo

ur

log

ic h

ere

Glo

bal o

pti

miz

ati

on

an

d p

art

itio

nin

g a

ssig

ns <

=k c

ell

s t

o e

ach

ph

ysic

al

reg

ion

Th

ere

are

dif

fere

nt

ways o

f p

lacin

g c

ell

s in

each

reg

ion

Wan

t to

ch

oo

se p

lacem

en

ts t

hat

min

imiz

e t

ota

l ch

ip a

rea

Page 75: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Macro

-blo

cks:

Exh

au

sti

ve S

licin

g

Op

tim

izati

on

L. van

Gin

nekin

, R

. H

. O

tten

, O

pti

mal S

licin

g o

f P

oin

t P

lacem

en

ts, E

DA

C,

1990, p

p. 322-3

26

Page 76: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Sli

cin

g v

s.

No

n-S

lic

ing

Flo

orp

lan

s

Slicin

g F

loo

rpla

n(s

lic

ing

str

uc

ture

): A

recta

ng

le d

issec

tio

n w

hic

h c

an

be

ob

tain

ed

by r

ec

urs

ively

dis

sec

tin

g t

he t

he b

ase

recta

ng

le in

to

sm

all

er

rec

tan

gle

s b

y v

ert

ical

an

d h

ori

zo

nta

l sli

cin

g l

ines

.

Slicin

g s

tru

ctu

res a

re g

oo

d f

or

rou

tin

g

Sli

cing F

loorp

lan

Non-S

lici

ng F

loorp

lan(w

hee

l)

Page 77: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Slicin

g T

ree

A

BC

D

E F G

D

A

C

B

GF

E

H

VH

HH

V

Slicin

g s

tru

ctu

re is d

escri

bed

by a

slicin

g t

ree

Page 78: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Th

e S

hap

e A

lgo

rith

m

Inp

ut:

S

licin

g T

ree

Sh

ap

e C

on

str

ain

ts f

or

mo

du

les

Co

st

Fu

ncti

on

(n

on

-decre

asin

g in

w, h

)

Ou

tpu

t:S

hap

es/Im

ple

men

tati

on

fo

r each

mo

du

le

Alg

ori

thm

•C

om

po

se s

hap

e c

on

str

ain

ts b

ott

om

-up

in

th

e s

licin

g t

ree

•A

pp

ly c

ost

fun

cti

on

to

co

mp

ute

bo

un

dary

po

int

on

sh

ap

e

co

nstr

ain

t o

f b

ase b

lock (

roo

t)

•P

rop

ag

ate

bo

un

dary

po

int

top

-do

wn

in

slicin

g t

ree t

o o

bta

in

imp

lem

en

tati

on

fo

r each

mo

du

le

Page 79: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Sh

ap

e C

on

str

ain

ts

Giv

en

a r

ec

tan

gu

lar

mo

du

le,

the s

hap

e c

on

str

ain

t re

lati

on

Ris

th

e s

et

of

y-x

pair

s s

o t

ha

t a

recta

ng

le w

ith

wid

th e

qu

al

to x

an

d h

eig

ht

eq

ua

l to

y c

on

tain

s a

t le

ast

a s

hap

e/o

rien

tati

on

realizati

on

of

the m

od

ule

.

3

1

3

1

12

34

12

34

2 134

2 134

Page 80: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

80

Ku

rt K

eu

tzer

Co

mp

osin

g S

hap

e C

on

str

ain

ts

3 b

y 1

4 b

y 1

1

2

3

4 5

6

7

5 4 3 2 1

1

2

3

4 5

6

7

5 4 3 2 1

1

2

3

4 5

6

7

7 6 5 4 3 2 1

7 b

y 1

Page 81: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Slicin

g T

ree

A

BC

D

E F G

D

A

C

B

GF

E

H

VH

HH

V

Tra

vers

e t

ree b

ott

om

-up

deri

vin

g c

om

po

sed

sh

ap

e f

un

cti

on

s

Page 82: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Th

e S

hap

e A

lgo

rith

m

Inp

ut:

S

licin

g T

ree

Sh

ap

e C

on

str

ain

ts f

or

mo

du

les

Co

st

Fu

ncti

on

(n

on

-decre

asin

g in

w, h

)

Ou

tpu

t:S

hap

es/Im

ple

men

tati

on

fo

r each

mo

du

le

Alg

ori

thm

•C

om

po

se s

hap

e c

on

str

ain

ts b

ott

om

-up

in

th

e s

licin

g t

ree

•A

pp

ly c

ost

fun

cti

on

to

co

mp

ute

bo

un

dary

po

int

on

sh

ap

e

co

nstr

ain

t o

f b

ase b

lock (

roo

t)

•P

rop

ag

ate

bo

un

dary

po

int

top

-do

wn

in

slicin

g t

ree t

o o

bta

in

imp

lem

en

tati

on

fo

r each

mo

du

le

Page 83: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Co

nstr

ain

ing

Pla

cem

en

t o

f M

acro

s

Insert

yo

ur

log

ic h

ere

30 X

50

At

top

level can

have c

om

ple

x s

hap

e f

un

cti

on

s

Ap

ply

a c

ost

fun

cti

on

an

d s

ele

ct

low

est

sco

re p

oin

t, e

.g.

�co

st(

w,h

) =

wh

�C

ost(

w,h

) =

2(w

+h

)

Page 84: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Slicin

g T

ree

D

A

C

B

GF

E

H

VH

HH

V30 X

50

Page 85: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Th

e S

hap

e A

lgo

rith

m

Inp

ut:

S

licin

g T

ree

Sh

ap

e C

on

str

ain

ts f

or

mo

du

les

Co

st

Fu

ncti

on

(n

on

-decre

asin

g in

w, h

)

Ou

tpu

t:S

hap

es/Im

ple

men

tati

on

fo

r each

mo

du

le

Alg

ori

thm

•C

om

po

se s

hap

e c

on

str

ain

ts b

ott

om

-up

in

th

e s

licin

g t

ree

•A

pp

ly c

ost

fun

cti

on

to

co

mp

ute

bo

un

dary

po

int

on

sh

ap

e

co

nstr

ain

t o

f b

ase b

lock (

roo

t)

•P

rop

ag

ate

bo

un

dary

po

int

top

-do

wn

in

slicin

g t

ree t

o o

bta

in

imp

lem

en

tati

on

fo

r each

mo

du

le

Page 86: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Slicin

g T

ree

A

BC

D

E F G

D

A

C

B

GF

E

H

VH

HH

V

Pro

pag

ate

op

tim

al ch

oic

es t

op

-do

wn

to

all t

he leaves

Page 87: The Physical Placement Problem in Integrated Circuitskeutzer/classes/244fa... · 2005-10-05 · 2 Schematic Entry Design Flow Kurt Keutzer schematic editor netlist Library physical

Min

-Cut

Based P

lace

me

nt

(Cont’d

)

A

BC

D

E F G