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The PDM-blockThe PDM-block
M. Casolino on behalf of JEM-EUSO collaborationEUSO-BALLOON Phase A review
2nd February 2012, CNES, Toulouse
PDM Block and the instrumentPDM Block and the instrument
22
• The PDM, which stands for Photo Detector Module, consists in 36 MAPMTs (grouped in 9 Elementary cells and arranged in matrix of 6x6) equipped with UV filters and their associated electronic chain. The PDM has a well defined mechanical structure that welcome all these elements
What is the PDM unit ?What is the PDM unit ?
33
• Functional RequirementsIt is the core element to detect the UV light coming from the optics.
• Size167 mm x 167 mm x 200 mm (TBC) corresponding to the mechanical structure, the MAPMT and electronic (EC_dynode, Ec_anode, EC_HV, EC_ASIC, PDM board, HV box (LVPS + switches))
• Mass The total weight is given by the mechanical structure (0,730 kg)+ electronic (~ 1,7 kg) + MAPMT (1,125 Kg) and HV box (300 g TBC) + PDM Board (145 g) + LVPS (150 g). All those numbers are TBC.
• Power budgetAbout 300 mW for one EC without MAPMT. Therefore 2.7 W for the 9 EC units. HV box is about 800 mW total. The power consumption of the PDM board (1.8 W) and the switches should be added. All those numbers are (TBC).
Technical specificationsTechnical specifications
44
Mechanical StructureMechanical Structure
Mechanics PrototypeMechanics Prototype
Prototypes of the PDM structure already manufactured by the INFN- National Laboratories in Frascati, Italy.
• The PhotoMultiplier (MAPMT) and the Filters• The ASIC (ASIC)• The Elementary Cell (EC)• The High Voltage Power
Supply (HVPS) and Switches (SW)• The PDM Board (PDMB)
PDM unit descriptionPDM unit description
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• 9 elements each with 4MAPMTs
• for a total of 36 MAPMTS
EC boards (P. Barrillon)EC boards (P. Barrillon)
• 6 elements each with 6ASICs on each• Total of 36 ASICs • 6 connectors to PDM-FPGA board
EC ASIC board (P. Barrillon)EC ASIC board (P. Barrillon)
ASICASICASIC
68 pins
ASIC
68 pins
68 pins
ASIC
68 pins
68 pins
ASIC
68 pins
At least120 mm needed.
~40 mm
~ 60 mm
~ 20 mm
~ 150 mm
120 pins
• 1 board in the PDM• Interfaces to 6ASIC boards• Interfaces to CCB board• Interface to LV power supply
PDM FPGA boardPDM FPGA board
Functional Requirements,• first-level trigger algorithm,
and the interface with the EC board and CCB board.
• Housekeeping and other operation-related functions are also controlled by the FPGA chips.
• Clocks at 40MHz and 400kHz are received from the CCB and distributed to EC boards.
• From the EC boards, the data transmission is running at the rate of 400kHz. To the CCB, the data transmission rate is at a lower level, 7Hz (TBC).
The PDM Board (PDMB)The PDM Board (PDMB)
LVPS and switches, HV box (P. Gorodetzky)LVPS and switches, HV box (P. Gorodetzky)
Risk analysisRisk analysis
1313
• EC boards not available in due time• Mechanical integration problems• Delay in PDM assembly/integration• Electronics integration problems• Common noise• Grounding loops• Failure of 1 component (EC, HV, PDM, ASIC after
integration…)• Maquette and electrical protype needed• Spares need to be produced. • Help will come from TA-EUSO experiment which
will produce a prototype
GANT chart and development planGANT chart and development plan
Special Thanks to P. Barrillon for the layout.