The Map Method Boolean expressions may be simplified by algebraic means as discussed in Previous lecture However, this procedure of minimization is awkward because it lacks specific rules to predict each succeeding step in the manipulative process. The map method provides a simple straightforward procedure for minimizing Boolean functions. This method may be regarded as a pictorial form of a truth table. The map method is also known as the Karnaugh map or K-map.

The map is a diagram made up of squares, with each square representing one minterm of the function. Since any Boolean function can be expressed as a sum of minterms, it follows that a Boolean function is recognized graphically in the map from the area enclosed by those squares whose minterms are included in the function.

Two-Variable Map

m1+ m2+m3

=¬xy+x¬y+xy=x+y

Fig 6.1 Two-Variable Map

Fig 6.2 Representation of Functions in the Map

Three-Variable Map

m5+ m7 = x¬yz + xyz = xz(¬y+y) = xz

Fig 6.3 Three-Variable Map

Example-1Simplify the Boolean function

There are cases where two squares in the map are considered to be adjacent even though they do not touch each other. In Fig. 6-3, mo is adjacent to m2 and m4 is

adjacent to m6 because the minterms differ by one variable. This can be readily

verified algebraically:

Fig 6.4 Map for Example-1:

Example-2

Simplify the Boolean function

Fig 6.5 Map for Example-2:

One square represents one minterm, giving a term of three literals. Two adjacent squares represent a term of two literals.Four adjacent squares represent a term of one literal.Eight adjacent squares encompass the entire map and produce a function that is always equal to 1.

Example-3Simplify the Boolean function

Fig 6.6 Map for Example-3:

Given the Boolean function

Example-4

(a) express it in sum of minterms(b) and find the minimal sum of products expression.

Fig 6.7 Map for Example-3:

The sum of products expression as originally given has too many terms. It can be simplified as shown in the map to an expression with only two terms:

Four-Variable MapThe map for Boolean functions of four binary variables is shown in Fig. 6-8. In (a) are lis the 16 minterms and the squares assigned to each. In (b) the map is redrawn to show -the re tionship with the four variables. The rows and columns are numbered in a Gray code sequence with only one

digit changing value between two adjacent rows or columns.

One square represents one minterm, giving a term of four literals. Two adjacent squares represent a term of three literals.Four adjacent squares represent a term of two literals. Eight adjacent squares represent a term of one literal. Sixteen adjacent squares represent the function equal to 1.Fig 6.8 Three-Variable Map

Simplify the Boolean functionExample-5

Fig 6.9 Map for Example-5:

Simplify the Boolean functionExample-6

Fig 6.10 Map for Example-6:

Prime Implication

Five Variable map

Product of sums simplification

NAND AND NOR IMPLEMENTATION

08/07/04

Combinational CircuitsA combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept signals from the inputs and generate signals to the outputs. This process transforms binary information from the given input data to a required output data

Analysis procedure

1. Determine the number of input variables in the circuit. For n inputs, form the 2n possible input combinations and list the binary numbers from 0 to 2" - 1 in a table.2. Label the outputs of selected gates with arbitrary symbols.3. Obtain the truth table for the outputs of those gates that are a function of the input variables only.4. Proceed to obtain the truth table for the outputs of those gates that are a function of previously defined values until the columns for all outputs are determined.

1

17

Design Procedure1. From the specifications of the circuit, determine the required number of inputs and out puts and assign a symbol to each.2. Derive the truth table that defines the required relationship between inputs and outputs.3. Obtain the simplified Boolean functions for each output as a function of the input variables. 4. Draw the logic diagram and verify the correctness of the design.

Half adder

Full- adder

Binary Adder

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain. Figure shows the interconnection of four full adder (FA) circuits to provide a 4-bit binary ripple carry adder.To demonstrate with a specific example, consider the two binary numbers, A = 1011 and B = 0011. Their sum S = 1110 is formed with the four-bit adder as follows:

The addition of two binary numbers in parallel implies that all the bits of the augend and addend are available for computation at the same time. As in any combinational circuit, the signal must propagate through the gates before the correct output sum is available in the output terminals. The total propagation time is equal to the propagation delay of a typical gate times the number of gate levels in the circuit. The longest propagation delay time in an adder is the time it takes the carry to propagate through the full adders.

Carry Propagation

Consider the circuit of the full adder shown in Fig. If we define two new binary variables

t

the output sum and carry can be expressed as

G

G; is called a carry generate and it produces a carry of 1 when both A; and B; are

1, regardless of the input carry Ci. Pi is

called a carry propagate because it is the term associated with propagation of the

carry from Ci, to Ci+1 .

We now write the Boolean functions for the carry outputs of each stage and substitute each C; its value from the previous equations:

C=K+Z8Z4+Z8Z2

When C=1 , it necessary to add

0110 to the binary sum and

provide an output carry for the

next stage .

A BCD adder that adds two

BCD digits and produces a

sum digit in BCD is shown in

fig. The two decimal digits ,

together with the input carry ,

are first added in the top 4-bit

adder to produce the binary

sum . When the output carry is

equal to zero , nothing is added

to the binary sum . When it is

equal to one , binary 0110 is

added is added to the binary

sum through the bottom 4-bit

adder

BCD ADDER

The addition of two n-digit unsigned BCD numbers follows the same procedure. Consider the addition of 184 + 576 = 760 in BCD:

T

Binary Multiplier

Decoder

S

Decoder applications• Microprocessor memory systems

– selecting different banks of

memory

• Microprocessor input/output systems

– selecting different devices

• Microprocessor instruction decoding

– enabling different functional

units

• Memory chips

– enabling different rows of

memory depending on address

• Lots of other applications

Combinational Logic Implementation

What about Encoder?

Multiplexers

Boolean Function Implementation

Sequential circuitsThe digital circuits considered thus far have been combinational, where the outputs are entirely dependent on the current inputs. Although every digital system is likely to have combinational circuits, most systems encountered in practice also include storage elements, which require that the system be described in terms of sequential logic

A synchronous sequential circuits:

An asynchronous sequential circuits

LATCHESThe most basic types of flip-flops operate with signal levels and are referred to as latches. The latches introduced here are the basic circuits from which all flip-flops are constructed.

SR Latch

The operation of the basic SR latch can be modified by providing an additional control input that determines when the state of the latch can be changed. An SR latch with a control input is shown in Fig. It consists of the basic SR latch and two additional NAND gates. The control input C acts as an enable signal for the other two inputs. The output of the NAND gates stay at the logic 1 level as long as the control input remains at 0. This is the quiescent condition for the SR latch. When the control input goes to 1, information from the S or R input is allowed to affect the SR latch. The set state is reached with S = 1, R = 0, and C = 1. To change to the reset state, the inputs must be S = 0, R = 1, and C = 1. In either case, when C returns to 0 , the circuit remains in its current state. Control input disables the circuit by applying 0 to C, so that the state of the output does not change regardless of the values of S and R. Moreover when C=1 and both the S and R inputs are equal to 0, the state of the circuit does not change.

D LatchOne way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs Sand R are never equal to 1 at the same time. This is done in the D latch shown in Fig. This latch has only two inputs: D (data) and C (control). The D input goes directly to the S input and its complement is applied to the R input. As long as the control input is at 0, the cross coupled SR latch has both inputs at the 1 level and the circuit cannot change state regardless of the value of D. The D input is sampled when C = 1. If D = I, the Q output goes to 1, placing the circuit in the set state. If D = 0, output Q goes to 0, placing the circuit in the reset state.

FLIP-FLOPSThe state of a latch or flip-flop is switched by a change in the control input. This momentary

change is called a trigger and the transition it causes is said to trigger the flip- flop. The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the pulse goes to the logic 1 level. As long as the pulse input remains in this level, any changes in the data input will change the output and the state of the latch.

Consequently, the inputs of the flip-flops are derived in part from the outputs of the same and other flip-flops. When latches are used for the storage elements, a serious difficulty arises. The state transitions of the latches start as soon as the clock pulse changes to the logic 1 level. The new state of a latch appears at the output while the pulse is still active. This output is connected to the inputs of the through the combinational circuit.

Edge Triggered D Flip-FlopThe construction of a D flip-flop with two D latches and an inverter is shown in Fig. The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the negative-edge of the controlling clock (designated as CLK). When the clock is 0, the output of the inverter is l. The slave latch is enabled and its output Q is equal to the master output Y The master latch is disabled because CLK = 0. When the input pulse changes to the logic I level, the data from the external D input is transferred to the master.

JK Flip-Flop

When J = 1 and K = 0, D = Q' + Q = 1, so the next clock edge sets the output to l. When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0. When both J = K = 1, D = Q', the next clock edge complements the output.When both J = K = 0, D = Q, the clock edge leaves the output unchanged.

The T Flip-Flop

W

The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip flop when inputs J and K are tied together. This is shown in Fig.When T = 0 (J = K = 0) a clock edge does not change the output. When T = 1 (J = K = 1) a clock edge complements the output. The complementing flip-flop is useful for designing binary counters.The Tflip-flop can be constructed with a D flip-flop and an exclusive-OR gate as shown in Fig. The expression for the D input is