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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 2, JUNE 2007 1
The Impact of Drift Implant and Layout Parameterson ESD Robustness for On-Chip ESD Protection
Devices in 40-V CMOS Technology
1
2
3
Wei-Jen Chang, Student Member, IEEE, and Ming-Dou Ker, Senior Member, IEEE4
Abstract—The dependences of drift implant and layout pa-5rameters on electrostatic discharge (ESD) robustness in a 40-V6CMOS process have been investigated in silicon chips. From the7experimental results, the high-voltage (HV) MOSFETs without8drift implant in the drain region have better transmission line9pulsing (TLP)-measured secondary breakdown current (It2) and10ESD robustness than those with drift implant in the drain region.11Furthermore, the It2 and ESD level of HV MOSFETs can be in-12creased as the layout spacing from the drain diffusion to polygate13is increased. It was also demonstrated that a specific test structure14of HV n-type silicon-controlled rectifier (HVNSCR) embedded15into HV NMOS without N-drift implant in the drain region has the16excellent TLP-measured It2 and ESD robustness. Moreover, due17to the different current distributions in HV NMOS and HVNSCR,18the dependences of the TLP-measured It2 and human-body-model19ESD levels on the spacing from the drain diffusion to polygate are20different.21
Index Terms—Electrostatic discharge (ESD), high-voltage22n-type SCR (HVNSCR), human body model (HBM), secondary23breakdown current (It2), transmission line pulsing (TLP).24
I. INTRODUCTION25
H IGH-VOLTAGE (HV) CMOS process has been widely26
used in liquid-crystal-display driver circuits, telecommu-27
nication, power switch, motor control systems, etc., [1]. In28
the smart-power technology, HV MOSFET, silicon-controlled29
rectifier (SCR) device, or bipolar junction transistor (BJT)30
was used as on-chip electrostatic discharge (ESD) protection31
devices [2]–[9]. Some ESD protection designs used the lateral32
or vertical bipolar transistors as ESD protection devices in33
smart power technology [7], [8]. However, fabrication cost and34
process complexity are increased by adding bipolar modules35
into the HV CMOS process. The HV MOSFET was often used36
as the ESD protection device because it can work as both of37
output driver and ESD protection device simultaneously in the38
HV CMOS ICs. With an ultrahigh operating voltage, the ESD39
robustness of HV MOSFET is quite weaker than that of low-40
voltage MOSFET [2]–[9]. To increase ESD robustness, the41
Manuscript received December 1, 2006; revised April 4, 2007. W.-J. Changwas supported by the MediaTek Fellowship, Hsinchu, Taiwan, R.O.C.
The authors are with the Nanoelectronics and Gigascale Systems LaboratoryInstitute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan 300,R.O.C. (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TDMR.2007.901185
conventional design with large device dimension still suffers 42
the nonuniform current distribution among the device. The HV 43
NMOS has the extremely strong snapback phenomenon during 44
ESD stress, which often results in nonuniform turn-on variation 45
among the multifingers of HV NMOS [10]. To overcome the 46
problem of nonuniform turn-on phenomenon, the gate-coupling 47
technique was applied to the HV NMOS [3], [4]. However, 48
the gate of HV NMOS must be in series with a large resistor, 49
which occupies a large layout area. Hence, how to improve the 50
ESD robustness of HV NMOS with a reasonable silicon area is 51
indeed an important reliability issue in HV CMOS technology. 52
In this paper, ESD robustness of MOSFETs in a 40-V CMOS 53
process is investigated with or without drift implant. In addi- 54
tion, the layout spacing from the drain diffusion to polygate is 55
split to find its dependence on ESD robustness [11]. To improve 56
ESD robustness of HV NMOS in a limit layout area, a specific 57
structure of HV n-type SCR (HVNSCR) can be built in the HV 58
NMOS by replacing part of the drain region with P+ diffusion. 59
ESD robustness of HVNSCR is also verified with or without 60
the N-drift implant under different layout spacings from the 61
drain region to polygate. All test chips have been fabricated in a 62
0.35-µm 40-V CMOS technology. 63
II. DEVICE STRUCTURES IN 40-V CMOS PROCESS 64
To integrate the HV devices while maintaining the charac- 65
teristics of the standard 0.35-µm low-voltage CMOS process 66
without changing all of the design rules and device parame- 67
ters, the device structures of HV MOSFET can be achieved 68
by adding several additional mask layers in the standard 69
0.35-µm CMOS technology. The additional mask layers are HV 70
N-well, HV P-well, N-drift or P-drift, N-grade or P-grade, and 71
N-field or P-field. The HV N-well and HV P-well in the HV 72
region are complementary layers which are fabricated on the 73
same P-substrate. The lightly doped N-drift (P-drift), N-grade 74
(P-grade), and N-field (P-field) implants are required for HV 75
MOSFETs to sustain the HV (40 V) during normal operating 76
conditions in 0.35-µm 40-V CMOS process. 77
In the given 0.35-µm 40-V CMOS process, the device struc- 78
tures in the test chip can be classified as follows: 1) HV NMOS 79
with or without N-drift implant in the drain region, 2) HV 80
PMOS with or without P-drift implant in the drain region, and 81
3) HV n-type SCR (HVNSCR) embedded into HV NMOS with 82
or without N-drift implant in the drain region. 83
1530-4388/$25.00 © 2007 IEEE
2 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 2, JUNE 2007
Fig. 1. Cross-sectional views of HV NMOS (a) with and (b) withoutN-drift implant in the drain region. The spacing (D) from the drain diffusion topolygate is a layout parameter to be investigated in the test chip.
A. HV NMOS With or Without N-Drift Implant84
The device cross-sectional views of HV NMOS with or85
without N-drift implant in the given 0.35-µm 40-V CMOS86
process are shown in Fig. 1(a) and (b), respectively. The HV87
NMOS is fabricated in the HV P-well, as shown in Fig. 1(a),88
where the P-field implant is used as isolation ring to isolate89
the device from the other. The N-grade implant is used in90
increasing the breakdown voltage of the drain region in the HV91
NMOS. Moreover, the HV NMOS has lightly doped N-drift92
implant below the field oxide in the drain region, and utilizes the93
field oxide between the gate and the drain contact to minimize94
the peak electric field around the corner of the drain region,95
which can avoid the hot carrier effect in the N-channel. The96
device structure of HV NMOS without N-drift implant was also97
fabricated, as shown in Fig. 1(b), where the N-drift in the drain98
region was removed.99
The trigger voltage of the HV NMOS device is determined100
by the drain avalanche breakdown voltage of the N-grade/HV101
P-well junction. While the overstress voltage reaches the break-102
down voltage of N-grade/HV P-well junction, the parasitic lat-103
eral n-p-n BJT in HV NMOS will be triggered on to discharge104
ESD current.105
B. HV PMOS With or Without P-Drift Implant106
The device cross-sectional views of HV PMOS with or107
without P-drift implant in the given 0.35-µm 40-V CMOS108
process are shown in Fig. 2(a) and (b), respectively. The HV109
PMOS is fabricated in the HV N-well, as shown in Fig. 2(a),110
where the purpose of N-field implant is the same as the P-field111
implant used in HV NMOS to isolate device from the other. The112
Fig. 2. Cross-sectional views of HV PMOS (a) with and (b) withoutP-drift implant in the drain region. The spacing (D) from the drain diffusionto polygate is a layout parameter to be investigated in the test chip.
P-grade implant in the drain region is also used in increasing 113
its breakdown voltage for HV application. The lightly doped 114
P-drift implant below the field oxide is also used in avoiding the 115
hot carrier effect in the P-channel. The device structure of HV 116
PMOS without P-drift implant was also fabricated, as shown in 117
Fig. 2(b), where the P-drift in the drain region was removed. 118
The trigger voltage of the HV PMOS device is determined 119
by the drain avalanche breakdown voltage of the P-grade/HV 120
N-well junction. While the overstress voltage reaches the break- 121
down voltage of P-grade/HV N-well junction, the parasitic 122
lateral p-n-p BJT in HV PMOS will be triggered on to discharge 123
ESD current. 124
C. HVNSCR With or Without N-Drift Implant 125
It has been well known that SCR has a good ESD protec- 126
tion capability. Hence, to improve the ESD robustness of HV 127
NMOS, the part of drain region in HV NMOS was replaced 128
by P+ diffusion to form an SCR structure in the device, where 129
the P+ diffusion is conjunction with N+ diffusion in the drain 130
region. The device cross-sectional views of HVNSCR with or 131
without N-drift implant in the given 0.35-µm 40-V CMOS 132
process are shown in Fig. 3(a) and (b), respectively. The SCR 133
path in the HV NMOS was composed by P+ diffusion in the 134
drain region, N-grade, HV P-well, N+ diffusion in the source 135
region. Here, no extra layout area is needed to realize this 136
HVNSCR structure in HV NMOS. 137
The HVNSCR device is composed of a lateral n-p-n BJT and 138
a vertical p-n-p BJT to form a two-terminal/four-layer PNPN 139
(P+/N-grade/HV P-well/N+) structure. The trigger voltage of 140
CHANG AND KER: IMPACT OF DRIFT IMPLANT AND LAYOUT PARAMETERS ON ESD ROBUSTNESS 3
Fig. 3. Cross-sectional views of HVNSCR (a) with and (b) without N-driftimplant in the drain region. The spacing (D) from the drain diffusion topolygate is a layout parameter to be investigated in the test chip.
Fig. 4. Equivalent circuit of the HVNSCR embedded into HV GGNMOS.
the HVNSCR device is the same as that of the HV NMOS,141
which is determined by the drain avalanche breakdown volt-142
age of the N-grade/HV P-well junction. While the overstress143
voltage reaches the breakdown voltage of N-grade/HV P-well144
junction, the HV NMOS will be first triggered on by the ESD145
transient pulse, and then, the embedded HVNSCR will be146
triggered on to discharge ESD current.147
The equivalent circuit of the HVNSCR device embedded into148
HV NMOS is shown in Fig. 4. When the magnitude of the ap-149
plied voltage is greater than the drain breakdown voltage of HV150
NMOS, the hole and electron currents will be generated through151
the avalanche breakdown mechanism. The hole current will152
flow through the HV P-well to P+ diffusion connected to the P-153
field ring of HV NMOS, which will increase the voltage level154
of the HV P-well. As long as the voltage drop across the HV155
P-well resistor (RHVP-well) is greater than the cut-in voltage of156
lateral n-p-n BJT, the lateral n-p-n BJT will be triggered on to157
keep HV NMOS into its breakdown region. While the lateral 158
n-p-n BJT is turned on, the electron current will be injected 159
through the N-grade into N+ diffusion in the drain of HV 160
NMOS to lower the voltage level of N-grade. As the injected 161
electron current is larger than some critical value, the voltage 162
drop across the N-grade resistor (RN-grade) will be greater 163
than the cut-in voltage of the vertical p-n-p BJT. The vertical 164
p-n-p BJT will be turned on to inject the hole current through 165
the HV P-well into P+ diffusion to further bias the lateral n-p-n 166
BJT. Such positive feedback regeneration physical mechanism 167
[12] will initiate the latching action in the HVNSCR. Finally, 168
the HVNSCR will be successfully triggered into its latching 169
state by the positive-feedback regenerative mechanism [12]. 170
Once the HVNSCR is triggered on, the required holding current 171
to keep the n-p-n and p-n-p BJTs on can be generated through 172
the positive-feedback regenerative mechanism of latchup with- 173
out involving the avalanche breakdown mechanism again. 174
III. EXPERIMENTAL RESULTS AND DISCUSSION 175
A. Transmission Line Pulsing (TLP)-Measured 176
I–V Characteristics 177
To simulate the human-body-model (HBM) [13] ESD event, 178
the TLP generator [14] is designed to generate the stable and 179
consistent pulses of very high current in a very short period 180
of time. To investigate the device behavior during HBM ESD 181
stress, the TLP with a pulsewidth of 100 ns and a rise time 182
of 10 ns has been widely used in measuring the secondary 183
breakdown current (It2) of ESD devices. In the test chip, the 184
device dimension (W/L) of HV NMOS was 200 µm/3 µm and 185
the device dimension (W/L) of HV PMOS was 200 µm/4 µm, 186
where the minimum device lengths (L) of HV NMOS and HV 187
PMOS are 3 and 4 µm, respectively, in the given 0.35-µm 40-V 188
CMOS process. The device dimension (W/L) of HVNSCR is 189
also kept the same as that of HV NMOS. Generally, the ESD 190
robustness is highly dependent on the ESD current discharging 191
path among HV MOSFETs. In HV MOSFETs, the location of 192
ESD damage is usually occurred at the drain region. Therefore, 193
in this test chip, the drift implant in the drain region and the 194
layout spacing (D) from the drain diffusion to polygate were 195
split to see its impact on ESD performance. 196
The TLP-measured I–V curves of HV gate-grounded NMOS 197
(GGNMOS) with or without N-drift implant in the drain region 198
are shown in Fig. 5, where the layout spacing from the drain 199
diffusion to polygate (D, as shown in Fig. 1) is split to find 200
the dependence on TLP-measured It2. The breakdown voltage 201
of HV GGNMOS with or without N-drift implant is about 202
70 ∼ 75 V, which is higher than the operation voltage of 40 V. 203
When the parasitic n-p-n BJT in HV GGNMOS is turned on, 204
it will snap back with a low holding voltage. Comparing to 205
other HV CMOS processes with deeper N-well and n+ buried 206
layer [15], no double-snapback characteristic was found in 207
the TLP-measured I–V curves of HV GGNMOS in the given 208
0.35-µm 40-V CMOS process with the shallower N-grade im- 209
plant. The double-snapback characteristic occurs while the ESD 210
current path changes from vertical direction (deeper region) to 211
lateral direction (shallower region) [7], [15]. However, the ESD 212
4 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 2, JUNE 2007
Fig. 5. TLP-measured I–V curves of HV GGNMOS (a) with and (b) withoutN-drift implant in the drain region under different spacings D.
current flows only in the lateral direction due to the shallower213
N-grade implant.214
In Fig. 5(a), with N-drift implant in the drain region, the TLP-215
measured It2 of HV GGNMOS are 1.1, 1.5, and 1.7 A for the216
spacing D of 5.5, 7.5, and 9.5 µm, respectively. The trigger217
voltage and holding voltage will be increased when the spacing218
D is increased. In Fig. 5(b), without N-drift implant in the drain219
region, the TLP-measured It2 of HV GGNMOS are 1.3, 1.6,220
and 1.9 A for the spacing D of 5.5, 7.5, and 9.5 µm, where221
the It2 and the holding voltage are obviously increased as the222
parameter D is increased. The trigger voltage is 75 V, which is223
independent to the spacing D.224
Comparing Fig. 5(a) and (b), under the same spacing of D,225
the HV GGNMOS without N-drift implant in the drain region226
has a higher It2 than that with N-drift implant in the drain227
region. To further illustrate the impact of N-drift implant on228
the turn-on mechanism of HV GGNMOS, the simulated current229
distributions of HV GGNMOS before and after the parasitic230
n-p-n BJT is triggered on are shown in Figs. 6 and 7, respec-231
tively. Because the doping concentration of N-grade implant232
Fig. 6. Simulated current distributions of HV GGNMOS (a) with and(b) without N-drift implant in the drain region before the parasitic n-p-n BJT istriggered on.
is higher than that of N-drift implant, the breakdown voltage 233
of the N-grade/HV P-well junction is lower than that of the 234
N-drift/HV P-well junction. Some part of current among HV 235
GGNMOS with N-drift implant flows through the N-grade/HV 236
P-well junction, as shown by the indicated region A in Fig. 6(a). 237
This part of current flows from drain into HV P-well and, 238
finally, to source, which results in a longer current path to 239
trigger on the parasitic n-p-n BJT. Therefore, the TLP-measured 240
I–V curves appear a high-resistance region before the parasitic 241
n-p-n BJT in HV GGNMOS is turned on. Here, a higher trigger 242
voltage is needed to turn on the parasitic n-p-n BJT in HV 243
GGNMOS with N-drift implant, where the trigger voltage will 244
be increased when the spacing D is increased due to a longer 245
current path. The other part of current among HV GGNMOS 246
with N-drift implant flows through the corner between the 247
N-drift implant and the channel, as shown by the indicated re- 248
gion B in Fig. 6(a). This part of current could cause the current 249
crowding at the channel surface to damage the device easily 250
while the parasitic n-p-n BJT being triggered on. Moreover, the 251
current path of HV GGNMOS without N-drift implant flows 252
directly from drain through the N-grade/HV P-well junction 253
to source, as shown in Fig. 6(b). Hence, the trigger voltage 254
is kept the same as the breakdown voltage of N-grade/HV 255
P-well while the spacing D is increased. Most of the current 256
flows from drain to source instead of into the HV P-well, which 257
would not cause a longer current path to trigger on the parasitic 258
n-p-n BJT. Therefore, HV GGNMOS without N-drift implant 259
in the drain region can switch to its snapback region quickly 260
with a lower holding voltage, which in turn results in a higher 261
TLP-measured It2. 262
CHANG AND KER: IMPACT OF DRIFT IMPLANT AND LAYOUT PARAMETERS ON ESD ROBUSTNESS 5
Fig. 7. Simulated current distributions of HV GGNMOS (a) with and(b) without N-drift implant in the drain region after the parasitic n-p-n BJTis triggered on.
For HV GGNMOS with N-drift implant in Fig. 7(a), while263
the voltage reaches to the trigger voltage (the breakdown volt-264
age of the N-drift/HV P-well junction), the current starts to flow265
through the N-drift/HV P-well junction and the parasitic n-p-n266
BJT of HV GGNMOS is turned on into the snapback region.267
After the parasitic n-p-n is triggered on, the ESD current in268
HV GGNMOS with N-drift implant will concentrate around the269
N-drift implant region, as shown in Fig. 7(a), which causes the270
device damage easily. On the contrary, the ESD current in HV271
GGNMOS without N-drift implant will flow more uniformly272
and deeper into the HV P-well to avoid the current crowding,273
as shown in Fig. 7(b), which in turn can sustain higher ESD274
stress [16]. Hence, HV GGNMOS without N-drift implant275
in the drain region has a higher It2 than that with N-drift implant276
in the drain region due to the different current distributions277
among the devices. Moreover, the It2 and the holding voltage278
of HV GGNMOS with or without N-drift implant are increased279
while the spacing D is increased. Although the power dissipa-280
tion is higher due to the higher holding voltage, the device can281
still achieve a higher It2 since the ESD current is spread deeper282
into the device [7].283
The TLP-measured I–V curves of HV gate-VDD PMOS284
(GDPMOS) with or without P-drift implant in the drain region285
are shown in Fig. 8, where the spacing D is also split to286
find its impact on It2. The trigger voltage of HV GDPMOS287
with or without P-drift is ∼80 V, which is higher than the288
operation voltage of 40 V in the given 0.35-µm 40-V CMOS289
process. When the parasitic p-n-p BJT of HV GDPMOS is290
triggered on, the current will be increased as the voltage is291
increased. Because the mobility of electron is higher than that292
Fig. 8. TLP-measured I–V curves of HV GDPMOS (a) with and (b) withoutP-drift implant in the drain region under different spacings D.
of hole, the current gain of the parasitic p-n-p BJT in HV 293
GDPMOS is lower than that of the parasitic n-p-n BJT in HV 294
GGNMOS. Moreover, the base distance of the parasitic p-n-p 295
BJT in HV GGNMOS (4 µm) is longer than that of the parasitic 296
n-p-n BJT in HV GGNMOS (3 µm), which results in the more 297
inefficient parasitic p-n-p bipolar action in the HV GDPMOS. 298
Hence, there is no snapback characteristic in TLP-measured 299
I–V curves of HV GDPMOS as compared with HV GGNMOS. 300
In Fig. 8(a), with P-drift implant in the drain region, the It2 301
of HV GDPMOS are 0.01, 0.01, and 0.06 A for the spacing 302
D of 5.5, 7.5, and 9.5 µm, respectively. After the parasitic 303
p-n-p is triggered on, the current of HV GDPMOS will be 304
slightly increased as the voltage is increased. When the voltage 305
reaches to over 110 V, the current will suddenly increase to 306
burn out the HV GDPMOS. Moreover, In Fig. 8(b), without 307
P-drift implant in the drain region, the It2 of HV GDPMOS are 308
0.13, 0.1, and 0.14 A for the spacing D of 5.5, 7.5, and 9.5 µm, 309
respectively, where the It2 is slightly increased as the parameter 310
D is increased. 311
6 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 2, JUNE 2007
TABLE ITLP-MEASURED It2 OF HV GGNMOS AND HV GDPMOS WITH OR
WITHOUT DRIFT IMPLANT UNDER DIFFERENT SPACINGS D
Comparing Fig. 8(a) and (b), under the same spacing of D,312
the HV GDPMOS without P-drift implant in the drain region313
has a higher It2 than that with P-drift implant in the drain314
region. In Fig. 2(a), because the ESD current of HV GDPMOS315
with P-drift implant flows in the longer current path through the316
P-grade/HV N-well junction, the TLP-measured I–V curves317
appear a high turn-ON resistance and a higher holding volt-318
age. In Fig. 2(b), the current path of HV GDPMOS without319
P-drift implant flows directly through the P-grade/HV N-well320
junction. Hence, the turn-ON resistance of GDPMOS without321
P-drift implant in the drain region is much lower than that with322
P-drift implant in the drain region, which will result in the lower323
holding voltage and higher It2.324
Table I summarizes the dependence of TLP-measured It2 of325
HV GGNMOS and GDPMOS with or without drift implant326
under different spacings D. Because no snapback characteristic327
is found in the TLP-measured I–V curves of HV GDPMOS,328
the holding voltage of HV GDPMOS is much higher than329
that of HV GGNMOS, which results in a lower It2 of HV330
GDPMOS. For both HV GGNMOS and HV GDPMOS with331
the same spacing of D, the device without drift implant in the332
drain region has a higher It2 than that with drift implant in the333
drain region due to the different current distributions among334
the devices. Moreover, HV MOSFETs with drift implant in the335
drain region has the longer current path than that without drift336
implant in the drain region.337
The TLP-measured I–V curves of HVNSCR with or with-338
out N-drift implant in the drain region under different layout339
spacings D are shown in Fig. 9. Although the measured trigger340
voltage of HVNSCR is lower than that of HV GGNMOS, it341
is still higher than the operation voltage of 40 V in the given342
0.35-µm 40-V CMOS process. After the HVNSCR is triggered343
on into its snapback region, it will keep at the lower holding344
voltage.345
In Fig. 9(a), with N-drift implant, the TLP-measured It2 of346
HVNSCR are 4.9, 4, and 2.4 A for the spacing D of 5.5,347
7.5, and 9.5 µm, where the It2 is obviously increased as the348
spacing D is decreased. While the spacing D is increased, the349
distance from anode to cathode of SCR path is increased, which350
results in the increase of the holding voltage [17]. In Fig. 9(b),351
without N-drift implant, the TLP-measured It2 of HVNSCR352
are all over 6 A for the spacing D of 5.5, 7.5, and 9.5 µm.353
Comparing Fig. 9(a) and (b), under the same spacing of D, the354
HVNSCR without N-drift implant in the drain region also has355
Fig. 9. TLP-measured I–V curves of HVNSCR (a) with and (b) withoutN-drift implant in the drain region under different spacings D.
a higher It2 than that with N-drift implant in the drain region. 356
Moreover, HVNSCR without N-drift implant in the drain region 357
has a lower trigger voltage, which can be triggered on into its 358
snapback region earlier. 359
Table II summarizes the dependence of TLP-measured It2 of 360
HV GGNMOS and HVNSCR with or without N-drift implant 361
under different spacings D. With the same spacing of D, both 362
HV GGNMOS and HVNSCR without N-drift implant in the 363
drain region have higher TLP-measured It2 than those with 364
N-drift implant in the drain region. From the TLP-measured 365
I–V curves, the trigger voltage and holding voltage of 366
HVNSCR is lower than that of HV GGNMOS. Therefore, 367
the TLP-measured It2 of HVNSCR is higher than that of 368
HV GGNMOS. In HV GGNMOS, only the drain avalanche 369
breakdown current can be generated to the HV P-well to trigger 370
on the parasitic lateral n-p-n BJT. In HVNSCR, the parasitic 371
vertical p-n-p BJT can be turned on because part of the current 372
can flow from P+ diffusion of the drain region to HV P-well. 373
CHANG AND KER: IMPACT OF DRIFT IMPLANT AND LAYOUT PARAMETERS ON ESD ROBUSTNESS 7
TABLE IITLP-MEASURED It2 OF HV GGNMOS AND HVNSCR WITH OR WITHOUT
DRIFT IMPLANT UNDER DIFFERENT SPACINGS D
Fig. 10. HBM ESD levels of HV GGNMOS with or without N-drift implantin the drain region under different spacings D.
The parasitic vertical p-n-p BJT can also provide a current to374
trigger on the parasitic lateral n-p-n BJT. Furthermore, with the375
turned on vertical p-n-p BJT, the current in HVNSCR flows376
more deeply into the HV P-well as compared to HV GGNMOS,377
which can make the current more uniform distribution among378
the HVNSCR to sustain higher ESD stress. Due to the dif-379
ferent current distributions in HV GGNMOS and HVNSCR,380
the dependences of TLP-measured It2 on the spacing of D are381
different. For HV GGNMOS, as the spacing of D is increased,382
the ESD discharge energy will not concentrate at the local383
drain region and the ESD current can be spread deeper into384
the device, which results in the higher TLP-It2. However, for385
HVNSCR, as the spacing of D is increased, the trigger and the386
holding voltage of SCR path is also increased, which results in387
a lower TLP-It2.388
B. HBM ESD Robustness389
HBM ESD events are produced by the discharge of a charged390
100-pF capacitor through a 1.5-kΩ resistor. The HBM ESD391
levels of HV GGNMOS, HV GDPMOS, and HVNSCR under392
different spacings D are shown in Figs. 10–12, respectively.393
In ESD test, the HBM levels are measured under the failure394
criterion defined as the I–V characteristic curve shifting over395
30% from its original curve after three continuous ESD zaps at396
every ESD test voltage level.397
Fig. 11. HBM ESD levels of HV GDPMOS with or without P-drift implantin the drain region under different spacings D.
Fig. 12. HBM ESD levels of HVNSCR with or without N-drift implant in thedrain region under different spacings D.
In Fig. 10, the HBM ESD levels of HV GGNMOS with 398
N-drift implant in the drain region are about 400 V which is not 399
enough for on-chip ESD protection device in HV CMOS ICs 400
due to the low ESD robustness. By removing the N-drift implant 401
in the drain region, the HBM ESD levels of HV GGNMOS with 402
the same device dimension can be improved up to over 2 kV. 403
Moreover, while the spacing D is increased from 5.5 to 9.5 µm, 404
the HBM ESD levels of HV GGNMOS without N-drift implant 405
can be improved from 2 to 2.8 kV. 406
In Fig. 11, the HBM ESD levels of HV GDPMOS are only 407
improved from 200 to 300 V by removing the P-drift implant 408
in its drain region. Moreover, the HBM ESD levels of HV 409
GDPMOS are not increased when the spacing of D is increased 410
with the minimum step of 100 V in the measurement. Such a 411
low ESD robustness of HV GDPMOS is not suitable for on- 412
chip ESD protection device in HV CMOS ICs. To achieve a 413
good on-chip ESD protection, the power-rail ESD clamp circuit 414
[18] should be added across the power lines of HV CMOS ICs 415
to avoid the ESD current flowing through HV GDPMOS in the 416
breakdown operation. 417
8 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 2, JUNE 2007
Fig. 13. SEM failure picture of contact spiking in the drain region of HVGGNMOS under the spacing D of 7.5 µm after 3-kV HBM ESD stress.
Fig. 14. SEM failure picture of contact spiking in the drain region of HVGDPMOS under the spacing D of 7.5 µm after 400-V HBM ESD stress.
In Fig. 12, the HBM ESD levels of HV GGNMOS can be418
greatly improved by replacing partial N+ diffusion in the drain419
region with P+ diffusion to form HVNSCR. The HBM ESD420
levels of HVNSCR can be further improved by removing the421
N-drift implant in drain region. Here, the HBM ESD levels422
of HVNSCR are not obviously increased when the spacing of423
D is decreased. For HVNSCR without N-drift implant in the424
drain region, the variation on the measured data is increased425
as the spacing D is increased. From these experimental results,426
HVNSCR with high ESD level can be used as a good on-chip427
ESD protection device for HV CMOS ICs.428
Because of the strong snapback phenomenon with a lower429
holding voltage in HV GGNMOS and HVNSCR, the nonuni-430
form turn-on mechanism may occur among the devices, which431
could cause the HBM ESD test results not to correlate well432
with TLP measurements (It2). The TLP could serve effectively433
as a voltage and current limiter (similar to ballasting resistor)434
that could improve device’s robustness in high-current region,435
while the limiting mechanism does not exist in real HBM ESD436
event [19]. Therefore, the devices with and without N-drift437
implant could be uniformly turned on during TLP measure-438
ment. Moreover, the ESD current among the devices without439
N-drift implant will flow more uniformly and deeper into the440
HV P-well to avoid the current crowding, so the devices without441
N-drift implant could serve as the devices with a ballasting442
resistor to force device uniform turn-on and to improve its443
ESD robustness. Hence, as comparing to the TLP-measured444
It2, the HBM ESD levels of the HV devices have a significant445
improvement by removing the N-drift implant.446
Fig. 15. SEM failure picture of contact spiking in the drain region ofHVNSCR under the spacing D of 7.5 µm after 5-kV HBM ESD stress.
C. Failure Analysis (FA) 447
The FA pictures of HV GGNMOS, HV GDPMOS, and 448
HVNSCR after 3-kV, 400-V, and 5-kV HBM ESD stresses 449
are shown in Figs. 13–15, respectively. In Fig. 13, the contact 450
spiking was found in the drain region of the HV GGNMOS 451
without N-drift implant under the spacing of 7.5 µm after 452
3-kV HBM ESD stress. In Fig. 14, the contact spiking was also 453
found in the drain region of the HV GDPMOS without P-drift 454
implant under the spacing of 7.5 µm after 400-V HBM ESD 455
stress. Moreover, in Fig. 15, the contact spiking was found in 456
the drain region of the HVNSCR without N-drift implant under 457
the spacing D of 7.5 µm after 5-kV HBM ESD stress. 458
IV. CONCLUSION 459
The drift implant in the drain region and layout spacing 460
(D) from the drain diffusion to polygate have been split to 461
verify the ESD robustness of HV MOSFETs in a given 40-V 462
CMOS process. It has been found that HV MOSFETs without 463
drift implant in drain region have higher TLP-measured It2 464
and higher ESD robustness than those with drift implant in the 465
drain region. Moreover, without N-drift implant, the It2 and 466
ESD level of HV GGNMOS can be obviously improved as the 467
spacing D is increased. The ESD robustness of HV GGNMOS 468
can be improved up to 2-kV HBM by removing the N-drift 469
implant in the drain region. The HVNSCR without N-drift 470
implant in drain region has the highest ESD performance in a 471
given 40-V CMOS process. For HVNSCR, the TLP-measured 472
It2 can be improved over 6 A and the ESD robustness can be 473
improved to 4 kV by removing N-drift implant in the drain 474
region. Moreover, the ESD level and It2 of HV NMOS can be 475
increased as the layout spacing D from the drain diffusion to 476
polygate is increased. The ESD level and It2 of HVNSCR are 477
increased as this spacing D is decreased. 478
ACKNOWLEDGMENT 479
The authors would like to thank T.-H. Lai, T.-H. Tang, and 480
K.-C. Su of the United Microelectronics Corporation, Hsinchu, 481
Taiwan, R.O.C., for the support of research project in HV 482
CMOS process and to Dr. S.-F. Hsu for the support of the device 483
simulation in MEDICI/TCAD. The authors would also like to 484
thank the Guest Editor (Dr. Y. Chen) and her reviewers for the 485
valuable comments and suggestions to improve this paper. 486
CHANG AND KER: IMPACT OF DRIFT IMPLANT AND LAYOUT PARAMETERS ON ESD ROBUSTNESS 9
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Wei-Jen Chang (S’02) was born in Taiwan, R.O.C., 553in 1979. He received the B.S. degree from the 554Department of Electronics Engineering, National 555Chiao-Tung University, Hsinchu, Taiwan, in 2002, 556where he is currently working toward the Ph.D. 557degree at the Institute of Electronics. 558
His current research interests include electrostatic- 559discharge protection design for mixed-voltage I/O 560circuits and high-voltage applications. 561
Mr. Chang received the MediaTek Fellowship 562award in 2005. 563
Ming-Dou Ker (S’94–M’95–SM’97) received the 564B.S. degree from the Department of Electron- 565ics Engineering, National Chiao-Tung University, 566Hsinchu, Taiwan, R.O.C., and the M.S. and Ph.D. 567degrees from the Institute of Electronics, National 568Chiao-Tung University, in 1986, 1988, and 1993, 569respectively. 570
In 1994, he was with the Very Large Scale 571Integration (VLSI) Design Department, Computer 572and Communication Research Laboratories (CCL), 573Industrial Technology Research Institute (ITRI), 574
Taiwan, as a Circuit Design Engineer. In 1998, he was the Department Manager 575in the VLSI Design Division of CCL/ITRI. Currently, he has been a Full Pro- 576fessor with the Department of Electronics Engineering, National Chiao-Tung 577University. In the field of reliability and quality design for CMOS integrated 578circuits, he has published over 300 technical papers in international journals 579and conferences. He has proposed many inventions to improve reliability and 580quality of integrated circuits, which have granted with 120 U.S. patents and 581132 R.O.C. (Taiwan) patents. His current research topics include reliability 582and quality design for nanoelectronics and gigascale systems, high-speed and 583mixed-voltage I/O interface circuits, and on-glass circuits for system-on-panel 584applications in thin-film-transistor liquid crystal display. He has been invited 585to teach or to consult reliability and quality design for integrated circuits by 586hundreds of design houses and semiconductor companies in the Science-Based 587Industrial Park, Hsinchu; in the Silicon Valley, San Jose, CA; in Singapore; in 588Malaysia; and in Mainland China. 589
Dr. Ker has served as member of the Technical Program Committee and 590Session Chair of numerous international conferences He was selected as a 591Distinguished Lecturer in IEEE Circuits and Systems Society for 2006–2007. 592He has also served as an Associate Editor of IEEE TRANSACTIONS ON VLSI 593SYSTEMS. He was elected as the President of Taiwan ElectroStatic Discharge 594(ESD) Association in 2001. He has received many research awards from ITRI, 595National Science Council, National Chiao-Tung University, and the Dragon 596Thesis Award from Acer Foundation. In 2003, he was selected as one of the 597Ten Outstanding Young Persons in Taiwan by Junior Chamber International. In 5982005, one of his patents on ESD protection design has been awarded with the 599National Invention Award in Taiwan. 600