THE EQUIPMENT SHOWN HEREON MAY BE ......Q2 C20 C23 E2 R26 R180 R24 C29 C25 C27 F2 C31 P2 C1 R209 R208 R207 R206 C2 C11 C16 C7 C19 C5 C10 C12 R1 R2 C15 C14 C13 C6 C3 C4 C8 C9 C17 C18

SDP-K1 SCHEMATIC (REV E)PAGE 2 - USB

PAGE 4 - MCU MISCELLANEOUS SIGNALSPAGE 5 - PROGRAMMING PROCESSOR

PAGE 3 - MCU

PAGE 6 - POWER ON RESETPAGE 7 - POWER CIRCUITRYPAGE 8 - ARDUINO UNO REV3 HEADERPAGE 9 - SDP CONNECTORPAGE 10 - SDRAM LEVEL TRANSLATORSPAGE 11 - SDRAM

1 11

<User Define><User Define><User Define>

: Pitch-pitch StyleVendor StylePACKAGE : N/A-lead N/A N/A-family

: N/AProduct(s): N/AHW TYPE : Customer Evaluation

no_template

ECodeID1:1

02_049259TBD

-

-

-

-

-

Sean Doyle

-

-

-

-

REV

2REVISIONS

1

OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES.USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER

8

2

67

A

DATE APPROVED

D

B

DESCRIPTION

345

57

OEM PART# HANDLER

6

C

B

8

SOCKET OEMBK/BD SPEC.P.O SPEC.

A

3 14

C

NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS

CHECKER

DESIGNER

PTD ENGINEER

TEST ENGINEER

DECIMALS

X.XXX +-0.005X.XX +-0.010

MASTER PROJECT TEMPLATE

TOLERANCES

+-1/32FRACTIONS

+-2SIZE

DDDD

SCHEMATIC

DRAWING NO.

SCALE CODE ID NO.SHEET OF

REV.

DA A

ENV C

L GSE

ODATE

ANGLES

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES

TESTER TEMPLATE

TEMPLATE ENGINEER

HARDWARE SERVICES

HARDWARE SYSTEMS

COMPONENT ENGINEER

TEST PROCESS

HARDWARE RELEASE

D

USB

RESISTOR FOR RBIAS ON USB3443 NEEDS TO BE KEPT AS CLOSE AS POSSIBLE TO THE DEVICE

KEEP 1UF CAP AS CLOSE AS POSSIBLE TO PIN 9

KEEP 0.1UF CAP AS CLOSE AS POSSIBLE TO PIN 1

KEEP DP & DM STUBS TO <2.5MM

2 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

0

DNI0

0 DNI

0

0.33UF

1000PF

2.2UF

26MEGHZ

0.1UF

0.1UF

10K

338.06K

1UF

333333

1UF

18PF

12K

24MEGHZ

1UF

2.2UF

100K

100K

0.1UFUSB2422-I/MJ

1UF

0.1UF

18PF

USB3343-CP

1UF

0.1UF

5.1K

16VDC

SI2333DDS-T1-GE3

1UF0.033UF

600OHM

5.1K

76.8K

1000PF

1UF

0.5A

330 0.1UF

12401598E4#2A

33333333

3333

3333

1000PF

1000PF

1000PF

1000PF

D2

D4

R80

V1

Q2

C20

C23

E2

R26

R180

R24

C29

C25 C27

F2

C31

P2

C1

R209

R208R207R206

C2

C11

C16

C7

C19

C5

C10

C12

R1

R2

C15

C14

C13

C6

C3

C4

C8

C9

C17

C18

R5

R12Y1

Y2

R6

R7

R9

R8

R3

U1

U2

PROG_I2C_SDA

PROG_I2C_SCL

NON_REM1

USB_OTG_HS_ULPI_STP

USB_ULPI_RESET

USB_ULPI_DMUSB_ULPI_DP

MAIN_PWR_SUPPLY

USB_VBUS

+3.3V

ULPI_REFCLK

USB_DM

HUB_XTAIN

HUB_XTALOUT

USB_VBUS_DETECT

USB_VBUS

+3.3V

+3.3V

+3.3V

HUB_RESET

HUB_XTAIN

NON_REM1CFG_SEL

USB_PROG_DP

USB_PROG_DMUSB_ULPI_DM

HUB_XTALOUT

USB_DP

USB_ULPI_DP

USB_OTG_HS_ULPI_CKUSB_OTG_HS_ULPI_DIRUSB_OTG_HS_ULPI_NXT

MAIN_PWR_SUPPLY

CFG_SEL

USB_DM

USB_DP

USB_VBUS

USB_CC2 USB_CC1USB_CC2USB_DP

USB_DMUSB_DP

USB_CC1

USB_DM

USB_OTG_HS_ULPI_D0USB_OTG_HS_ULPI_D1USB_OTG_HS_ULPI_D2USB_OTG_HS_ULPI_D3

USB_OTG_HS_ULPI_D5USB_OTG_HS_ULPI_D4


2

1

2

1

2

1

2

1

3

21

21

B4

B9

A9

A4

B3B2

A3A2

SH4SH3SH2SH1

B8

A8

A10A11

B10B11

B1

B12

A12

A1

B7

A7

B6

A6

B5

A5

161152

134143

12511610798

43

12

4

2 3

1

21

22

PAD

1891

16 20

53

19

42

17

131415

24

117

23

128

6

10

20

915 23

17

16

24

22

21

19

PAD

3

181314

1

12111087654

2

VSS

RBIAS

PLLFILT

XTAIN/CLKIN

XTALOUT/(CLKIN_EN)

USBDP_UPUSBDM_UP

VDD3

3

SUSP_IND/LOCAL_PWR/(NON_REM0)

VBUS_DET

RESET_N SMBCLK/CFG_SEL0SMBDATA/NON_REM1

OCS2_N

PRTPWR2CRFILT

VDD3

3

OCS1_N

PRTPWR1/(BC_EN1)

NC

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

VDD3

3

SH4SH3SH2SH1

GNDTX2+TX2-VBUSCC2D+D-

SBU2VBUSRX1-RX1+GND

GNDRX2+RX2-VBUSSBU1

D-D+

CC1VBUSTX1-TX1+GND

PAD

STP

VDD1

8

RESETB

REFCLK/XI

XO

RBIAS

ID

VBUS

VBAT

VDD3

3

DMDP

DATA7DATA6DATA5

VDDI

O

DATA4DATA3DATA2DATA1DATA0

NXT

CLKOUTDIR

VDDOUTGND

OE

IN/OUT

NC

NC

IN/OUT

D

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

AC

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.

2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

STM32F469. TAKE CARE NOT TO ENABLE SPI AND QUADSPI ON

NOTE: SOME OF THE SPI & QUADSPI SIGNALS ON THE SDP

THE SDP CONNECTOR SIMULTANEOUSLY.

MCU

CONNECTOR ON PAGE 9 ARE ROUTED TO MULTIPLE PINS ON THE

SDP QUADSPI_SCK = STM32F469 PF10 (F469_SPI/QUADSPI_SCK)SDP QUADSPI_DIO1 = STM32F469 PC10 (F469_SPI_MISO/QUADSPI_DIO1)SDP QUADSPI_DIO0 = STM32F469 PD11 (F469_SPI_MOSI/QUADSPI_DIO0)SDP QUADSPI_NSS_A = STM32F469 PB6 (F469_SPI/QUADSPI_NSS_A)

SDP SPI_MISO = STM32F469 PF8 (F469_SPI_MISO/QUADSPI_DIO1)SDP SPI_SCK = STM32F469 PH6 (F469_SPI/QUADSPI_SCK)

SDP SPI_MOSI = STM32F469 PF9 (F469_SPI_MOSI/QUADSPI_DIO0)SDP SPI_NSS_A = STM32F469 PB9 (F469_SPI/QUADSPI_NSS_A)

3 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

STM32F469NIH62.2UF 2.2UF

31

4.7UF

DNI

10K

10K

DNI10K

8.2PF

3333

8.2PF

9

8

7

6

5

3

2

1

12

11

10

9

8

7

6

5

0

4

1

0

33

3333

33

33

33

33

30

29

27

26

24

23

22

21

20

18

17

16

15

14

13

3

2

3333

15

14

10

11

DNI2.2UF

0.1UF 0.1UF

1UF

0.1UF1UF

0.1UF

0.1UF0.1UF0.1UF0.1UF


0.1UF0.1UF0.1UF

33

3333

33

3333

33

33

8MEGHZ

0

2.2UF

0.1UF

0.1UF

STM32F469NIH6

0.1UF0.1UF 0.1UF 4.7UF 0.1UF

33

0

DNI0

DNI

33

19

STM32F469NIH6

28

25

10K

4

10K

33

0600OHM

0.1UF

33

33

33

33

R60

C77

U11

U11

U11

R33

Y3

C51 C54

R45

C74 C76

E3

R47

C71

C68

R31

R32

C48 C50 C53 C56 C58 C60 C62 C64 C65

C47 C49 C52 C55 C57 C59 C61 C63

C70

C72

C73

C79

C67 C69

R4

R10

C75

R46

R57

C78

R61

R63

R62

SDP_SPI/QUADSPI_SCK

SDP_SPI/QUADSPI_NSS_A

F469_SPI_MISO/QUADSPI_DIO1

MAIN_PWR_SUPPLY

F469_SPI_MOSI/QUADSPI_DIO0

F469_SPI/QUADSPI_NSS_A

F469_SPI/QUADSPI_SCK

SDP_SPI_MISO/QUADSPI_DIO1

MAIN_PWR_SUPPLYMAIN_PWR_SUPPLY

BOOT1_CTRL

MAIN_PWR_SUPPLY

ARDUINO_SDA_SWARDUINO_SCL_SW

SDP_I2C_SDA0_SW

SDP_GPIO0

PROCESSOR_STATUS

SDP_GPIO4

LED_GREEN

ARDUINO_GPIO5/PWM1

F469_SWDIOF469_SWCLK


BOOT1_CTRLARDUINO_GPIO13/SCK

ARDUINO_GPIO12/MISOUSB_OTG_HS_ULPI_D7

USB_OTG_HS_ULPI_D3USB_OTG_HS_ULPI_D4USB_OTG_HS_ULPI_D5USB_OTG_HS_ULPI_D6

LED_ORANGELED_RED

ARDUINO_GPIO1/TX

F469_SPI_MISO/QUADSPI_DIO1SDP_SERIAL_INT

BOOT0_CTRL

F469_VIO_CHECK

ARDUINO_GPIO0/RX

SDP_TMR_B

PROGRAMMING_PROCESSOR_UART_TX

SDP_SPI_NSS

SDP_SPORT_DR0SDP_SPORT_RFS

SDP_SPORT_RSCLK

SDP_QUADSPI_DIO3ARDUINO_GPIO3/PWM0

ARDUINO_GPIO8ARDUINO_GPIO7ARDUINO_GPIO4SDRAM_SDCLKARDUINO_GPIO2

SDRAM_A13SDRAM_A12

SDP_EXT_BOOT

SDRAM_NBL1SDRAM_NBL0

F469_SPI_MOSI/QUADSPI_DIO0

SDP_UART_RXSDP_UART_TX

SDRAM_A<11:0>

SDRAM_D<31:0>

SDRAM_A<15:14>

SDP_SPI_NSS_C

MAIN_PWR_SUPPLY

USB_OTG_HS_ULPI_D0

ARDUINO_ADC_IN2

USB_OTG_HS_ULPI_STPARDUINO_ADC_IN3USB_OTG_HS_ULPI_DIRUSB_OTG_HS_ULPI_NXTARDUINO_ADC_IN4

SDP_GPIO5

SDP_SPI_NSS_BARDUINO_GPIO11/PWM5/MOSI

SDP_SPORT_TFSSDP_TMR_D

VDDA

ARDUINO_ADC_REF

MPU_VDD_SUPPLY

ARDUINO_ADC_IN0

ARDUINO_ADC_IN5

VDDA

SDP_GPIO7

ARDUINO_GPIO6/PWM2

SDP_GPIO6

SDP_GPIO2

SDP_GPIO1

PROGRAMMING_PROCESSOR_UART_RX

SDRAM_N_CAS

USB_OTG_HS_ULPI_CKARDUINO_ADC_IN1

F469_USB_RESET

F469_SWO

ARDUINO_GPIO10/PWM4/SS

SDP_GPIO3

SDP_QUADSPI_DIO2

F469_SPI/QUADSPI_SCK

SDP_SPORT_TSCLKSDP_SPORT_DT0

SDRAM_N_WE

SDRAM_SDNE0SDRAM_SDCKE0

USB_AVAILABLE

F469_SPI/QUADSPI_SCKSDP_I2C_SCL0_SW

SDRAM_N_RAS

SDRAM_NBL3SDRAM_NBL2

MAIN_PWR_SUPPLY

F469_SPI_MISO/QUADSPI_DIO1F469_SPI_MOSI/QUADSPI_DIO0

MAIN_PWR_SUPPLY

SDP_TMR_AARDUINO_GPIO9/PWM3

MAIN_RESET

F469_SPI/QUADSPI_NSS_A

MAIN_PWR_SUPPLY

ARDUINO_ADC_REF

MAIN_PWR_SUPPLY

SDP_SPI_MOSI/QUADSPI_DIO0

J6F2

H10

B12C12D12C11D11C10B11A11L15L14K15N10M10M11L12K13

A6

A2

B1B2R8N9P9R9

P10R10R12P11R11

D2E2G2H2J2K3

L2L1P8M6N6P6M8

N7M7M13M12N12N11J15J14H14D9C8B8C7B3A4B7

K4J4H4J3

N13P14N14P15N15

E13D13

E14D14C14C13C3D3D6D4C2E4D5F3E3

H3G4

L5K12G13

G12

C1

L11

L10F11E7K5

L8L9

J11

E9

F4K11

L7

G11

R1P1 N1

K9

F6K6H6K7

G10F8

K10F9

L6

M1

E6

H13H12

J13J12

F13F12J1

N3N2P2R2N4P4P3R3

F15E15D15C15B15A15A14A13

R5R4M5

A10A9

B6B5A7B4

P12R13L13K14R14R15

M2M3M4L4N5P5H15G15G14F14B14B13A12D1

E1F1

E5

G1H1

R7P7N8M9M14

B10B9C9

C4

1 2

1 2

F10

F7

G5

C5C6D7D8

D10

K2K1

G3

L3

A1

M15E12

P13

A3A5

K8

F5E10

J10

G6

H5

R6

A8

E8J5

H11

E11

BANK1

PDR_ON

DSI_DI_NDSI_DI_P

DSI_D0_NDSI_D0_P

DSI_CK_NDSI_CK_P

PK7PK6PK5PK4PK3

PJ15PJ14PJ13PJ12

PJ5PJ4PJ3PJ2PJ1PJ0

PC13_ANIT_TAMPPC12PC11PC10

PC9PC8PC7PC6PC5PC4PC3PC2PC1PC0

BOOT0

NRST

PH1_OSC_OUTPH0_OSC_IN

PC15_OSC32_OUTPC14_OSC32_IN

PB15PB14PB13PB12PB11PB10PB9PB8PB7PB6PB5PB4PB3PB2PB1PB0

PA15PA14PA13PA12PA11PA10PA9PA8PA7PA6PA5PA4PA3PA2PA1PA0_WKUP

BANK3

VCAP2VCAP1

BYPASS_REGVBAT

VREF-VSSA

VSS20VSS19

VSS17VSS15VSS14

VSS13_VSS18VSS12VSS11VSS10

VSS9VSS8VSS7VSS6VSS5VSS4VSS3VSS2VSS1

DSI_VSS

DSI_VCAPDSI_VDD12

VDD_VREGDSI

VREF+VDDA

VDD19VDD18VDD17VDD15VDD14VDD13VDD12VDD11VDD10

VDD_USBVDD8VDD7VDD6VDD5VDD4VDD3VDD2VDD1

BANK2

PI15PI14PI13PI12PI11PI10

PI9PI8_ANTI_TAMP2

PI7PI6PI5PI4PI3PI2PI1PI0

PH15PH14PH13PH12PH11PH10

PH9PH8PH7PH6PH5PH4PH3PH2

PG15PG14PG13PG12PG11PG10

PG9PG8PG7PG6PG5PG4PG3PG2PG1PG0

PF15PF14PF13PF12PF11PF10PF9PF8PF7PF6PF5PF4PF3PF2PF1PF0

PE15PE14PE13PE12PE11PE10PE9PE8PE7PE6PE5PE4PE3PE2PE1PE0

PD15PD14PD13PD12PD11PD10PD9PD8PD7PD6PD5PD4PD3PD2PD1PD0

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

LED4

STATUS

LED1

LED2

LED3

MCU MISCELLANEOUS SIGNALS

4 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

0

0

0

0

0

DNI

0

DNI

0

DNI

DNI

0

BSH111BKR

10K

LTC4313IDD-3#PBF

10K

10K

10K

LY L29K-H1J2-26-Z

BSH111BKR

ADG819BRTZ

0.1UF

BSH111BKR

LY L29K-H1J2-26-Z

10K

2.2K LG L29K-G2J1-24-Z

4.02K

2.2K

10K

0.1UF

10K

10K

LTC4313IDD-3#PBF

LTC4313IDD-3#PBF

10K

10K

BSH111BKR

10K

10K

2.2K

0.1UF

BSH111BKR

1MEG

1MEG

BSH111BKR

0.1UF

2.2K

0.1UF

0.1UF

10K

3.9K

3.9K

10K

DNI

DNI

4.02K

BSH111BKR

LS L29K-H1J2-1-Z

LTC4313IDD-3#PBF

0.1UF

SN74LVC1GU04DCKR

SN74LVC1GU04DCKR

U34R210R104

U33

U12

U37

U36

U35

R219

R16

DS5

DS4

DS6

R224

R221

Q16

R222

Q17

R220

Q18

R223

R214

C21

C66

R213

R212

C30

R211

R22

R20

R67

R25

R21

R19

R64

R23

R218R216

R217R215

Q15

C26

R18

C24

R17

Q1

R78 R113

C28

Q5

R120

R119

Q4

R118 DS3

U39

C118

SDP_I2C_SCL0_SW

ARDUINO_SDA_SWARDUINO_SCL_SW

SDP_I2C_SDA0_SW

ARDUINO_I2C_CTRL_INV

+3.3V

SDP_I2C_SCL

MAIN_PWR_SUPPLYUSB_AVAILABLE

SDP_I2C_SDA

SDP_I2C_CTRL_NON_INV

+5V

SDP_I2C_SCL0_SW

MAIN_PWR_SUPPLY

SDP_I2C_CTRL_INV

+3.3V

F469_VIO_CHECK

SDP_I2C_SDA0_SW

+3.3V

PROG_I2C_SDAPROG_I2C_SCL

ARDUINO_I2C_CTRL_INV

PROG_I2C_SDA

+3.3V

USB_VBUS

+5V

ARDUINO_I2C_CTRL_NON_INV

PROCESSOR_STATUS

MAIN_PWR_SUPPLY

+5V

LED_RED

MCU_ADJ

+5V

SDP_I2C_CTRL

+3.3V

ARDUINO_I2C_CTRL

+3.3V

+3.3V

ARDUINO_SDA

LED_GREEN

+5V

ARDUINO_SCL_SW

MAIN_PWR_SUPPLY

LED_ORANGE

ARDUINO_I2C_CTRL_NON_INV

ARDUINO_SCLARDUINO_SDA_SW

PROG_I2C_SCL

SDP_I2C_CTRL_NON_INV

+3.3V

SDP_I2C_CTRL_INV

4

5

13

2

4

5

13

2

8

7 62 3

5

4PAD

1

8

7 62 3

5

4PAD

1

8

7 62 3

5

4PAD

1

8

7 62 3

5

4PAD

1

A C

A C

A C

2

1

3

2

1

3

2

1

32

1

3

A C

2

6

4

1

3

5

SG

D

SG

D

S1D

VDDS2

GNDIN

VCC

Y

GND NC

A

VCC

Y

GND NC

A

EPAD

VCC

SDAOUT SDAIN

READY

GND

SCLINSCLOUT

ENABLE

EPAD

VCC

SDAOUT SDAIN

READY

GND

SCLINSCLOUT

ENABLE

EPAD

VCC

SDAOUT SDAIN

READY

GND

SCLINSCLOUT

ENABLE

EPAD

VCC

SDAOUT SDAIN

READY

GND

SCLINSCLOUT

ENABLE

SG

D

SG

D

SG

D

SG

D

SG

D

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

CONNECTED

DAPLINK TX

MBED DAPLINK

AWAKE

DAPLINK RX

5 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

DNI

2.2UF

DNIBLU

2.2K

DNI0.1UF

3220-10-0100-00

3220-10-0100-00

100K

2.2K

ADG854BCPZ

0.1UF

18PF 18PF

4.02K

100K

0.1UF

DNI

8MEGHZ

10K

3333

1UF

1MEG100K 100K 100K

LY L29K-H1J2-26-Z

BSH111BKR

10K

1UF 0.1UF

MK20DX128VFM5

10K

69157-102HLF

DNI

R225

TP1

R14R13

DS1R115

Q3

R116

R11

C116

P8

C111 C115

C108

C117C112

C113

R110R109

P11

P12

U23

R111R108

R105

R112

R107

R106

C109 C110

Y4

U24

DAPLINK_USB_RESET

MAIN_PWR_SUPPLY

F469_SWO

F469_SWCLK

USB_PROG_DPUSB_PROG_DM

PROGRAMMING_PROCESSOR_UART_RXPROGRAMMING_PROCESSOR_UART_TX

+5VMAIN_PWR_SUPPLY

MBED_TMS

MBED_TDO

MBED_RESET

HEADER_SWDIO

TARGET_SWD_CLK

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

MBED_TCLK

MAIN_PWR_SUPPLY

HEADER_SWCLKTARGET_SWD_DATA_IO

HEADER_SWCLK

SWD_CTRLSWD_CTRL

HEADER_SWDIO

MBED_TDI

MAIN_RESET

F469_SWDIO

PROCESSOR_AWAKE

USB_AVAILABLE

TARGET_SWD_DATA_IO

PROG_RESET

MBED_TMSMBED_TDOMBED_TDI

MBED_TCLK

+5V

ARDUINO_I2C_CTRLSDP_I2C_CTRL

PROG_I2C_SDAPROG_I2C_SCL

PROCESSOR_AWAKE

BOOT0_CTRL

TARGET_SWD_CLKMBED_LED_CTRLPROGRAMMING_PROCESSOR_UART_TXPROGRAMMING_PROCESSOR_UART_RXMAIN_RESET

MBED_LED_CTRL

A C

2

1

3

21

10987654321

10987654321

6

79

31

5

4

10

8

2

21

9

82

6 5

71 11

34

19

32

31

30

29

28

27

26

25242322

2120

18171615141312

PAD

10

SG

D

D2IN2S2BS2A

D1

VDD

S1BIN1

S1A

GND

PAD

PTD7

PTD6/LLWU_P15

PTD5

PTD4/LLWU_P14

PTC7

PTC6/LLWU_P10

PTC5/LLWU_P9

PTC4/LLWU_P8PTC3/LLWU_P7

PTC2PTC1/LLWU_P6

PTB1PTB0/LLWU_P5

RESET_B

PTA19PTA18PTA4/LLWU_P3PTA3PTA2PTA1PTA0

VBAT

EXTAL32XTAL32

VSSA

VDDA

VREGIN VOUT33

USB0_DMUSB0_DP

VSS

VDD

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

52K OHM INTERNAL PULL UP

POWER ON RESET

6 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

0

DNI

95.3K

100K

0.1UF

SN74LVC1G08DBVT

ADG819BRTZ

74LVC1G11DW-7

0.1UF

ADM6384YKS29D3Z

10K

SN74LVC1G08DBVTPMV48XP,215

0.1UF100K

100K

AD8613AKSZ

100K

0.1UF

ADG819BRTZ

3.9K

BSH111BKR

0.1UF

100K

100K

0.1UF

120K

100K

0.1UF

0.1UF

ADM6384YKS29D3Z

ADM6384YKS17D3Z

100K

0.1UF

74AUP1G09GW

NC7SP125P5X

0.1UF100K

0.1UF

100K

EVQQ2K03W

0.1UF R229U31

C90

U15

C81R79

R77 C89

U30

S1

C22

R75

R15

U29

R76

C88

U32

R69

Q10

Q6

U28

R68

U40

C91

R82

R81

C87

U41

R74

R70

U10C82

U14C85

R73

C86

R71

C83

U13C84

R72

F469_USB_RESETULPI_VBAT_CHECK

SDP_RESET_IN

MAIN_PWR_SUPPLY

MBED_RESET

MAIN_PWR_SUPPLY

ULPI_VBAT_CHECK

USB_ULPI_RESET

MAIN_PWR_SUPPLY

ULPI_VBAT_CHECKDAPLINK_USB_RESET

+5V

POR_3.3V

MCU_ADJ

MAIN_PWR_SUPPLY

1.8V_RESET_SUPPLY

POR_3.3V

MCU_ADJ

+5V

+3.3V

MAIN_PWR_SUPPLY

+3.3V

HUB_RESET

+5V

MAIN_PWR_SUPPLY

MAIN_RESET

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

SDP_RESET_OUT

MAIN_RESET

MAIN_RESET

MAIN_PWR_SUPPLY

PROG_RESET

4

5

1

3

2

4

5

3

21

4

5

2

631

2B1B

2A1A

4

5

3

21

4

5

3

1

2

2

1

3

2

1

3

2

5

143

2

6

4

1

3

5

2

6

4

1

3

5

4231

4231

4231

VCC

Y

GND

A

B

SG

D

RESET_NMR_NVCC GND

V+

-IN+IN

V-OUT

S1D

VDDS2

GNDIN

S1D

VDDS2

GNDIN

RESET_NMR_NVCC GND

RESET_NMR_NVCC GND

Y

OE_N

A

VCC

GND

VCC

GNDB

YA

VCC

GNDC

YBA

VCC

GNDB

YA

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

MPU_VDD_SUPPLY

RECOMMENDED VOLTAGE RANGE: 7V -12V

SDRAM_ARDUINO_SUPPLY

POWER CIRCUITRY

USB_SUPPLY

MAIN_SUPPLY

IO_SUPPLY

VIO_ADJUST

3.3V

1.8V

PWR_GOOD

+5V_REG

3.5 AMP MAX

VIN

7 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

86.6K 86.6K86.6K

0

DNI0

0DNI

0

0

6800PF

6800PF

6800PF

6800PF6800PF

1MEG

0.1UF

NC7SZ332P6X

10K

100K

10K10K

PMV48XP,215

RED

DMP1046UFDB -7

LTC4417HUF#PBF

1UF

DMP1046UFDB -7DMP1046UFDB -7

RED

LT8609SIV#PBF

PMEG3030EP,115PJ-037AH

0.1UF

178K

10PF

374K 374K

BSS138LT1G

100K

22UF

DMP1046UFDB -7

22UF

16.9K

1.5A

105K

1UF

ADP7105ACPZ-3.3

0.1UF

0.1UF

0.1UF0.1UF

1MEG

13.7K

6.8UH38.3K

1UF

1MEG

38.3K

1MEG

100K

34.8K

M20-9990345

374K

RED

38.3K

DMP1046UFDB -7

453K4.7UF

REDDNI

47UF47UF

100K

1UF 1UF

RED

100K

ADP7105ACPZDNI

DNI

BSS138LT1G

13.7K

16.9K

RED

ADP7105ACPZ

1UF

34.8K

100K

1UF

100K

ADP7105ACPZ-3.3DNI

RED

100K1UF1UF

30K

12K

100K

DNI

100K

1UF

DNI

4.02K

100K

LG L29K-G2J1-24-Z

0.1UF

13.7K

DMP1046UFDB -7

ADP7105ACPZ

50165016

1UF

1UF

ADP1290ACBZ

1UF

34.8K

100K

16.9K

100K

0.1UF

BSS138LT1G

BSH111BKRR114R103R98

R97

U17C97

C99 R181

C80

U38

Q19

R228

R226

TP11

R205

R227

C146

U26

C144

C142

TP6

TP12

C106R186

TP22 TP23

R117 DS2

U22

Q11

Q7

F3 R201

C143

R190

R189

Q9

Q8

D5P15

C100C98C96

Q13

Q13 Q14

Q14

Q12

Q12

R204

R198 R199

R200R196

C148C147C145R202

L1

R203R194

C141R187

C133

P14

R195

TP10

R197

TP9

R192

C140

C136

R193

C138

C137

U21

C103

U20

C104

TP8

R191

C139

C135TP7

R188C134

C107

U19

C105

U18

R184C102

R185

R93

R94

R95

R88

R89

R90

R83

R84

R85

R183

C101

R182

R179

R178

R177R92

U16

C93

C94

C95

R86

R91

R87

+5V_REG

+5V

+5V_REGSDP_VIN

ARDUINO_VIN

USB_VBUS_OVUSB_VBUS_UV

USB_CONFIG

SEC_PWR_SENSE

SDP_VIN_UV

+5V_REG_OV USB_VBUS_OV

USB_VBUS_UV

USB_VBUS+5V_REG

USB_VBUS

+5V_REG_OVSDP_VIN

SDP_VIN_UVSDP_VIN_OV

+5V_REG_UV+5V_REG

+5V

+5V_REG_UV

SDP_VIN_OV

SDP_VIN

USB_VBUS

+5V_REG

IO_PWR_SUPPLY

MAIN_PWR_SENSE

MAIN_PWR_SENSE

SDRAM_&_ARDUINO_PWR_SUPPLY

MAIN_PWR_SUPPLY

MCU_ADJ

+5V+3.3V

+5V

MAIN_PWR_SUPPLY

+5V

SEC_PWR_SENSE

MCU_ADJ

+5V

MPU_VDD_SUPPLY

+5V_REG SDP_VIN

MPU_VDD_SENSE

+5V

+5V

+5V_CON

+5V

MPU_VDD_SENSE

USB_CONFIG

USB_CONFIG

PROCESSOR_AWAKE

B2A2

B1A1

C2C1

4

5

2

631

2

1

3

118

4

2

7

PAD63

5

1

1

1 1

A C

109

2

15

16

65

112

20191817714843

13

PAD

11

2

1

3

2

1

3

21

2

1

3

2

1

3

A C

2

1

4

5

PAD23

1

2

PAD1

6

1

2

PAD1

6

4

5

PAD23

1

2

PAD1

6

4

5

PAD23

32

1

1

1

18

4

2

7

PAD63

5

18

4

2

7

PAD63

5

1

1

18

4

2

7

PAD63

5

18

4

2

7

PAD63

5

141618

12

98719

20

21

5

3

1

23

PAD

6

4

2

24

10

131517

22 11

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

GNDENVOUTVINVOUTVIN

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

PAD

NCNCNCNC

SYNC

TR/SS

GND

FBPG

EN/UVVINVIN

GND NC

SWSW

GND

GND

VCC

RT

SG

D

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

PAD

V1

V2

V3

VS1

G1

VS2

G2

VS3

G3

VOUT

CAS

GND

VALID3_NVALID2_NVALID1_N

OV3UV3

OV2UV2

OV1UV1

HYSSHDN_NEN

BA

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

THE ADC'S PINS A4 AND A5 ARE ONLY USED AS ADC'S THEY DO NOT WORK AS I2C LINES

ANALOG

POWER

5V

VIN

3/PWM

DIGI1

DIGI0

11/PWM/MOSI12/MISO13/SCKGNDAREF 1.7 <= AREF <= VDDA

SCLSDA

5/PWM

RX + 0TX + 12

4

7-----

A1A2

A4A5

A3

NCIOREFRESET

---------

-

--

A0

GNDGND

6/PWMAIN

10/PWM/CS9/PWM8

ARDUINO CONNECTOR

3.3V

8 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

RED

DNI

2.2K2.2K

PPPC101LFBN-RC

PPPC081LFBN-RC

PPPC081LFBN-RC

PPPC061LFBN-RC

TSW-103-07-F-D

TP5

R66R65

P5

P3

P7

P4

P6

+5V_CON

ARDUINO_VIN

+5V_CONSDRAM_&_ARDUINO_PWR_SUPPLYMAIN_RESETIO_PWR_SUPPLY

ARDUINO_ADC_IN0ARDUINO_ADC_IN1ARDUINO_ADC_IN2

ARDUINO_GPIO11/PWM5/MOSI

ARDUINO_GPIO11/PWM5/MOSI

ARDUINO_ADC_IN3

ARDUINO_GPIO7ARDUINO_GPIO6/PWM2ARDUINO_GPIO5/PWM1

ARDUINO_GPIO4ARDUINO_GPIO3/PWM0

ARDUINO_GPIO0/RX

ARDUINO_GPIO8

ARDUINO_ADC_IN5

ARDUINO_GPIO1/TX

ARDUINO_GPIO9/PWM3ARDUINO_GPIO10/PWM4/SS

ARDUINO_SCLARDUINO_SDA

ARDUINO_GPIO12/MISOARDUINO_GPIO13/SCK

MAIN_PWR_SUPPLY

ARDUINO_ADC_IN4

ARDUINO_GPIO2

ARDUINO_ADC_REF

ARDUINO_GPIO13/SCKARDUINO_GPIO12/MISO

MAIN_RESET

1

654321

87654321

87654321

654321

10987654321

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

SPI

CONNECTOR

VIO: USED TO SET I/O VOLTAGE

VIN: USE THIS PIN TO POWER THE SDP-K1 REQUIRES 5V 300MA

HIGH OR LOW BY YOUR BOARD AT POWER UP. FAILURE TO MEET THIS CRITERIA MAY RESULT IN A NON-FUNCTIONAL SYSTEM.

DATA LINE UNLESS PROPERLY ADDRESSED WITH AN ACTIVE LOW CHIP SELECT, YOU MUST ALSO ENSURE THE SPI CLK LINE IS NOT HELD

PARALLELPORT

GENERALINPUT/OUTPUT

I2C

SPORT

AS SPI IS A SHARED BUS, YOU MUST ENSURE THAT ANY SPI DEVICES ON YOUR DAUGHTER BOARD ARE NOT ACTIVELY DRIVING THE MISO

STANDARD

NOT OVERLAP THAT OF THE EI3 BREAK-OUT BOARD.

IS NOT 0X50 OR 0X51. THIS IS TO ENSURE THE I2C ADDRESS RANGE DOES

CARE MUST BE TAKEN TO ENSURE DAUGHTER BOARD I2C EEPROM ADDRESS

WHEN DESIGNING A DAUGHTER BOARD THE ID EEPROM (24LC32) MUST BE ON I2C BUS 0.

SDP CONNECTORTHE SDP CONNECTOR IMPLEMENTS THE EI3 CONNECTOR SPECIFICATION STANDARD. THIS IS A STANDARD FOR USE ACROSS ADI AND CANNOT BE MODIFIED

9 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

0

100K

FX8-120P-SV1(92)

2.2K2.2K

10KR96

R100

R99

R101 R102

P10

SDP_RESET_OUT

SDP_SPI_NSS_CSDP_SPI_NSS_B

SDP_SPORT_DT0SDP_SPORT_TSCLK

SDP_SERIAL_INT

SDP_VIN

SDP_GPIO6

SDP_TMR_DSDP_TMR_BSDP_GPIO7

SDP_GPIO5SDP_GPIO3SDP_GPIO1

SDP_SPI/QUADSPI_SCK

IO_PWR_SUPPLY

SDP_SPORT_RSCLK

SDP_SPORT_TFS

SDP_UART_RX

SDP_SPORT_RFSSDP_SPORT_DR0

SDP_UART_TXSDP_RESET_IN SDP_EXT_BOOT

SDP_SPI/QUADSPI_NSS_ASDP_SPI_MOSI/QUADSPI_DIO0

SDP_I2C_SCLSDP_I2C_SDA

SDP_SPI_MISO/QUADSPI_DIO1

SDP_TMR_A

SDP_QUADSPI_DIO2SDP_QUADSPI_DIO3

SDP_GPIO4SDP_GPIO2SDP_GPIO0

MAIN_PWR_SUPPLY

SDP_SPI_NSS

MAIN_PWR_SUPPLY

+5V_CON 116

65

1

5

6259

72497348

87

89

3029 92

9032

88

3191

3837

85

39

8483

3433

82

64

35

41 8042 79

57

60

1002199

26 9527

7 1148 1139 112

10 111110

1213 10814 10715 10616 105

18 10319 10220 101

22

94

24 9725 96

120119

70

68676655

5453

5150

2

7447

764577447843

118117

115

109

104

98

93

86

81

75

69

6358

52

46

40

36

28

23

17

11

6

43

56

71

61

SPI_SEL_A_N

CLKOUT

NCNC

GNDGNDVIO

GNDPAR_D22PAR_D20PAR_D18PAR_D16PAR_D15

GNDPAR_D12PAR_D10

PAR_D8PAR_D6

GNDPAR_D4PAR_D2PAR_D0

PAR_WR_NPAR_INT

GNDPAR_A2PAR_A0

PAR_FS2PAR_CLK

GNDSPORT_RSCLK

SPORT_DR0SPORT_RFSSPORT_TFSSPORT_DT0

SPORT_TSCLKGND

SPI_MOSISPI_MISO

SPI_CLKGND

SDA_0SCL_0GPIO1GPIO3GPIO5

GNDGPIO7

TMR_BTMR_D

NCGND

NCNCNC

WAKE_NSLEEP_N

GNDUART_TXBMODE1RESET_IN_N

UART_RXGNDRESET_OUT_NEEPROM_A0NCNCNCGNDNCNCTMR_CTMR_AGPIO6GNDGPIO4GPIO2GPIO0SCL_1SDA_1GNDSPI_SEL1/SPI_SS_NSPI_SEL_C_NSPI_SEL_B_NGNDSERIAL_INTSPI_D3SPI_D2SPORT_DT1SPORT_DR1SPORT_TDV1SPORT_TDV0GNDPAR_FS1PAR_FS3PAR_A1PAR_A3GNDPAR_CS_NPAR_RD_NPAR_D1PAR_D3PAR_D5GNDPAR_D7PAR_D9PAR_D11PAR_D13PAR_D14GNDPAR_D17PAR_D19PAR_D21PAR_D23GNDUSB_VBUSGNDGNDNCVIN

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

SDRAM LEVEL TRANSLATORS

10 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

0

SN74LVC1GU04DCKR

2

0.1UF

74LVC8T245BQ,118

10K

10K

10K

1

0.1UF


0.1UF

0.1UF0.1UF

0.1UF0.1UF

0.1UF0.1UF

0.1UF0.1UF

74LVC8T245BQ,118

74LVC8T245BQ,118

1

6

5

4

74LVC8T245BQ,118

15

16

10

11

12

13

14

9

1

7

74LVC8T245BQ,118

4

2

74LVC8T245BQ,118

74LVC8T245BQ,11828

22

23

3

31

30

26

29

27

25

24

21

16

19

18

17

20

11

12

13

15

9

8

10

31

30

29

27

26

28

24

25

23

22

21

20

19

17

18

8

0

5

6

7

5

4

3

1

0

15

7

8

9

3

11

14

10

0

6

2

6

7

8

9

2

3

11

14

0

15

10

5

4

14

U27

R27

U9

U8

U7

U6

U5

U4

C46

C39C45C44C43C42

C41C40C38

C35C32

C36C33

C37C34

R28

R30

R29

U3

SDRAM_DATA_DIR_CTRL

SDRAM_N_WE

MAIN_PWR_SUPPLY

SDRAM_D<31:0>

SDRAM_N_RAS_TRNSLT

SDRAM_A<11:0>

MAIN_PWR_SUPPLY

TRNSLT_OE

SDRAM_A_TRNSLT<11:0>


SDRAM_DATA_DIR_CTRL


TRNSLT_OE


TRNSLT_OE

MAIN_PWR_SUPPLY

SDRAM_NBL2_TRNSLT

TRNSLT_OE



TRNSLT_OE

SDRAM_&_ARDUINO_PWR_SUPPLY MAIN_PWR_SUPPLY

SDRAM_DATA_DIR_CTRL



MAIN_PWR_SUPPLY

SDRAM_N_CAS_TRNSLT

SDRAM_DATA_DIR_CTRL

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

SDRAM_N_WE

SDRAM_SDCKE0SDRAM_SDCLKSDRAM_SDNE0

SDRAM_N_CASSDRAM_N_RAS

MAIN_PWR_SUPPLY


SDRAM_NBL1_TRNSLT

SDRAM_NBL3_TRNSLT

SDRAM_N_WE_TRNSLTSDRAM_SDNE0_TRNSLT

SDRAM_NBL0_TRNSLT

TRNSLT_OE

SDRAM_NBL3SDRAM_NBL2SDRAM_NBL1SDRAM_NBL0

SDRAM_SDCKE0_TRNSLT

TRNSLT_OE

SDRAM_DATA_TRNSLT<31:0>

SDRAM_A<15:14>

MAIN_PWR_SUPPLY

SDRAM_SDCLK_TRNSLT

TRNSLT_OE

4

5

1 3

2

24 23 1

PAD

22

13 12 11

2

1415161718192021

109876543

24 23 1

PAD

22

13 12 11

2

1415161718192021

109876543

24 23 1

PAD

22

13 12 11

2

1415161718192021

109876543

24 23 1

PAD

22

13 12 11

2

1415161718192021

109876543

24231

PAD

22

131211

2

1415161718192021

109876543

24231

PAD

22

131211

2

1415161718192021

109876543

24231

PAD

22

131211

2

1415161718192021

109876543

VCC

Y

GNDNC

A

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1

DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1

DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1

DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1

DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8


VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8


VCCA

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

SDRAM

11 11

<DESIGN_VIEW>


1:1

E02_049259

Sean Doyle

DNI0DNI0

0 DNI

0 DNI

0 DNI0 DNI

0 DNI

DNI0

DNI0

DNI0

DNI0

DNI0

DNI0

DNI0

DNI0

DNI0

DNI0

DNI0

0 DNI

DNI0

DNI0

DNI0

0 DNI

DNI0

DNI00 DNI

DNI0

0 DNI

DNI0

DNI0

DNI0

DNI0

0 DNI

0 DNI

DNI00 DNI

0 DNI

DNI0

DNI0

0 DNI

DNI0

0 DNI

0 DNI

DNI0

DNI0

0 DNI

DNI0

DNI0

DNI0

0 DNI

DNI0

DNI0

0 DNI

DNI0

DNI0

0 DNI


0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF

0.1UF0.1UF0.1UF

3

2

7

19

20

22

23

18

17

16

11

8

6

1

0

31

12

29

30

28

24

18

21

22

19

13

23

1616

12

17

13

11

10

8 8

11

10

9

5

3

2 2

6

4

15

14

11

10

9

8

7

6

5

4

3

1

0

15

14

8

7

0

1

15

14

11

10

9

8

7

4

30

29

28

27

26

25

24

21

15

14

13

10

9

5

4

30

31

28

27

25

24

26

23

22

20

19

21

18

17

15

14

12

11

9

7

6

5

4

2

1

3

0

31

29

27

26

25

20

15

14

10

9

6

7

5

4

3

2

1

0

6

5

3

1

0

2

MT48LC4M32B2B5-6AXIT:L

C131C129C127C125C123C121C119

C132C130C128C126C124C122C120

R142

R131

R130

R143

R144R132

R139R128

R127

R140

R141R129

R136R125

R124

R137

R138R126

R134

R133

R135

R121

R122

R123R145

R161

R162

R163

R164

R165

R167

R166

R168

R169

R170

R171

R172

R173

R174

R176

R175

R146

R147

R149

R148

R150

R151

R152

R154

R153

R155

R156

R157

R158

R159

R160

U25

SDRAM_NBL0_TRNSLTSDRAM_NBL0SDRAM_NBL1_TRNSLTSDRAM_NBL1

SDRAM_NBL3_TRNSLTSDRAM_NBL3SDRAM_NBL2_TRNSLTSDRAM_NBL2

SDRAM_N_WE_TRNSLTSDRAM_N_WE

SDRAM_SDCLK_TRNSLTSDRAM_SDCLK

SDRAM_N_RAS_TRNSLTSDRAM_N_RAS

SDRAM_SDCKE0_TRNSLTSDRAM_SDCKE0

SDRAM_SDNE0_TRNSLTSDRAM_SDNE0

SDRAM_N_CAS_TRNSLTSDRAM_N_CAS








SDRAM_A_TRNSLT<11:0>SDRAM_A<11:0>

SDRAM_A<15:14>

SDRAM_D<31:0>


SDRAM_NBL3_TRNSLTSDRAM_NBL2_TRNSLT

SDRAM_SDCLK_TRNSLTSDRAM_SDCKE0_TRNSLT

SDRAM_SDNE0_TRNSLT

SDRAM_N_RAS_TRNSLT

SDRAM_NBL1_TRNSLT

SDRAM_N_CAS_TRNSLTSDRAM_N_WE_TRNSLT

SDRAM_NBL0_TRNSLT

K8

P8P3N1M1L9E9D1C1B8B3R3L3F1A3

P7P2N9M9

L1E1D9C9B7B2R7L7F9A7

J9

K2

K3H7H3E7E3

F2F8K1K9

E2D3D2B1C2A1C3A2A8C7A9C8B9D8D7E8R2N3R1N2P1M2M3L2L8M7M8P9N8R9N7R8

J8

J1J2

K7

H8J7

H9G7J3H2H1G3G2G1F3F7G9G8

DQ2

DQ0VDD

VSS

DQ15

DQ13

DQ4

VSSQ

VDDQ

VSSQ

VDDQ

DQ11

VDDQ

DQ3

DQ1

DQ14

DQ12

VSSQ

VDDQ

DQ5DQ6

DQ9DQ10

VSSQ

VSSQ

DQ7

VDD

VSS

DQ8

VDDQ

DQM0

WE#CAS#

NC

NU

DQM1

RAS#

CS#

BA0

A9

CKECLK

A11

BA1

NCNC

A8A7

A1A0

A10

A6A5A4

VDD

DQM2

A2A3

DQM3

VSS

VSSQ

DQ16

NCNC

DQ31

VDDQ

VDDQ

DQ18DQ17

DQ30DQ29

VSSQ

VDDQ

DQ20

DQ22

DQ25

DQ27

VSSQ

DQ19

VSSQ

VDDQ

VSSQ

VDDQ

DQ28

DQ21

DQ23

VDD

VSS

DQ24

DQ26

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Documents

THE EQUIPMENT SHOWN HEREON MAY BE ......Q2 C20 C23 E2 R26 R180 R24 C29 C25 C27 F2 C31 P2 C1 R209 R208 R207 R206 C2 C11 C16 C7 C19 C5 C10 C12 R1 R2 C15 C14 C13 C6 C3 C4 C8 C9 C17 C18