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A.Marchioro /EP
The CMS Tracker Control System
A. Marchioro, G. Cervelli, C. Ljuslin, G. Magazzu, E. Murer, C. Paillard (CERN)
July 4, 2002
Tracker Control System - July 2002 2A.Marchioro /EP
Tracker R-O: General Architecture
APVs
CLK - T1
CCU
DCU
Det
PLL-Delay
A/DMemory
TTCrxI2
CFED
FEC
IV
TTCrx
PCIIntfc
CLK
& T
1
A/D
Temp
Front-endModule
CCUM
FEC ctrl
DataPathControlPath
toDAQ
LVDSMUX
LVDSBUF
LD
Tracker Control System - July 2002 3A.Marchioro /EP
IC components
uCCU25uDCU25uTTCrx-DuPLL25uLDuRX40uLVDSBUF and LVDSMUX
Tracker Control System - July 2002 4A.Marchioro /EP
Cards
uFECuCCUMuTSC
Tracker Control System - July 2002 5A.Marchioro /EP
… for each item
uHardware– Architecture, Functionality and some details of
implementationuPackaging
– Selected packagesuSoftware
– Drivers– Development environment
uDocumentation
A.Marchioro /EP
CCU and ring protocol
Tracker Control System - July 2002 7A.Marchioro /EP
Architecture of Network
ApplicationASICs
CCU
ApplicationASICs
CCU
ApplicationASICs
CCU
FEC
Internal protocol
User accessible protocol:I2C, Memory, Parallel, JTAG
Tracker Control System - July 2002 8A.Marchioro /EP
Rationale
uNeeded to be able to carry slow control, trigger and timing (40 MHz clock)
uR/WuAs close as possible to a “standard”
protocoluSupport for redundancyuAble to adapt to several protocols of
different front-end chips
Tracker Control System - July 2002 9A.Marchioro /EP
Architecture for Redundancy
CCUM-1
LVDS/CMOS
CC
U
Primary
Secondary
CC
U
CC
U
CC
U
LVDS/CMOS LVDS/CMOS LVDS/CMOS
CCUM-2 CCUM-3 CCUM-4
B
A
B
A
Tracker Control System - July 2002 10A.Marchioro /EP
CCU-M Cabling with Redundancy (v.5)
CCU
In-A Out-A
In-B Out-B
CCU
In-A Out-A
In-B Out-B
CCU
In-A Out-A
In-B Out-B
CCU
In-A Out-A
In-B Out-BXA
B
A
B
Tracker Control System - July 2002 11A.Marchioro /EP
CCU: Communication and Control Unit
I2C Master
I2C Master
LinkController
Node Controller
SCLSDATA
D[0:7] A[0:15] R/W CS[1-2]*
DO(A)
CLKI(A)
Local Bus
DI(A)
DO(B)
DI(B)
Clock Distribution CLKI(B)
CLKO(A)
CLKO(B)
ST1ST2ST3ST4
TriggerDecoder
Trigger Counter& other timing logic
16 x
I2C
Bus
es
PIA
Memory BusInterface
PA[0:7] PB[0:7] PC[0:7] PD[0:7]
Ext Reset*
JTAGMaster
JTAGSlave
Reset*
Alarms
Interrupts[0-3]*
PLL Clk Select
Tracker Control System - July 2002 12A.Marchioro /EP
CCU-M Cabling with Redundancy (v.5)
CCU
Data In-Port A
Data In-Port B Data Out-Port B
Data Out-Port A
Clk In-Port A
Clk In-Port B
ClkIn_A ClkOut_A
DIn_A DOut_A
PLL_Clk
DOut_B
ClkOut_BClkIn_B
DIn_B
PLLCKSEL
LVDSMUX
Tracker Control System - July 2002 13A.Marchioro /EP
Clock to CCU
CLK
T1
CLK+T1
~ 25 ns
Tracker Control System - July 2002 14A.Marchioro /EP
Clock to CCU
Tracker Control System - July 2002 15A.Marchioro /EP
NRZI Coding
u Non-Return-Zero-Invertedu 40 Mbit/sec with 20 MHz bandwidthu “1” signaled by level changeu “0” signaled by no level change
1 1 1 1 0 0 0 1 0 1
25 ns
Tracker Control System - July 2002 16A.Marchioro /EP
CCU Ring protocol
4 bit Binary Hex Value
5 bit Symbol
0000 0 11110
0001 1 01001
0010 2 10100
0011 3 10101
0100 4 01010
0101 5 01011
0110 6 01110
0111 7 01111
1000 8 10010
1001 9 10011
1010 A 10110
1011 B 10111
1100 C 11010
1101 D 11011
1110 E 11100
1111 F 11101
Control Symbol Code Comment
Idle 11111 Idle
J 11000 In SOF field
K 10001 in SOF field
H 00100 Special
R 00111 Reset
S 11001 Set
T 01101 Termination
Tracker Control System - July 2002 17A.Marchioro /EP
Coding on line
Token: “JKTRRR”
Tracker Control System - July 2002 18A.Marchioro /EP
LAN Protocol (1)
uRing-like topology– Circulating token indicates bus available– Source waits for token:
» removes token, injects data packet– Packet circulates, passed by all nodes– Destination copies packet in, sets “S” symbol– Packet returns to source, removed by source– Source inserts new token
Tracker Control System - July 2002 19A.Marchioro /EP
LAN Protocol (2)
uAll nodes can generate packetsuFor simplicity:
– Only FEC can perform network supervision» inserts first token» monitors token integrity» receives all data packets from CCUs
uFEC requires CPU for protocol manag.
Tracker Control System - July 2002 20A.Marchioro /EP
LAN protocol: Packet Format
SOF Dest Src Length Data CRC EOF
Universal
Channel SpecificCmd TR# Addr DWCh#
(Example for an I2C byte write)
Tracker Control System - July 2002 21A.Marchioro /EP
LAN Protocol (3): Transaction example
uTransaction from FEC to CCU– FEC sends packet– CCU receives packet and sets “S” symbol– CCU directs data portion to channel– Channel performs action– Optional: Channel sends ACK packet to CCU
specifying TR#
Tracker Control System - July 2002 22A.Marchioro /EP
LAN Protocol (4): Addressing
uCCU Address allocation» FEC has address “00”» Special Broadcast address: “0x80”» Up to 127 CCUs on ring
uChannel Addressing» 0: CCU Node controller» 0x10-0x1f: I2C channels» 0x20: I2C broadcast» 0x40: Memory channels» 0x30-0x33: PIA channel» 0x50: Trigger distribution channel» 0x60: JTAG master controller» 0xfe-oxff: Special interrupt channel
Tracker Control System - July 2002 23A.Marchioro /EP
I2C Protocol (back-to-back @ 100KHz)
Tracker Control System - July 2002 24A.Marchioro /EP
CCU25 – Memory protocol
ADDRESS<7:0>
DATA<15:0>
W*
CS*
ADDRESS<7:0>
DATA<15:0>
W*
CS*
Write cycle
Read cycle
Tracker Control System - July 2002 25A.Marchioro /EP
Memory transfer
CS*
RW*
Address
Data
Tracker Control System - July 2002 26A.Marchioro /EP
Parallel Port Protocol
u4 8-bit bi-directional ports per CCUuArchitecture like Motorola PIA
– 8 Programmable direction data lines– 1 input strobe– 1 output strobe
Tracker Control System - July 2002 27A.Marchioro /EP
PIA port after Reset
Reset to CCU
I/O line changingdirection
Tracker Control System - July 2002 28A.Marchioro /EP
JTAG Master port
uSimple master portuLimited intelligence on controlleruEntire JTAG sequence programmed from
FECuNeed special ring packet uNeed special software support from FEC
Tracker Control System - July 2002 29A.Marchioro /EP
CCU25 in 0.25 µm
uFeatures» 6.3x6.3 mm2, 3 metals» Fully synthesized (Synopsys)» Three independent clock trees» Pad-Limited» Slew rate limited IO pads» IDD = 100 mA @ 2.5V» 196 pin fpBGA
array 14x14 with1 mm pitch
Tracker Control System - July 2002 30A.Marchioro /EP
CCU25-Proto card
Tracker Control System - July 2002 31A.Marchioro /EP
CCUM with 12 I2C channels for ROD proto
Tracker Control System - July 2002 32A.Marchioro /EP
CCU25 redundancy features for SEU
uNode controller: 3 x logic + votinguData path: parity on all registersuControl FSM: One-Hot + Auto-ResetuSeveral status SEU registers + counters
A.Marchioro /EP
DCU
Tracker Control System - July 2002 34A.Marchioro /EP
Monitoring with DCU
uDetector Control Unit– Generic Voltage, Current and Temperature
Monitoring– 12 bit Analog to Digital Converter– I2C Interface– Rad-Tolerant– Low-Power
Tracker Control System - July 2002 35A.Marchioro /EP
Detector Monitoring
AI4
AI7AI5
IOUT
DCU
APV
APV
1M
1M
1M
1M
Si DETECTOR
HVSi Strip
Si Strip
Si Strip
Si Strip
RsRtR
R
AI2AI1
I2Cbus
Rs = 100 ΩRt (25 °C) = 10 KΩRt (-20 °C) ~ 80 KΩR = 100 KΩRref ~ 120 KΩ
I2CaddReset
Rref
RES
AI6
AI3
R
R
2.50V1.25V
Rt Rt
20uA10uA
Tracker Control System - July 2002 36A.Marchioro /EP
DCU Architecture
12-bit ADC
BandgapReference
I2C
In
terf
ace
Temp. Sensor
Input AI7
I2C Bus
VREF
Ext. Reset
IREF
RES
I2C Address
For testing only
Input AI1
20uA Source
10uA Source
Input AI8
ID Number
Tracker Control System - July 2002 37A.Marchioro /EP
I2C Registers
u Internal addresses:– Control Register CREG (r/w - reg_add = 000)
» CREG[2:0] ⇒ select the ADC input channel» CREG[3] ⇒ selects the ADC operating mode» CREG[6] ⇒ performs a “software” reset (an external reset pin is also provided)» CREG[7] ⇒ starts an ADC acquisition
– Status & Data High Register SHREG (read only - reg_add = 001)» SHREG[3:0] ⇒ The 4 MSBs of the result of the last ADC acquisition» SHREG[6] ⇒ A majority error (SEU) occurred» SHREG[7] ⇒ The DCU is in the IDLE state
– Data Low Register LREG (read only - reg_add = 011)» LREG[7:0] ⇒ The 8 LSBs of the result of the last acquisition
– Auxiliary Test Register AREG (r/w - reg_add = 010) [DO NOT USE !]– Test Register TREG (r/w - reg_add = 100) [DO NOT USE !]– ID Registers (read only - reg_add = 111-110-101)
» Unique 24-bit serial number in each chip
Tracker Control System - July 2002 38A.Marchioro /EP
DCU Layout (proto 1)
ADC analog blocks
ADC digital blocks & I2C interface
Bandgap
Tracker Control System - July 2002 39A.Marchioro /EP
ADC Test Results (1)
u Gain ~ 454 mV/LSB u -1LSB < INL < 1LSB
ADC Gain and INL (“low input range” mode: 128 input voltages in the range GND < Vin < 1.25V)
A.Marchioro /EP
PLL
Tracker Control System - July 2002 41A.Marchioro /EP
Timing Distribution PLL-Delay chip
CLK &T1 extract
DelayLines
I2CSlaveInterface
PLL
SCLSDA
CLK
T1
I2C_Add
Functional view
Tracker Control System - July 2002 42A.Marchioro /EP
PLL25 Detailed architecture
RC-CFilter
I2CSlaveInterface
PFD /PD
SDA, SCL
CLKI2C_Add
Charge Pump
Differential 12 Stages VCO
MUX
Calibration Logic
V to IConv
V and IReference
Lock Control
Reset*
Tracker Control System - July 2002 43A.Marchioro /EP
On Resets
uPower-on and master Reset is distributed with CMOS (valid low) level from the Digital Opto-Hybrid
uTracker uses “101” sequence for re-synchronization
uAt the moment the FEC ignores “channel B”– Mod is under consideration, please advice!
A.Marchioro /EP
LLD
Tracker Control System - July 2002 45A.Marchioro /EP
LD0LD0 LD1LD1 LD2LD2
+ + +
-Id
c0-I
dc0
-Id
c1-I
dc1
-Id
c2-I
dc2
V0-
V2+
V2-
V0+
V1+
V1-
I2C
Inte
rfac
eI2
C In
terf
ace
to lasers
SCL
SDA
from Mux
Linear Laser Driver: Block Diagram
Adr
(5)
Reg
(3)
Bias(7)
Gain (2)
100 Ω100 Ω 100 Ω
•MANUAL / DATASHEET: available on http://cern.ch/proj-lld
Tracker Control System - July 2002 46A.Marchioro /EP
Linear Laser Driver (LLD): Layout
• 0.25µm CMOS (2.5V)
• Size: 2.00 x 2.00 mm
• Modularity: 3 channels
• Fully differential architecture
• Common anode biasing mode
• Linearity 1% (active bulk)
• I2C interface (tripled logic)
• Programmable gain/pre-bias
• On-chip pre-bias generation up to 55mA
• Individual channel masking
I2out VDD VSS I1out VDD VSS I0out VDD
V2+ V2- VDD V1+ V1- VSS V0+ V0-
I2CA2
I2CA3
I2CA4
I2CA5
I2CA6
DRES6
VDD
VSS
PONb
RESb
SDA
SCL
DRES4
DRES5
VDD
VSS
Tracker Control System - July 2002 47A.Marchioro /EP
0 16 32 48 64 80 96 112 1280
10
20
30
40
50
60
I2C REGISTER
PRE-BIAS CURRENT [mA ]
σ = -3.0σ = -1.5σ = 0σ = +1.5σ = 3.0
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-10
-8
-6
-4
-2
0
2
4
6
8
10
DIFFERENTIAL INPUT VOLTAGE [V]
MODULATION CURRENT [mA ]
LLD: Transfer CharacteristicLASER PRE-BIAS CURRENT
ANALOG RANGE
DIGITAL RANGE
TRANSFER CHARACTERISTIC
• Programmable pre-bias: 55mA (7bits)
• Switcheable gains: 5mS, 7.5mS, 10mS, 12.5mS
differentσ’s
LSB=0.45mA
Tracker Control System - July 2002 48A.Marchioro /EP
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-8
-6
-4
-2
0
2
4
6
8x 10
-3
DIFFERENTIAL INP UT VOLTAGE [V]
MODULATION CURRENT [mA]
VCM = -625mVVCM = 0VVCM = +625mV
-0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
DIFFERENTIAL INPUT VOLTAGE [V]
INTEGRAL LINEARITY DEVIATION [% ]
LLD: Gain and Linearity
ILD < 1%
• Linear operating range: ±300mV
• Integral linearity deviation: <0.5% (Vcm=0)
differentσ’s
differentσ’s
TRANSFER CHARACTERISTIC LINEARITY
A.Marchioro /EP
RX-40
Tracker Control System - July 2002 50A.Marchioro /EP
RH Receiver for digital opto-link
preamplifier L.A. L.A. L.A. L.A.
B.F.
LVDSTx
sf
Resetblock
in
reset
out
PINdiode N
o_si
gnal
_out
Switchbox
RX-40
Tracker Control System - July 2002 51A.Marchioro /EP
Reset from DOH
A.Marchioro /EP
Small chips
Tracker Control System - July 2002 53A.Marchioro /EP
LVDSMUX• Used next to CCU25 for clock regeneration and distribution to ROD etc.
•0.25µm CMOS (2.5V)
• Size: 2.00 x 2.00 mm
•Packaged in TQFP32 (7*7 mm2)
Tracker Control System - July 2002 54A.Marchioro /EP
LVDSBUF• Used on mother-cables and petals
•One LVDS + 1 CMOS repeater
•Slew rate control on CMOS
•Size: 2.00 x 2.00 mm
•Packaged in SOIC-8L
Tracker Control System - July 2002 55A.Marchioro /EP
Built-in protection against SEU
uCCU25– Measures: 3x redundancy in node controller– Parity in data path and one-hot FSM
uPLL25– 3x redundancy on 99% of chip
uDCU– 3x redundancy on I2C interface
uLD– 3x redundancy on I2C interface
Tracker Control System - July 2002 56A.Marchioro /EP
SEU Test on Componentsu Irradiation with 200 MeV protons at
PSI in December 2001u Test card housing 4 CCUs,
+ 4 x (LD + DCU + PLL25 + LVDSMUX)u Test procedure:
– Configure normally running ring (remote FEC)
– Loop reading status registers from all chips waiting for SEU events
– Monitor IDD currents on all chips with ADC on DCU itself
PLL25
LVDSMUX LD
DCU
Tracker Control System - July 2002 57A.Marchioro /EP
CCU25: production testing
uAbout 2,000 chips will be packageduTest vectors from design verification
vectors to be translated to the IMS digital tester
uTest-fixture card with ZIF socket for fpBGA196 for IMS is being done
uTest time < 1 sec per deviceuTotal test time when ready < 2 weeks
Tracker Control System - July 2002 58A.Marchioro /EP
DCU Production testing (1)
uNeed one DCU per FE hybriduNot only a functional test but need also
storing of calibration parametersuTest on IMS tester probably too slow
– Storing of calibration parameters from IMS too cumbersome
uNeed dedicated test carduCalibration in two phases
Tracker Control System - July 2002 59A.Marchioro /EP
DCU Production testing (2)
D/A A/DA-In
DCU
I2Cbus
IOut
RTh
Few points on Analog InputsNeed to take two
measurements at different temperatures
Few points on Analog InputsNeed to take two
measurements at different temperatures
RRef
Tracker Control System - July 2002 60A.Marchioro /EP
DCU Production testing (3)
uTwo steps approach– While on test card characterize each DCU for
» I2C functionality» Analog inputs » Current references
– Absolute voltage calibration and temperature calibration only when mounted on hybrid
» Store DCU parameters in DB at this stage
A.Marchioro /EP
FEC
Tracker Control System - July 2002 62A.Marchioro /EP
Current FEC Block diagram
TTCrx
BusIntfc(PLX)
FEC logic (FPGA)
CLK -T1Data PCI
FIF
Os
Tracker Control System - July 2002 63A.Marchioro /EP
Current Version
uFEC– Available in PCI-
PMC format» Electrical I/O» Optoelectronics on
separate add-on board
Tracker Control System - July 2002 64A.Marchioro /EP
Production version: Modular approach
VME-9U (~360x400mm)
PMC-PCI
PCI
VME-XX
PCIAdapter
VMEInterface
TTCrx
TTCrx
Tracker Control System - July 2002 65A.Marchioro /EP
Specifications for final FEC
uModularity of x1 (lab use) or 8x (experiment)u8 ways matches exactly one fiber-cableuTTCrx on carrier carduSplit the internal FEC bus
– All components and TX-RX FIFOs still on module– PCI or VME interface on carrier card
uOpto-electronics on module
Tracker Control System - July 2002 66A.Marchioro /EP
Optical component
u8 ways transceiver
uMounted directly on FEC module
uCan’t be used with electrical version !
A.Marchioro /EP
TSC
Tracker Control System - July 2002 68A.Marchioro /EP
Trigger Sequencer Card
A solution for test stations trigger management
Tracker Control System - July 2002 69A.Marchioro /EP
• Wait for any trigger
• Filter (gate, N clocks between triggers, count)
• Internal and external clock
• Internal and external triggers
• Make special sequence for APVs (calibration 110, reset 101)
• Electrical output for ADCs
• Electrical output for APVs
• Optical output for FEC
Documentation available at ftp://lyoftp.in2p3.fr/cms/Tsc/tsc02.pdf or .doc
TSC features
Tracker Control System - July 2002 70A.Marchioro /EP
TSC simple block diagram
Tracker Control System - July 2002 71A.Marchioro /EP
TSC block diagram
Tracker Control System - July 2002 72A.Marchioro /EP
TSC functionnal block diagram
A.Marchioro /EP
CCUM
Tracker Control System - July 2002 74A.Marchioro /EP
UTRI and CCUM0
Tracker Control System - July 2002 75A.Marchioro /EP
Documentation
uDoc on all components is posted on: CMS Tracker Controlhttp://cern.ch/CMSTrackerControl
u Integration results in:CMS Electronics Integrationhttp://cern.ch/CMSTEI/index.htm