The 8255 allows the microprocessor to communicate with the outside world through three programmable 8-bit wide I/O ports The PC uses a few 82C55 (in the

• The 8255 allows the microprocessor to communicate with the outside world through three programmable 8-bit wide I/O ports

• The PC uses a few 82C55 (in the chip set) to control the keyboard, speaker, and parallel port

• The 8255 PPI is available in DIP or surface mount forms

• Also implemented as functions within modern interface chip sets

The 82C55 PPIPPI = Programmable Peripheral Interface

A

B

C

3 programmable 8-bit I/O ports: A, B, C

Port A + Upper half of C = Group A(12 bits)

Port B + lower half of C = Group B(12 bits)

82C55 DIP Version

Data Bus

2-bit Address I/P(select port or Command register for Read or Write)

CS Input(low)

Read/Write Control

On the PC: Two 82C55s- One 82C55 occupies4 I/O ports 60H-63H:Handling Keyboard, timer, speaker, etc.

- One 82C55 occupies 4 I/O ports 378H-37BHParallel printer port

RESET initializes the PPI to operate in mode 0 & all 3 ports as inputs at power up.

With all ports as input ports, this avoids damage to the device at Power up

2 Groups 12-bit groups A, B

Similar to a 4-byte RAM

B

I/O Port Assignments

• Group A is Port A and upper ½ of Port C (PC7-PC4).

• Group B is Port B and lower ½ of Port C (PC3-PC0).

A1 A0 Function

0 0 Port A

0 1 Port B

1 0 Port C

1 1 Command RegisterWriting into this registerprograms the various ports to operate in various modes and be used as either inputs or outputs

100

100

001

80386SX Processor

A7 A6 A5 A4 A3 A2 A1 A01 1 0 0 0 0 0 0 = C0H Port A1 1 0 0 0 0 1 0 = C2H Port B1 1 0 0 0 1 0 0 = C4H Port C2 1 0 0 0 1 1 0 = C6H Comnd

Register

A1 A0 Inputs on 82C55

Address from80386SXmicroprocessor

Address from microprocessor

Select PPIAt decoded mP address

Programming the 82C55

Using one internal register• If bit 7 = 1 select format for Command Byte A• If bit 7 = 0 select format for Command Byte B

Bit 7 = 1: Command Byte A:• Programs Groups A and B (as defined in terms of ports A, B, C - previous slide): - as either inputs or outputs - in either modes 0, 1, or 2

Bit 7 = 0: Command Byte B:• Sets (to 1) or Clears (to 0) the specified one of 8 bits of port C (in modes 1 and 2)

Only for mode 0

Program

Program

8255 Modes• Mode 0 (for groups A & B)- the most commonly used mode:

All 12 bits of the group are simple inputs or simple latched outputs

• Mode 1 (for groups A & B)- is used occasionally to provide handshaking to an I/O device and operate asynchronously with the device. Most Port C bits are dedicated for handshake functions for the operation. A few are controlled separately using the Command byte B format for handshaking I/O.

• Mode 2 (for group A only- Group B not used)- is a bidirectional mode for Port A only (Port B is not used). Port C provides handshaking signals.

Data

Data

Data

Control, e.g. Busy, Strobe, etc.

8255 Modes

Not Used

Control:HandshakingFor the data port

When O/P,Set or Reset Using Command Byte B

Programming the 82C55

• To program the command

register of the 82C55 and select operation use command byte A

• For example, to program all the ports as outputs and in mode 0 (the most common mode) use:

MOV AL,80H

MOV DX,COMMAND_PORT

OUT DX,AL

= C6H in slide 50

Mode 0 Application: 7-Segement Display

Common

SegmentDriver

7-Segement Display

Select Segments: Switched Resistors to GND

Anode

Cathode

Select Segments: Switched Resistors to Vcc

CA

CC

Vcc

GND

7-Segement Display

Anode

Cathode

Segment Data (1 byte)for each character

Multiplexed 7-Segement DisplayMotivation for MUXing:- Reduce the number of segment drivers by a factor of n

CommonTo segment on all Digits

SequentiallyTurn ON one digit at a time

Recommended rate: 100 – 1500 times per sec

n = 8Digits

B: O/P Port:Select # Displayed

A: O/P Port:Segment dataFor selected digit

B: O/P Port:Select digit To be displayed

Digit transistor switchControlled by Port B bit,e.g. Tr 1

Vcc

7 Segment data transistor switchesControlled by Port A bits, e.g. Tr 2

GNDPLD for 14-bit I/O address (A15-A2) + IO/#M decoding

Address decoding is similar to that of a 4-byte Read/Write memory

Multiplex the eight digit displays (only one is ON at a time)

1 turns segment ON

0 turns digitdigit ON

Most Significant (MS) Digit

. . . . . . 1 digit

Tr 1Tr 2

library ieee;use ieee.std_logic_1164.all;entity DECODER_11_21 isport (

IOM, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2: in STD_LOGIC;

D0: out STD_LOGIC);end;architecture V1 of DECODER_11_17 isbegin

D0 <= not IOM or A15 or A14 or A13 or A12 or A11 or not A10 or not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2;

end V1; A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A00 0 0 0 0 1 1 1 0 0 0 0 0 0 X X 0700 Port A

0701 Port B0702 Port C0703 Control Register

82C554 I/O ports:

On chipSelection

14-bit address decodingUsing PLD

PLD Program for Address Decoding

Total: 16-bit I/O address

; Program the 82C55 for Port A and Port B are output ports in mode 0MOV AL, 80H ; 80H Data into ALMOV DX, 703H ; Address of Command Port into DXOUT DX, AL ; Write 80H into Command Port

; ; to program PPI; An assembly language procedure that multiplexes the 8-digit display.; This procedure must be called often enough for the display to appear stableDISP PROC NEAR USES AX BX DX SI

PUSHFMOV BX,8 ;load counter BX with # of display digitsMOV AH,7FH ;load initial digit selection pattern to enable MS digit (01111111)MOV SI,OFFSET MEM - 1 ;Load SI with offset (MEM) - 1MOV DX,701H ;address Port B (for Port A: decrement DX)

;Sequentially display all 8 digits starting with MS digit.REPEAT

MOV AL,AHOUT DX,AL ;send digit selection pattern to Port BDEC DX ;Address Port A (to send Digit Data)MOV AL,[BX+SI] ;Load digit data from memory into ALOUT DX,AL ;send digit data to Port ACALL DELAY ;wait 1.0 ms leaving displayed digit ONROR AH,1 ;adjust selection pattern to point to next digitINC DX ;Address port BDEC BX ;decrement counter for data of next digit.

.UNTIL BX == 0POPFRET

DISP ENDP

.

.

.MEM

BX

MEM+7 MS Digit

8 bytes ofDigit DataIn memory

LS Digit

Procedure for 1 ms delay, e.g. a loop of instructionsi.e. digit remains ON for 1 ms before moving to next

; Delay Loop

DELAY PROC NEAR USES CXMOV CX, XXXX ; XXXX determines delay, = Delay required / loop exec time

D1:LOOP D1RET

DELAY ENDPLoop execution time is calculated from instruction data and the clock frequency.

An 80486 executes “LOOP D1” in 7 clock cycles

With a 20 MHz clock, loop exec time = 7 x 50 = 350 ns

XXXX = 1ms/350ns

Display Flashing Rate:

- Assume the DISP Procedure is called continuously- Ignore loop execution times relative to delay time (e.g. 350 ns << 1 ms)

. . . Digit Displayed 8 7 2 1

. . .

7 2 1 8

1 ms

8 ms

. . .

Flashing rate = 1/8 ms = 125 Hz

DISP Proc DISP Proc

Stepper Motor InterfaceWk 10

• Stepper motor is digital in nature

• It rotates in a sequence of discrete steps controlled by sequentially energizing a set of coils (windings)

• Step angles vary from 1 to 15 depending on precision required (and cost)

• N Pole lies between the two energized coils• Rotation Direction: Anti-clock wise• Step angle: 90

45135

225 315

2 coils driven at a time

0 0 1 1

ROL: Motor rotates anticlockwise

Anti-clockwise Rotation

ROR reverses the direction ofMotor rotation

Darlington pairsfor driving high load currents Anti-surge diodes

33H or 66H or CCH or 99HPOS

Current angular Position stored at location POS (in memory)

33H = 0011001166H = 01100110CCH = 1100110099H = 10011001

ROL ROR

Anti-Clockwise Clockwise

ROL

1 activates coil

Rotate instruction operates on whole byteWe want to rotate half the byte duplicate pattern!

PORT EQU 40H;An assembly language procedure that controls the stepper motorSTEP PROC NEAR USES CX AX

MOV AL,POS ;get positionOR CX,CX ;set flag bitsIF !ZERO?

.IF !SIGN? ;if not sign Rotate left.REPEAT (anti clockwise)

ROL AL,1 ;rotate step leftOUT PORT,ALCALL DELAY ; wait 1 ms for motor to move

.UNTILCXZ.ELSE

AND CX,7FFFH ;make CX positive.REPEAT

ROR AL,1 ;rotate step rightOUT PORT,ALCALL DELAY ;wait 1 ms for motor to move

.UNTILCXZ.ENDIF

.ENDIFMOV POS,AL ; Save POSN for next stepRET

STEP ENDP

If CX = 0 QuitNo rotation required

CX has:- Sign of rotation 0: ACW 1:CW- # of steps

e.g. 0000H (0) 0005H (5,ACW) 8007H (7,CW)

CX Positive: Rotate Anti-clockwise

CX Negative: Rotate Clockwise

Not

At exit of proc, CX is changed

Interfacing a 4x4 Key Matrix

Row Inputs

Column Outputs

• With no keys pressed, all row inputs are 1’s due to the pull up resistors connected to Vcc• Column outputs are sequentially scanned as 0’s• If key (X,Y) is pressed, it connects the scanning 0 from column X output to row Y input. If no other key is pressed on the same column, this allows the pressed key to be identified.

X

Y

0 2. Scan columns with one 0 to locate a pressed key

O/P

I/P

0 0 0 01. All 0’sTo checkFor any Press/Release

Scan for the next key pressedand locate its column

Wait for any remaining pressed keys to be Released

Wait for next key to be Pressed to determine it

Scan again after things have settled, and determine coordinates (row, column) of pressed key

Software DebounceOf Switch Release

Software DebounceOf Switch Press

Use key position determinedTo get its correspondingCode stored in a lookup table In memory

Still

Here, column is known

row

Determine row of key pressed(look for 0 bit in read data)

into CF

Read Input Pattern

;assembly language version;;KEY scans the keyboard and returns the key code in AL.

COLS EQU 4ROWS EQU 4PORTA EQU 50HPORTB EQU 51H

KEY PROC NEAR USES CX BXMOV BL,FFH ;compute row maskSHL BL,ROWSMOV AL,0

OUT PORTB,AL ;place all zeros on Port B.REPEAT ;wait for release

.REPEATCALL SCAN

.UNTIL ZERO?CALL DELAY10 ; Release debounceCALL SCAN

.UNTIL ZERO?

.REPEAT ;wait for key press (to be determined).REPEAT

CALL SCAN.UNTIL !ZERO? ; (not zero, i.e. not = FF)CALL DELAY10 ; Press debounceCALL SCAN , scan again after things have settled

.UNTIL !ZERO?MOV CX,00FEH.WHILE 1 ;find column

MOV AL,CLOUT PORTB,ALCALL SHORTDELAY ;Wait till data outputted to PortB have settled! CALL SCAN.BREAK !ZERO? ;Key found at this column- Quit WHILE1!ADD CH,COLS ;Key not found at this row- move on to next row – add COLS to CHROL CL,1 ;AL = 11111101 on 2nd trial

.ENDW

.WHILE 1 ;find row from pattern Read into PortA in SCANSHR AL,1.BREAK .IF !CARRY? ; LSB of AL is shifted into the carry flag by SHR! So we stop on 1st zero bitINC CH ; for each shift until row is found

.ENDW

MOV AL,CH ;get key code into AL: AL = CH = (COLS) X + Y = 4 X + Y; X = 0, 1,..,3 , Y = 0, 1,.., 3RET

KEY ENDPSCAN PROC NEAR

IN AL,PORTA ;read rowsOR AL,BLCMP AL,0FFH ;test for no keysRET

SCAN ENDP

• Program the 8255 for: Port A: Input Port B: Output• Size in ROWS, COLS can be set, up to 8 x 8, here 4 X 4BL = F0, for rows = 4

Mask for Oring in SCAN

BL: 11110000 = F0H AL: XXXX1111 (No Keys Pressed)Oring: 11111111 = FF

Keep calling SCANUntil FF (no key pressed)i.e. wait for key release

Keep calling SCANUntil (Not FF) (a key pressed)i.e. wait for key stroke

DetermineX,Y of Pressed Key as NumberIn CH AL

AL = 11111110

1st Column

(for a key pressed on row 3)After SCAN:AL = XXXX1011

Column # Row #

AL from SCAN

ASCII?

ZERO: No Pressed!ZERO: Pressed

SHR into Carry

X (Column)

Y(row)

• Ports A and/or B used as latching input ports to store data temporarily from external devices before processor is ready to take the data in.

• Port C provides the control (handshake) bits:- PC5(1): IBF (Input buffer full) Output indicating (to both external device and mP) if port latch has data

- PC4(2): #STB (strobe) Input latches data into the port latch at the + ive going edge- PC3(0): INTR (Interrupt Request) If enabled, used to interrupt the processor. High at + ive going edge of #STB and low after data is read by processor- PC4(2) INTE (Interrupt Enable) Internal bit programmed through PC4(2) for enabling/disabling interrupt generation- PC6,7 General Purpose I/O bits. Set/Reset by CBB

Mode 1: Port A/B for Strobed Input

Data from External Device

Two ways to interface to the processor:

1. Polled: Processor polls IBF waiting for data to be available in port latch (IBF=1)

2. Interrupt-driven: INTR is used to interrupt the processor when data becomes available in port- saves processor time

as Input as Input

Automatically the associated C half assumes these functions- no longer separately Programmed (except PC6,7)

To mP

(Normal I/O bits)Program with Command Byte B (CBB) format

PortLatch

E x

t e

r n

a l

B u

s

Data Byte

Handshake

mP Data Bus

For Input Operations…Action started by who?

External DeviceSide

MicroprocessorSide

Data strobed in from external device into port latch

microprocessor reads datafrom port latch through the data bus

Hardware Polling By Device

Software Polling by mP

mP

to Dev & mP

or

Release IBFFor next transfer

IBF = 1

1

2

automatic

automatic(If Enabled)

;A procedure that reads the keyboard and;returns the ASCII key code in AL

BIT5 EQU 20H ;00100000 Mask defining PC5 (IBF for Port A)PORTC EQU 22HPORTA EQU 20HREAD PROC NEAR

.REPEAT ;poll IBF bitIN AL,PORTCTEST AL,BIT5

.UNTIL !ZERO? ; Quit polling when bit 5 read is not ZERO (IBF=1)IN AL, PORTA ; get ASCII value of key pressed from keyboardRET

READ ENDP

Interfacing a Keyboard to mP using Port A in Mode 1 (Strobed Input)

1 ms

Port A

Port C

To Processor

Data

H/S Control (PC5 IBF bit)

8255 should be programmed for operation in:- Group A in Mode 1- Port A is input

Handshake (Polling) Method

• Ports A and/or B used as strobed output ports to write data from processor into external devices. Associated half C bits provide handshake signals for the interface.

• Port C provides control bits:- PC7(1): #OBF (Output Buffer Full) Activated when port has data written into it by the processor. Deactivated to 1 when #ACK is received from external device indicating that data was read. - PC6(2): #ACK (Acknowledge input) from external device requesting data in port to be put on external bus for reading by external device- PC3(0): INTR (Interrupt Request) Used to interrupt the processor when external device receives data (end of #ACK). - PC6(2) INTE (Interrupt Enable) Internal bit programmed through PC4(2) for enabling/disabling interrupt generation- PC4,5 General Purpose I/O bits

Mode 1: Port A/B for Strobed Output

Automatically the associated C half assumes these functions- no longer separately programmed (except PC4,5)

From mP

Data from mPIs strobed into port latch at trailing edge of #WR

from mP by mP

Again mP can do its part in two ways:

1. Polling for #OBF high

2. Getting an interrupt with INTR

Ext

erna

l Bus

Port Latch

Data Byte

Handshake

mP DataBus

For output operations…Action started by who?

External DeviceSide

MicroprocessorSide

Software Polling By Processor

Hardware Polling byDevice

For device to take data:- #ACK puts latch data on the external bus- mP Provides a strobe pulse

1

2

or

For mP to O/PNext char

DeviceRealizes there isData in port latch

AutomaticAutomatic

(If Enabled)

;A procedure that transfers an ASCII character from AH to the printer ;connected to port BBIT1 EQU 2 ; Bit PC1 = #OBF for port BPORTC EQU 62HPORTB EQU 61HCMD EQU 63H; The 8255 command byte addressPRINT PROC NEAR

.REPEAT ;Wait for printer ready to receive a new char- Poll #OBF till highIN AL,PORTCTEST AL,BIT1

.UNTIL !ZERO? ; #OBF =1 No data in output buffer, so can write into it! MOV AL,AH ; Write ASCII char data into port latchOUT PORTB,ALMOV AL,8 ;Generate data strobe pulse

; on PC4

OUT CMD,ALMOV AL,9OUT CMD,ALRET

PRINT ENDP

Interfacing a Printer to mP using Port B in Mode 1 (Strobed Output)

Port B

Port C

Data

Control (PC1 #OBF bit)Strobe dataInto Printer

Ordinary C I/O bitSet and reset with command byte B To generate the #DS pulse (Strobe output) signal to Ex Device

#OBF not usedAs a strobe to printer

1 0 0 0 1 0 0 1

In port C

Reset PC4Set PC4

D

ata

fro

m m

P t

o po

rt la

tch

Dat

a f

rom

por

t la

tch

to P

rinte

r

mP Polling for #OBF = 1

Mode 2: Port A only for Bidirectional I/O• Ports A (only) is used for bidirectional I/O. 5 Port C bits

provide bidirectional handshake signals. 3 Port C bits are programmable I/O with Command byte B format.

• Application: Computer-to-computer comm., GPIB bus• Handshake signals combine input handshake and

output handshake of mode 1:- For Input: #STB, IBF- For Output: #OBF, #ACK- Common: INTR (qualified by 2 internal enable bits INTE1 and INTE2)

• Program operates the port’s bidirectional bus using the OUT and IN instructions

I/P Control

O/P Control

To/From mP

Mode 2 Example: Processor Sends Data to External Device on the Bidirectional Bus

To send Data from processor to external device:1. Processor checks if #OBF = 1 (No data pending in port)2. Processor OUTs data to port (Writes it into Port A latch- not on external

bus yet)3. Port automatically lowers #OBF O/P to alert device to take data4. Device detects 3 and lowers #ACK input to port5. This raises #OBF high6. #ACK enables Port external bus to carry latch data so it can be taken

by device7. After device takes data it raises #ACK high

I/P Control

O/P ControlFrom mP

I understand you have data for me in your latch. Please put it on the busso I can take it!

By external device(May need a strobe pulse from mP)

By Microprocessor

Data in Port A latch, but not on its I/O bus yet

Port I/O bus is normally HiZTo allow use inThe other direction

Enable I/O Busto carrylatch data

1

2

3

4

6

5

7

;A procedure transmits AH through the bidirectional bus

BIT7 EQU 80HPORTC EQU 62HPORTA EQU 60H

TRANSPROC NEAR

.REPEAT IN AL,PORTC TEST AL,BIT7.UNTIL !ZERO?MOV AL,AHOUT PORTA,ALRET

TRANS ENDP

Wait for #OBF =1Result = 1 (Not zero)

Mode 2 Example: Processor Receives Data from External Device on the Bidirectional Bus

To Receive Data:1. External device sending data checks if #IBF = 0 (No pending

data in port latch not read by processor) (Hardware Polling)2. Then it puts its data on external bus and strobes it into port latch

using #STB3. IBF automatically goes high until data is read by processor4. Processor polls IBF for IBF = 1 to make sure data is in port latch

(software polling)5. Processor reads data from port 6. This automatically lowers IBF to enable further writes

I/P Control

O/P Control

By device on the other side

HiZ external bus!(It is OK…processor reads its data bus)

To mP

By Microprocessor

latch

Port I/O bus is normally HiZ

Hardware Polling for IBF = 0 by device to generate #STBTo avoid overwriting existing data in Port not read by processor yet

;A procedure that reads data from the bidirectional bus into AL

BIT5 EQU 20H PORTC EQU 62H PORTA EQU 60H

READ PROC NEAR

.REPEAT ;Wait for IBF = 1IN AL,PORTCTEST AL,BIT5 .UNTIL !ZERO? IN AL,PORTA RET

READ PROC NEAR

1

2

3 4

5

Step 4

6

2

Step 5

Summary of port functions in various modes

Programmable Counter/Interval Timer (PIT): 8254

• 3 Identical and separate 16-bit presettable down counters

• Clock frequency up to 10 MHz Binary or BCD counting • Each can be programmed to operate in any of 6 modes• Each can be preset and read under program control• Programmed by writing into a command register (A1A0=11)• Appears as 4 I/O bytes in the processor I/O space (similar to the PPI 82C55)

Note similarity with the 82C55:3 programmable units+ 1 Command register

Data bus

Chip Select

(Obtain by Decoding Remaining I/OAddress lines)

2-bit address

RD/WR Control

PIT

For each counter:

- Clock Input: - ive edge- Gate Input: Function depends on mode, e.g. 1: Count, 0: No count- Output: Changes state on terminal count

WK 11

The PIT in the PC

• The timer appears in the PC at I/O ports 20H and 23H. It generates speaker beeps and generates a periodic signal at the correct repetition frequency to refresh the DRAM

A1 A0 Function

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control word (command byte)

General Applications

Generation of accurate time delays under software control

• Real Time Clock• Event Counter: Interrupts processor when a preset number

of events occur• Digital one-shot (A pulse of a programmable width

generated in response to an event)• Programmable frequency clock (fout = fin/n, n determined

by software)• Square wave generator (programmable frequency)• Complex waveform generation (counter output fed to

a digital to analog converter- DAC)• Complex motor control

Close-up of one Counter

2-byte Count Register(Input Latches for writing Initial Counts from mPInto counter)

16-bit Counting Element

• 2-byte Output Latches for reading counter Parallel output (at the counter’s I/O address with the same format specified when the counter was programmed)

• Normally follow counter count and can be read at any time. • A “Counter Latch Command” latches the present counter count into them. Will be frozen till read by

processor

Program the counters By writing into thisControl byte (A1A0 = 11)

LSMS

CR and OL are written/read one byte at a time across the 8-bit data bus

Counter Status: Use the Read-back Command to latch into Status Latch for readingby Processor

LSMS

Inputs & Outputs

Programming the Counters: Write Operations• Each counter must be programmed before it can be used• A counter is programmed by writing a control word (specifying the

counter) into the control word register (A1A0=11), followed by an initial count into the I/O address of that counter

Counting Method: BCD or Binary

Counter Mode

Reading/Writing Format

Specify Counterto be programmed

• Initial counts are written into the I/O address of the counter specified, e.g. A1A0 = 01 for counter 1

• Initial count bytes or words specified for a counter in the control word should be sent after the control word- but not necessarily immediately following it, and programming of the 3 counters can be interleaved

Counter Latch Command Latches present count of specifiedCounter to its OL. Remains frozenuntil latch is read by processor

Use different formats for theControl word- see Read Operations

Programming the Counters: Write OperationsAll sequences below for the Control Word followed by Initial Count bytes are valid

The arrow shows an invalidSequence. Why?

READ Operations: Reading a counter while it is countingThree Ways

1. Simple READ: Does not need a special command….Procedure:- Inhibit clocking by G = 0 (Disrupts future count!) to ensure reading stable levels- Simply Read the counter at the proper I/O address (e.g. A1A0=10 for counter 2)

2. Issue a “Counter Latch Command” by writing the appropriate byte into the Control Word Register (A1A0 = 11), with RW1 RW0 = 00 and specifying the address of the required counter SC1 SC0.

When this command is executed, Present count at the counter parallel output is latched into the counter’s output latch (OL) and remains fixed until the latch is read by the processor or the counter is re-programmed. Only then it returns to follow the counter count as before. OL bytes must be read in the same format specified when the counter was last programmed The command byte during a

“Counter latch command”

READ Operations: Reading a counter while it is countingThree Ways, Contd.

3. Read Back Command Written into the control word (A1A0=11)To latch Status and/or Count of any of the three counters(Up to all 3 counters can be specified simultaneously)

Format for the Counter Status Register(latched into the Status latch if so specified in the Read-Back Command)

Shows how the counter was programmed

i.e. Count = 00000H

Up to 3 Counters

The command byte written during a “Read back command”

The 6 Counter Modes

FreeRunning

One off

One off

Mode 0: Event Counter

• G input = 1 always to enable counting

• n: Initial Count Number loaded into counter after programming it by the Control Word

• OUT goes high at terminal count, (n+1) negative clock edges after n is written into Counter Register by software

Initial Count n = 5Written into Counter’s CR

Initial Count n = 5Loaded into Counter

. . . Counter decrements till Terminal Count = 00000H

To Processor INTR

OUT rises high at terminal (null) count

Applications:

Interrupt Processor on:• Arrival of a predetermined number of

events (1 0 clk transitions) = (n+1)• Or elapse of a time interval

t = (n+1) Tclk

From the writing of n by software into the counter

Count down from n till terminal (null) count

• Gate G in this mode is used as the monostable hardware trigger• It allows n to be loaded into counter, which clears OUT to 0. OUT remains

0 until terminal count• Duration of the 0 pulse on OUT = n Tclk• If Gate goes high again during the OUT pulse, monostable is retriggered

to extend the pulse by another duration


Initial Count n = 5Loaded into Counter . . . Counter decrements till Terminal Count = 00000H

Mode 1: Hardware Triggered One-Shot (Monostable Multivibrator- Retriggerable)

OUT rises high at terminal count

(Trigger)

Note: In this mode G needs not be kept high for counting to be enabled

OUT goes lowAt loading n

• Gate G = 1 always, to enable counting• OUT frequency = Clock frequency/n• OUT Duty cycle (ON:Total) = (n-1):n A square wave only for n = 2



Mode 2: Divide-by-n Counter (Programmable Frequency Clock)

(Trigger)


OUT goes lowAt n loading

written Into Counter

n = 3

Regular Period(3 pulses = n)

2 1

• Gate G = 1 always, to enable counting• OUT frequency = Clock frequency/n• OUT Duty cycle (ON:Total) = (1:2) for n even

1:2 for n odd and large



Mode 3: Divide-by-n Counter but with a Square Wave Output:

(Trigger)


OUT goes lowAt n loading

written Into Counterwritten Into Count Register of Counter

(Fixed)

Regular Period4

2 2

7

4 3

• Gate G = 1 always, to enable counting• OUT gives an active low strobe pulse

- Strobe pulse duration: Fixed at 1 clock interval

- Delay from writing initial count into counter (software trigger) = (n+1) Tclk• Useful for strobing data generated by processor into external devices, e.g.

a printer• Note similarity between modes 0 and 4

Mode 4: Software Triggered Strobe Output Pulse:

written Into Count Register of counter

1

• Gate G is used as a hardware trigger. Not needed high for counting• OUT gives an active low strobe pulse

- Pulse duration: 1 clock interval

- Delay from writing initial count into counter (software trigger) = (n) Tclk• Useful for strobing data generated by processor into external devices, e.g.

a printer• Note similarity between modes 1 and 5

Mode 5: Hardware Triggered Strobe Output Pulse:

written Into Counter

Summary of G effectIn the 6 counter modes

Event Counter

Hardware triggeredOne shot

Divide by N Counter

Divide by N Counter(Square Wave Output)

Software triggeredStrobe

Hardware triggeredStrobe

3 pairs of similar modes

Summary of the PIT 5 counter modes

M2 M1 M0 Mode # FunctionSpecifications (n = pre-loaded initial count, Tclk = clock interval)

0 0 0 0Event Counter

Delay to rising edge = (n+1) Tclk

0 0 1 1Hardware-Triggered One-Shot

Width of negative going pulse = (n) Tclk

X 1 0 2Divide-by-N Counter

fout = fclk / (n)Duty cycle: Mark:Total = (n-1):n

X 1 1 3Square-WaveGenerator

fout = fclk / (n)Duty cycle 50% (for all n)

1 0 0 4Software-Triggered Strobe

Strobe width = TclkStrobe Delay = (n+1) Tclk

1 0 1 5Hardware-Triggered Strobe

Strobe width = TclkStrobe Delay = (n) Tclk

8254 PIT Programming Example8 MHz Clock Frequency

100 KHz Square Wave: Mode 3 (requires G =

1)f Out = f in /nn = 8000/100 = 80d

200 KHz non-square wave: Mode 2 (requires G = 1)f Out = f in /nn = 8000/200 = 40d

G = 1 Permanently: Enable Counters 0 and 1

Addresses:Counter0: 700HCounter1: 702HCounter2: 704HControl Word: 706H

(Even addresses)A0 is decoded as 0

;A procedure that programs the 8254 timer to function;as illustrated in Figure 11-34TIME PROC NEAR USES AX DX

MOV DX,706H ; address Control registerMOV AL,00110110B ; program counter 0 for mode 3

; Counter Load/Read format is ; 2 bytes (LS first)

OUT DX,ALMOV AL,01110100B ;program counter 1 for mode 2OUT DX,ALMOV DX,700H ; Address counter 0MOV AL,80 ; Load initial count 80d into counter 0 ; LS byte of initial countOUT DX,ALMOV AL,0; ;Then MS byte of initial countOUT DX,ALMOV DX,702H ; Address counter 1MOV AL,40 ; Load initial count 40d into counter 1OUT DX,ALMOV AL,0 ;Then MS byte of initial countOUT DX,ALRET

TIME ENDP

Control Word

Waveform from Counter 0 startsbeing generated here

Waveform from Counter 1 startsbeing generated here

Program

1

0

1

1

0

0

ON

OFF

OFF

ON

DC Motor Speed and Direction ControlQ 0#Q 1Rotation inOpposite Direction

Q 1#Q 0Rotation inOne Direction; e.g. clockwise

The Q Output (#Q is the complement):• No net motion with duty cycle = 1:2

• Net motion in either directionWith a duty cycle < or > 1:2

Pulse Width Modulation for Speed Control:

We use counter 0 and Counter 1:- Both driven by an 8 MHz clock- Both are divide-by-30,720 counters (Mode 2) (output repetition rate, f = 8 MHz / 30,720 = 260 Hz (motor spec requires: 60 Hz < f < 1000 Hz)- Bistable is cleared (Q=0) by the #CLR signal from counter 0 and preset (Q=1) by the #PS signal from counter 1- Duty cycle is varied by controlling the timing of #PS relative to #CLR

(Preset: Q 1)(Set bistable)

(Clear: Q 0)

Set-Reset Bistable

(Reset bistable

Duty Cycle Motor Speed Control

The Q Output (#Q is the complement) duty cycle Controls motion:• No net motion with duty cycle = 1:2

• Net motion in either directionWith a duty cycle < or > 1:2

Pulse Width Modulation (Speed Control):

Duty Cycle: >1:2 Count < (30,720)/2

OUT of Counter 1 (mode 2)

OUT of Counter 0 (mode 2)

Wait for Counter 1to reach this count andstart Counter 0

This is done only onceand the system is left to free-rununtil a different speed is required

Duty Cycle = 1:2Count = (30,720)/2

Duty Cycle: < 1:2 Count > (30,720)/2

Assume 256 different speed control settings: Represented by byte variable in AH = 128 for no motion (1:2), = 0 -127: Speed in one direction (<1:2). 0: Maximum speed in that direction = 129 – 255: Speed in the other direction direction (>1:2), 255: Maximum speed in that direction

Increment Count for each speed control setting = 30720/256 = 120

e.g. for AH = 128: Delay count = 128 x 120 = 15360 (as seen above for no net motion (2:1))

Width = ?

AH = 0AH = 255

AH = 128

Waiting Count= 30720 – AH*120

0 128 255AH

Sp

ee

d

- max

+ max

= AH x 120= 128 x 120

230 x 120

25 x 120

From Counter 1

From Counter 0

Waiting Time = 30720 – AH * 120 Approx same speed but in opposite directions

;A procedure that controls the speed and direction of the motor ;in Figure 11-40.;;AH determines the speed and direction of the motor where;AH is between 00H and FFH.CNTR EQU 706H ; PIT Control WordCNT0 EQU 700HCNT1 EQU 702HCOUNT EQU 30720SPEED PROC NEAR USES BX DX AX

MOV BL,AH ;calculate count corresponding to AH: AH has speed control byte (0128255)MOV AX,120MUL BL ; Multiply AH (speed input) by 120MOV BX,AX ; result in AX, save in BX (BX has AH x 120)MOV AX,COUNTSUB AX,BXMOV BX,AX ; Subtract from 30720, Now BX has 30720 – AH x 120 = waiting count MOV DX,CNTRMOV AL,00110100B ; program control wordOUT DX,AL ; for counter 0: Binary, Mode 2, 2 bytes R/WMOV AL,01110100B ; same for counter 1OUT DX,AL ; but do not start it yet by loading COUNT- do this after waiting timeMOV DX,CNT1 ; program counter 1 to generate the clear (#CLR) signal for Q (free-running)MOV AX,COUNT ; OUT DX,AL ; LS byte of 30720 firstMOV AL,AHOUT DX,AL ; then MS byte.REPEAT ; wait for counter 1 count to reach Waiting Count in BX

IN AL,DX ; Read LS byte of counter 1 (goes as AL)XCHG AL,AH ; Put it in AHIN AL,DX ; Read MS byte of counter 1 (goes as AL)XCHG AL,AH ; swap AL and AH to put things back to order

.UNTIL BX == AXMOV DX,CNT0 ;program counter 0MOV AX,COUNT ; to generate a set (#PS) for Q (free-running) after that waiting

; delay by Counter 1. Note you also load COUNT as with Counter 1OUT DX,AL ; Actual outputting LS byte then MS byteMOV AL,AHOUT DX,ALRET

SPEED ENDP

For Control Reg

Always LS then MS

Counter 0 starts free running at 260 Hz,delayed by waiting countfrom the start of Counter 1

Counter 0 starts, free running at 260 Hz,Repeatedly read counter 1

Until it reaches “Waiting Count”

The 16550 UART• Universal Asynchronous Receiver

Transmitter • Baud rates up to 1.5 M bauds

(signal elements/s)• = Data rate (bps) for binary data• Compatible with Intel and other

Processors• Includes:

- A programmable baud rate generator - 16-byte FIFO buffers at input and output to help processor deal with data bursts

WK 12

Asynchronous Serial Data Communication

• Data sent asynchronously using the format illustrated below

• We often use one start bit and one stop bit to frame the data, which is usually 8-data bits with or without parity

Usually a byte of data

The 16550 UART: Functional Description

40 pin DIP

• Totally independent Transmitter (TX) and Receiver (RX) Sections

• This allows communication in the following modes: - Simplex: Only TX or RX is used (one direction all the time)- Half Duplex: TX then RX (two directions at different times)- Full Duplex: TX and RX simultaneously (two directions at the same time)

• Can control a modem using six signals, e.g. #DSR (Data Set Ready) input, #DTR (Data Terminal Ready) output….Here the UART is the data terminal and modem is the dataset.

The 16550 UART: Typical Configuration

UART

mPControl

Receiver

TransmitterSerialComm.Link

SIN

SOUT

Memory

Data

DMA Data Transfers:Memory UART Directly Without going through the mP

16-byte FIFO Input Buffer

16-byte FIFO Output Buffer

PS

PS

Serial to ParallelOr Parallel to SerialConverters

The 16550 UART: Pin Assignments

40 pin DIP

3 I/O Address bits from Processor(Table 11-5)

Baud rate Clock output

Chip Select Inputs(Multiple I/Ps)

Modem Interface: Inputs & Outputs

Data bus to Processor

Interrupt Processor

Master Reset (tie to mP Reset I/P) Serial data INput from RX

Serial data OUTput to TX

Receiver Clock input

Read & Write Control inputs from mP(with complements for versatility

User defined outputs

Crystal orExternal Clock Input

TX ready for data. Put data intoUART by DMA

RX ready with data. Take data fromUART by DMA

Address Strobe (not needed with Intels)

UARTs in the PC

• Used to control the COM ports of the PC

- UART at I/O address 3F8-3FF: COM Port 0

- UART at I/O address 2F8-2FF: COM Port 2

Programming the UARTTwo Stages:

a. Initialization Dialog: (Setup)- Follows RESET- Has two steps:

1. Program the line control register (Set asynchronous transmission parameters:

# of stop, data, and parity bits, etc.) 2. Program the baud rate generator for the required

baud rate

b. Operation Dialog: (Actual Communication)

A2 A1 A0 Function

0 0 0 Receiver buffer (read data from RX) and transmitter holding (write data to TX). Also write LS byte of baud rate divisor

0 0 1 Interrupt enable. Also write MS byte of baud rate divisor

0 1 0 Interrupt identification (read) and FIFO control Register (write)- Used for operation dialog programming

0 1 1 Line control Register (Write into the line control register to program asynchronous communication at initialization)

1 0 0 Modem control

1 0 1 Line status LSTAT (Read the line status register to see if TX or RX are ready and to check for errors )

1 1 0 Modem status

1 1 1 Scratch

The 8 I/O Byte Locations on the UART

1. Programming the Line Control RegisterI/O Address: A2 A1 A0 = 011

Data Length = 5 bits

Data Length > 5 bits

Parity ControlSee next slide

To allow programmingThe baud rate generator

See Table on next slide

A break is a minimum of 2 frames of 0’s

a. InitializationDialogProgramming

DL bit must be setbefore you can load the divisorfor the baud generator

ST P PE Function

0 0 0 No parity

0 0 1 Odd parity

0 1 0 No parity

0 1 1 Even parity

1 0 0 Undefined

1 0 1 Send/receive 1 (send 1 in place of the parity bit)

1 1 0 Undefined

1 1 1 Send/receive 0 (send 0 in place of the parity bit)

The 3 Parity Control Bits in the Line Control Register

Baud Rate Divisor Value

110 10,473

300 3840

1200 920

2400 480

4800 240

9600 120

19,200 60

38,400 30

57,600 20

115,200 10

• Baud rate is programmed by loading a 16-bit divisor for the crystal oscillator (or external input) frequency into the I/O port addresses:

{A2 A1 A0} = 000: LS Byte of divisor {A2 A1 A0} = 001: MS Byte of divisor

• Divisor value is determined by the Oscillator frequency and the baud rate required:

Divisor = Oscillator frequency / (16 * Baud rate)

Table shows divisor values required for various baud rates for osc frequency = 18.432 MHz

2. Programming the Baud rate Generator

(Active Low)

;Initialization dialog for Figure 11-45;Baud rate 9600, 7 bit data, odd parity, 1 stop bitLINE EQU 0F3H ; A2 A1 A0 = 011 for the Line Control RegisterLSB EQU 0F0H ; A2 A1 A0 = 000 for LSB of divisorMSB EQU 0F1H ; A2 A1 A0 = 001 for MSB of divisorFIFO EQU 0F2H ; A2 A1 A0 = 010 for the FIFO Control Register

INIT PROC NEARMOV AL,10001010BOUT LINE,AL ; Enable Baud rate programming See slide 108

; program Baud 9600; Divisor = 120d (see Table on slide 110)

MOV AL,120 ; LSB of divisorOUT LSB,ALMOV AL,0 ; MS Byte of divisorOUT MSB,ALMOV AL,00001010B ;program 7 bit data, oddOUT LINE,AL ;parity, 1 stop bit

;(& disable baud rate programming?)MOV AL,00000111B ;enable transmitter and receiverOUT FIFO,AL ;by writing into the FIFO control Reg.RET

INIT ENDP

Must write this into FIFO Registerto enable communicationand operation dialog programming

16550 FIFO Control Register (Write)

111

I/O Address: A2 A1 A0 = 010

Required to enableactual communication(Operation Dialog)

16550 Line Status Register (LSTAT)I/O Address: A2 A1 A0 = 101

Before writing datafor transmission, Ensure TX is ready to take it [TH (bit 5) = 1]

Before reading datafrom receiver, ensureRX has data [DR (bit 1) = 1]

Error status bitsAny being 1 indicatesAn error

b. OperationDialogProgramming

;A procedure that transmits the byte in AH serially ;via the 16650 UART

LSTAT EQU 0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101)

DATA EQU 0F0H ; TX/RX Data Register at (A2 A1 A0 = 000)

SEND PROC NEAR USES AX.REPEAT ;test the TH bit (bit 5) in to see if TX is available

IN AL,LSTATTEST AL,20H ;20H is the mask for the TH bit

.UNTIL !ZERO?MOV AL,AHOUT DATA,AL ;send data to TXRET

SEND ENDP

(LSTAT)

; Procedure receives byte from UART into AL if no comm. error; If error detected, it load Al with ‘?’ as an alert

LSTAT EQU 0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101)

DATA EQU 0F0H ; TX/RX Data Register at (A2 A1 A0 = 000)

REVC PROC NEAR.REPEAT

IN AL,LSTAT ;test DR bitTEST AL,1

.UNTIL !ZERO?TEST AL,0EH ;test for any error.IF ZERO? ;no error

IN AL,DATA ;Read RX Data Register into AL.ELSE ;any error

MOV AL,’?’ ;Put “?” in AL to indicate error.ENDIFRET

RECV ENDP

Documents

The 8255 allows the microprocessor to communicate with the outside world through three programmable 8-bit wide I/O ports The PC uses a few 82C55 (in the