Texas Instruments - SN74HC273 - Octal D-Type Flip-Flops with reset

SCLS136D DECEMBER 1982 REVISED AUGUST 2003

1POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 12 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max Contain Eight Flip-Flops With Single-Rail

Outputs

Direct Clear Input Individual Data Input to Each Flip-Flop Applications Include:

Buffer/Storage Registers Shift Registers Pattern Generators

description

12345678910

20191817161514131211

CLR1Q1D2D2Q3Q3D4D4Q

GND

VCC8Q8D7D7Q6Q6D5D5QCLK

SN54HC273 . . . J OR W PACKAGESN74HC273 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

45678

1817161514

8D7D7Q6Q6D

2D2Q3Q3D4D

1D 1Q CLR

5Q 5D8Q

4QG

ND CLK

V CC

SN54HC273 . . . FK PACKAGE(TOP VIEW)

description/ordering informationThese circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.

ORDERING INFORMATION

TA PACKAGEORDERABLE

PART NUMBERTOP-SIDEMARKING

PDIP N Tube of 20 SN74HC273N SN74HC273N

SOIC DWTube of 25 SN74HC273DW

HC273SOIC DWReel of 2000 SN74HC273DWR HC273

40C to 85CSOP NS Reel of 2000 SN74HC273NSR HC273

40C to 85C SSOP DB Reel of 2000 SN74HC273DBR HC273Tube of 70 SN74HC273PW

TSSOP PW Reel of 2000 SN74HC273PWR HC273TSSOP PWReel of 250 SN74HC273PWT

HC273

CDIP J Tube of 20 SNJ54HC273J SNJ54HC273J55C to 125C CFP W Tube of 85 SNJ54HC273W SNJ54HC273W55 C to 125 C

LCCC FK Tube of 55 SNJ54HC273FK SNJ54HC273FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%*)$#!" # ! "&%##!" &% !+% !%" %," "!$%!""!)) -!.* )$#! %""/ )%" ! %#%""(. #($)%!%"!/ (( &%!%"*

&)$#!" #&(! ! 01 (( &%!%" % !%"!%)$(%"" !+%-"% !%)* (( !+% &)$#!" &)$#!%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"*


2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

description/ordering information (continued)Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on thepositive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not relateddirectly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input hasno effect at the output.

FUNCTION TABLE(each flip-flop)

INPUTS OUTPUTCLR CLK D

OUTPUTQ

L X X LH H HH L LH L X Q0

logic diagram (positive logic)

CLK

1D3

1D

C1R

1Q2

2D4

1D

C1R

2Q5

3D7

1D

C1R

3Q6

4D8

1D

C1R

4Q9

5D13

1D

C1R

5Q12

6D14

1D

C1R

6Q15

7D17

1D

C1R

7Q16

8D18

1D

C1R

8Q19

CLR

11

1

logic diagram, each flip-flop (positive logic)

CLK(I)

R

Q

C

C

D

C

CC

C

C

C

TG TG

TG

TG

C

C



absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage range, VCC 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current, IO (VO = 0 to VCC) 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous current through VCC or GND 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, JA (see Note 2): DB package 70C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 69C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PW package 83C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg 65C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)SN54HC273 SN74HC273

UNITMIN NOM MAX MIN NOM MAX UNIT

VCC Supply voltage 2 5 6 2 5 6 VVCC = 2 V 1.5 1.5

VIH High-level input voltage VCC = 4.5 V 3.15 3.15 VVIH High-level input voltageVCC = 6 V 4.2 4.2

V

VCC = 2 V 0.5 0.5VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 VVIL Low-level input voltage

VCC = 6 V 1.8 1.8V

VI Input voltage 0 VCC 0 VCC VVO Output voltage 0 VCC 0 VCC V

VCC = 2 V 1000 1000t/v Input transition rise/fall time VCC = 4.5 V 500 500 nst/v Input transition rise/fall time

VCC = 6 V 400 400ns

TA Operating free-air temperature 55 125 40 85 CNOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications

of Slow or Floating CMOS Inputs, literature number SCBA004.



electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)

PARAMETER TEST CONDITIONS VCCTA = 25C SN54HC273 SN74HC273 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT

2 V 1.9 1.998 1.9 1.9IOH = 20 A 4.5 V 4.4 4.499 4.4 4.4

VOH VI = VIH or VIL

IOH = 20 A6 V 5.9 5.999 5.9 5.9 VVOH VI = VIH or VIL

IOH = 4 mA 4.5 V 3.98 4.3 3.7 3.84V

IOH = 5.2 mA 6 V 5.48 5.8 5.2 5.342 V 0.002 0.1 0.1 0.1

IOL = 20 A 4.5 V 0.001 0.1 0.1 0.1VOL VI = VIH or VIL

IOL = 20 A6 V 0.001 0.1 0.1 0.1 VVOL VI = VIH or VIL

IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33V

IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33II VI = VCC or 0 6 V 0.1 100 1000 1000 nAICC VI = VCC or 0, IO = 0 6 V 8 160 80 ACi 2 V to 6 V 3 10 10 10 pF

timing requirements over recommended operating free-air temperature range (unless otherwisenoted)

VCCTA = 25C SN54HC273 SN74HC273 UNITVCC MIN MAX MIN MAX MIN MAX UNIT

2 V 5 4 4fclock Clock frequency 4.5 V 27 18 21 MHzfclock Clock frequency

6 V 32 21 25MHz

2 V 80 120 100CLR low 4.5 V 16 24 20

tw Pulse duration

CLR low6 V 14 20 17

nstw Pulse duration 2 V 80 120 100 ns

CLK high or low 4.5 V 16 24 20CLK high or low6 V 14 20 172 V 100 150 125

Data 4.5 V 20 30 25

tsu Setup time before CLK

Data6 V 17 25 21

nstsu Setup time before CLK 2 V 100 150 125 ns

CLR inactive 4.5 V 20 30 25CLR inactive6 V 17 25 212 V 0 0 0

th Hold time, data after CLK 4.5 V 0 0 0 nsth Hold time, data after CLK6 V 0 0 0

ns



switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unlessotherwise noted) (see Figure 1)

PARAMETERFROM TO

VCCTA = 25C SN54HC273 SN74HC273 UNITPARAMETER FROM(INPUT)

TO(OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT

2 V 5 11 4 4fmax 4.5 V 27 50 18 21 MHzfmax

6 V 32 60 21 25MHz

2 V 55 160 240 200tPHL CLR Any 4.5 V 15 32 48 40 nstPHL CLR Any

6 V 12 27 41 34ns

2 V 56 160 240 200tpd CLK Any 4.5 V 15 32 48 40 nstpd CLK Any

6 V 13 27 41 34ns

2 V 38 75 110 95tt Any 4.5 V 8 15 22 19 nstt Any

6 V 6 13 19 16ns

operating characteristics, TA = 25CPARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance per flip-flop No load 35 pF



PARAMETER MEASUREMENT INFORMATION

VOLTAGE WAVEFORMSSETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMSPULSE DURATIONS

thtsu

50%

50%50%10%10%

90% 90%

VCC

VCC

0 V

0 V

tr tf

ReferenceInput

DataInput

50%High-LevelPulse 50%VCC

0 V

50% 50%VCC

0 V

tw

Low-LevelPulse

VOLTAGE WAVEFORMSPROPAGATION DELAY AND OUTPUT TRANSITION TIMES

50%

50%50%10%10%

90% 90%

VCC

VOH

VOL

0 V

tr tf

Input

In-PhaseOutput

50%

tPLH tPHL

50% 50%10% 10%

90%90%VOH

VOLtrtf

tPHL tPLH

Out-of-PhaseOutput

NOTES: A. CL includes probe and test-fixture capacitance.B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.C. For clock inputs, fmax is measured when the input duty cycle is 50%.D. The outputs are measured one at a time with one input transition per measurement.E. tPLH and tPHL are the same as tpd.

TestPoint

From OutputUnder Test

CL = 50 pF(see Note A)

LOAD CIRCUIT

Figure 1. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (C) Device Marking(4/5)

Samples

5962-8409901VRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type 5962-8409901VRASNV54HC273J

5962-8409901VSA ACTIVE CFP W 20 25 TBD A42 N / A for Pkg Type 5962-8409901VSASNV54HC273W

84099012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84099012ASNJ54HC273FK

8409901RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8409901RASNJ54HC273J

8409901SA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 8409901SASNJ54HC273W

JM38510/65601BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/65601BRA

JM38510/65601BSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/65601BSA

M38510/65601BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/65601BRA

M38510/65601BSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/65601BSA

SN54HC273J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC273J

SN74HC273DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI -40 to 85SN74HC273DBR ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC273

SN74HC273DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC273

SN74HC273DW ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br)


SN74HC273DWE4 ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br)


SN74HC273DWG4 ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br)




Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (C) Device Marking(4/5)

Samples

SN74HC273DWR ACTIVE SOIC DW 20 2000 Green (RoHS& no Sb/Br)

CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC273

SN74HC273DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS& no Sb/Br)


SN74HC273DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS& no Sb/Br)


SN74HC273N ACTIVE PDIP N 20 20 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC273N

SN74HC273N3 OBSOLETE PDIP N 20 TBD Call TI Call TI -40 to 85SN74HC273NE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS)CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC273N

SN74HC273NSR ACTIVE SO NS 20 2000 Green (RoHS& no Sb/Br)


SN74HC273NSRG4 ACTIVE SO NS 20 2000 Green (RoHS& no Sb/Br)


SN74HC273PW ACTIVE TSSOP PW 20 70 Green (RoHS& no Sb/Br)


SN74HC273PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS& no Sb/Br)


SN74HC273PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85SN74HC273PWR ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC273

SN74HC273PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS& no Sb/Br)


SN74HC273PWT ACTIVE TSSOP PW 20 250 Green (RoHS& no Sb/Br)


SNJ54HC273FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84099012ASNJ54HC273FK

SNJ54HC273J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8409901RASNJ54HC273J

SNJ54HC273W ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 8409901SASNJ54HC273W

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.



Addendum-Page 3

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC273, SN54HC273-SP, SN74HC273 :

Catalog: SN74HC273, SN54HC273

Automotive: SN74HC273-Q1, SN74HC273-Q1

Military: SN54HC273



Addendum-Page 4

Space: SN54HC273-SP

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Military - QML certified for Military and Defense Applications

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

TAPE AND REEL INFORMATION

*All dimensions are nominalDevice Package

TypePackageDrawing

Pins SPQ ReelDiameter

(mm)Reel

WidthW1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN74HC273DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1SN74HC273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1SN74HC273NSR SO NS 20 2000 330.0 24.4 9.0 13.0 2.4 4.0 24.0 Q1SN74HC273PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1SN74HC273PWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Dec-2014

Pack Materials-Page 1

*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74HC273DBR SSOP DB 20 2000 367.0 367.0 38.0SN74HC273DWR SOIC DW 20 2000 600.0 144.0 84.0SN74HC273NSR SO NS 20 2000 367.0 367.0 45.0SN74HC273PWR TSSOP PW 20 2000 367.0 367.0 38.0SN74HC273PWT TSSOP PW 20 250 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Dec-2014

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E JANUARY 1995 REVISED DECEMBER 2001

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,207,40

0,550,95

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,605,00

15

0,22

14

A

28

1

2016

6,506,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M0,15

08

0,10

0,090,25

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150

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Texas Instruments - SN74HC273 - Octal D-Type Flip-Flops with reset