Testing of integrated circuits and design for testability J. Christiansen CERN - EP/MIC [email protected]

Testing of integrated circuitsand

design for testability

J. Christiansen

CERN - EP/MIC

[email protected]

December 2003 J.Christiansen/CERN 2

Cost of finding failing chip

LEVEL FAILURE MECHANISM PRICE

Wafer Yield, speed, noise, gain 1$

Chip Cutting, bonding 10$

ModuleSoldering, ESD 100$ 100 $

SystemCables, connectors 1000$ 100 $

At customerReliability of components,vibrations, corrosion, 10.000$ GOLDradiation, high voltage

(MCM)

(Sub)

Design

PrototypeVerification,Qualification,Production margins

SpecificationFunctionality, PerformanceTestability, reliabilityInteroperability

1$

1000$ 100 $

100.000$ GOLD

Designverificationtesting

Productiontesting

( price per design)

(price per chip)

100K$ - ? $(if not sufficient design verificationperformed)


Design verification testing

Specification(text)

Behavioural model(Verilog, Spice, etc.)

Design:Full custom,Standard cell,Gate array

Produced chip

Application

Does model complywith specification ?

Does design have samebehaviour as model ?

Does design work ?Does chip workas specified ?( 50 % )

Does chip work in application ?(50 % * 50 % = 25 %)

Does specification complywith application ? (50 %)

How do we find outwhat’s wrong ?

Sufficient margins forproduction variations ?

Low quantity

Reliability ?

Is it testable in production ?

(10- 50% of total development costs)

Imperfect designs are often accepted in HEP if ways around bugs can be found.

(Can be improved by System - IC behavioural modelling)


Production testing

Packaged

Wafer

Bare dieBurn-in ?

Functional test:fault coverage, stuck at 0/1

Internal speed test:clocking speed

External speed test:setup time, hold time,

I/O level test:output levels, input thresholds

Analog parameters:gain, noise, time constants,precision, etc.

Margins ? (noise, measurement accuracy, etc.)Temperature ?.Supply voltage ?External loads ?

MCM

delay

(Production test pattern development 5 - 25 % of development costs)(Production test 20 - 50% of final chip cost)

Monitoring of radiation resistance (destructive test)


Production yieldYield is calculated from defects per mm2 ( = exp( - A * D) )

Typical defect density is of the order of 0.005 - 0.02 defects/mm2

0.0 50.0 100.0 150.0 200.0Area ( mm2 )

0.0

20.0

40.0

60.0

80.0

100.0

Yie

ld (

% ) 0.005

0.01

0.02

61%

37% 36%

14%Low production volume technology

Very high production volume technology

Typical ASIC technology

Price of 100 mm2 chip compared to 50 mm2 chip: 100 mm2/50 mm2 x 0.61/0.37 = 3.4 ( D=0.01 )

100 mm2/50 mm2 x 0.36/0.14 = 5.3 ( D= 0.02 )

(memories have redundancy)


Typical IC defects


Reliability of integrated circuits

Failure rate

Time

1000 hours 10 yearsFailing parts within first 1000 hours: ~1 %

Burn-in testing : Heating up chips to 125 deg. accelerates 1000 hoursperiod to approx. 24 hours.

Static: power supply connected.Dynamic: Power + stimulation patterns.Functional test: Power + stimulation patterns + test.

Temperature cycling: Continuous temperature cycling of chips to provoketemperature gradient induced faults.(Non matching thermal expansion coefficients).

Badly designed component(electron migration, hot electron, corrosion, etc.)

Infant mortality

Wear out

Electrical stress: Operation at elevated supply voltage


What to testCombinatorial

N inputs N inputs

M storage elements

Sequential

Exhaustive test vectors: 2N Exhaustive test vectors: 2(N+M)

100 Mhz tester:N=32 ; test time = 40 seconds.N=64 ; test time = 6.000 years

Knowledge about topology of circuit must be used to reduce number of test vectors so they can be generated by tester ( tester memory: 10K - 10M ).

N inputs

M storage elements

Mixed analog/digital

Exhaustive test vectors: 2(N+M)

A/D

plus analog parameters

Analog and digital stimuli must be generated from a tightly synchronised system.

100k – 100M


Basic testing terms

CONTROLABILITY: The ease of controlling the state of a node in the circuit.

OBSERVABILITY: The ease of observing the state of a node in the circuit

Example: 4 bit counter with clear

clr

q3q2q1q0

Control of q3:

Set low: perform clear = 1 vector

Set high : perform clear + count to 1000B = 9 vectors

Testing a node in a circuitA: Apply sequence of test vectors to circuit which sets node to demanded

state.B: Apply sequence of test vectors to circuit which enables state of node to

be observed.C: The observing test vector sequence must not change state of node.


Fault models

Fault types: Functional.Timing.

Abstraction level: Transistor. (layout)Gate. (netlist)Macro ( functional blocks ).

Source Drain

Gate

D S

G

Open Shortgm

C

R

Vt

Delay

Parameter

11/2 2

Doping

l

w


Problematic faults at transistor level

Vi Vo

Transfer characteristic

RpmosVo

Vi

Vo

Vi

Vi Vo

PMOS stuck on

CMOS logic may become NMOS logic.

1 3 42Vector

Iddq

Threshold

A

B

X

A

B

PMOS stuck open

A B X

1

0 00

0

11

1

11

10

A B X

1

0 00

0

11

1

110

A B X

1

0 00

0

111

11

10

0

Combinatorial logic may become sequential


Gate level (stuck at 0/1model)

Bridge

Stuck at 0Stuck at 1

The gate level stuck at 0/1 is the dominantly used fault model for VLSI circuits, because of its simplicity. Opens and bridges not taken into account

Fault coverage calculated by fault simulation are always calculated using the stuck at 0/1 model. Other more com-plicated fault models are to compute intensive for VLSI designs.

Fault coverage = Number of faults detected by test patternTotal number of possible stuck at faults in circuit

Open


Testability

Number of test vectors (test routines)

Fault coverage

100 %A

BC

A: Design made with testability in mind. ( ~1 test vector per gate )

B: Design made without testability in mind but good fault coverage obtainedby large effort in making test vectors.

C: Design very difficult to test even using large effort in test vector generation.


Generation of test patterns

• Test vectors made by test engineer based on functional description and schematics. Proprietary test vector languages used to drive tester. (over the wall)

• Test vectors made by design engineer on CAE system. Subset of test patterns may be taken from design verification simulations.

• Generated by Automatic Test Pattern Generators ( ATPG). Requires internal scan path

• Pseudo random generated test patterns.

• Fault simulation calculates fault coverage.


Fault simulation

Fault coverage found by fault simulations

Test patterns

Single faultsimulation model

Referenceresponse

Goodsimulation model

Compareresponse

Repeat for all possible stuck at zero/one faults

Requires long simulation times !.

Toggle test ( counts how many times each node has changed) can be used to get a first impression of fault coverage.


Test development with increased complexity

SSI MSI LSI VLSI

pins/gate

1

0.1

0.01

0.001

Testability is decreasing drastically with increased integration level

Cost (time)

Complexity(time)

100 %

0 %Today

Design

Test development

Digital

Mixed analog/digital


Memory testing

Memoryarray

Memory

Row address

Column address

row

adr

dec

col adr decsense amp

Data

010 0

000

00

111

1 11 1

Checker board Walking patterns

0 0 00 0 0 00 0 0 00 0 0 0

0 0 00 0 0 00 0 0 00 0 0 0

11

Test vectors = 4N Test vectors = 2N2

64 k = 1.3 min.256k = 22 min1 M = 5.5 hours

100 MHz tester:

100 0

100

10

000

0 00 1

Address

Test vectors = 2N

Exhaustive test of a 1 M memory would take longer than estimated age of our universe.

Large memory chips have built in redundant memory array columns enabling repair of failing memory cells.

Algorithmic test patterns used.


IC testersHigh speed high pin count VLSI testers are very expensive and complicated machines.(500 k$ - 10 M$ ).

Vector speed: 100 - 1000MHz,Vector depth: 32k - 1GTime resolution: 100ps - 10psPin count: 100 - 1024

+ Measurements of DC characteristics

Testers must be faster than current IC technology !.

No standard Mixed signal tester exists (mixed signal tests are always special)

“Cheap” = 500k$


IC tester architectures

Shared resources:

vectormemory

timinggenerators

Pinelec.

Pinelec.

Pinelec.

Algorithmicpatterngenerator

Tester per pin:

vecmem

tim.gen

pinelec

systemsync.

vecmem

tim.gen

pinelec

vecmem

tim.gen

pinelec

+ Measurements of DC characteristics

Testers must be faster than current IC technology !.


Test vector timing formattingTiming formatting of test vectors:

Vector period

Vector value

NRZ(non return zero)

RZ(return zero)

SBC(surround by complement)

Strobed compare

Window compare

1 32

0 1 0

t1 t2 t2 t2t1 t1Timing

Some testers can do timing changes on the fly


E-beam testingThe reflection of an E-beam from a surface is influenced by voltage potential of the surface.

Patterngenerator

Sync.Electrostaticshutter

Chip

Reflectedchargecollector

Electron source

Single point probing with very good timing resolution ( ~100ps )

Complete scan of chip to get voltage contrast picture at a specific time in pattern sequence.

E-beam

beamfocusing

e

V

using statistical averaging

Difficult to use in modern technologies with many metal layers


Scan Path testing


Scan path testing

Improving controllability/observability by enabling all storage nodes to be controlled/observed via serial scan path.

Scan data in

Scan data out

Scan clock

Test principle: 1: Enable scan mode and scan in control data.2: Disable scan mode and clock chip one cycle.3: Enable scan mode and scan out observing data.

Generation of test vectors: With the high controllability/observability the test vectors can be generated automatically with a ATPG program.

Logic

Logic


Scan cells

q

qd

D flip-flop

scan in

data outclk

Storage node

scan outdata in m

ux

scan mode

data in

scan mode

q

qd

D flip-flop

clk scan out

data out

scan in

Non storage node:mux

mux

scan mode


JTAG standardIEEE 1149 standard.

Boundary scan to test interconnect between chips.

Internal scan to test chip.

Control and status of built in self test.

Chip ID

Many commercial chips with JTAG standard implemented:Processors, FPGA, etc.

Testregister

Testregister

Testregister

Testregister

Testregister

Testregister

Testregister

JTAGController

A

B

C

Test data out

Inputs

Outputs(analog)


Boundary scan

Open

Solder bridge

Short to ground

IC1

IC2

IC3

Boundary scan makes it possible to test interconnections betweenchips on a module.

Test of chips and board connections can be performed in-situ.


Connection of IC’s with JTAG

TDI TDO

TCK TMS

TDI TDO

TCK TMS

TDI TDO

TCK TMS

TDI TDO

TCK TMS

Serial connection

TDOTDI

TCK

TMS

TDI TDO

TCK TMS

TDI TDO

TCK TMS

TDI TDO

TCK TMS

TDI TDO

TCK TMS

TDI

TCK

TMS1

TMS2

TDO

Hybrid serial/parallel connection


JTAG testing of mixed analog/digital IC’s

Analog

Digital

TAP

Consider analog part as being external and insert boundary scan registers between analog and digital.

IEEE 1149.4 standard for test of analog parts has been defined.Principle: Two analog test busses to which internal nodes canbe connected via analog multiplexers controlled from JTAG register


JTAG testing of embedded on-chip memories

Memoryarray

Memory

Address row

adr

dec

col adr decsense amp

DataEach memory test vector must be shifted in/out serially

Testing becomes very, very, very SLOW

Use special Built In Self Test (BIST)


JTAG ProtocolOnly 4 ( 5 ) pins used for JTAG interface

TCK: Test clock Clock for loading control and test patternsTMS: Test mode select Selects mode of testingTDI: Test Data Input Input to shift registersTDO: Test Data Out Output from shift registers

Tclk

Tdi

Tdo

Tms Load Ins. shift in test data update scan registers Load response Shift out response

Instruction Test data in

Test data out

Next test data

Initialize


JTAG Block diagram

Boundary scan register

ID code register

User definable registers

Instruction register

Instructiondecoder

MU

X

TestAccessPortcontrol(TAP)

ExtestIntestSampleRun self testetc.

Tdi

Tclk

Tms

Trst

Tdo


JTAG TAP controller

TAP = Test Access Port

Select DR scan0

1

Capture DR0

1

Shift DR 1

0

Exit1 DR 0

1

Pause DR1

0

Exit2 DR1

0

Update DR1

0

Select IRscan0

1

Capture IR0

1

Shift IR 1

0

Exit1 IR 0

1

Pause IR1

0

Exit2 IR1

0

Update IR1

0

Run test/idle0

1

Test logic reset0

1


JTAG scan cells

From previous cell

To next cell

Observed node

Scan clk

Shift/observe

Observing scan cell Controlling scan cell

Update clkScan clkFrom previous cell

To next cell

Node inControlled node out

Normal/control

Observing and controlling scan cell

Update clkScan clkFrom previous cell

To next cell

Node in

Normal/control

Node out

Shift/oberserveJTAG cell

JTAG cell

JTAG cell

Tristate

Out

In

I/O Pin

I/O PAD

JTAG cells required for Input/Output pin


JTAG test

Boundary scan enables test of digital board connections.(automatic test generation from netlist of board)

JTAG ID enables verification of correct component type.

Enables access to internal test features in components.

Testing can be also be performed in-situ.

Small and “cheap” test system required.

Many commercial IC’s now have JTAG (Processors, FPGA’s, etc.)

O p en

S ol de r b r id ge

S h o rt to g ro u n d

IC 1

IC 2

IC 3


Built In Self Test (BIST)

Include test pattern generator and

Patterngenerator

Logicunder test

Responsechecker

Testcontrol

response check on chipMake self checking during operationby duplicating all functions

Logicblock 1

Logicblock 2

Compareresponse

Different schemes of built in (self) test

Generate local check sums and check with transformation of previous check sum

Logicblock 1

Check sum Check sum

CompareTransform

Logicblock 2

Check sum

CompareTransform

Fail

Hardware overhead !!


Simple pattern generation and verificationLinear Feedback shift register (LFSR)

clk

Based on polynomialdivision.

= exclusive or

Pattern generation: Pseudo random patterns based ongenerating polynomial and seed.

Pattern checking: Multiple input signature register ( MISR ) generating“check sum” of input data.

Inputs

clk

Scan path cells can be implemented so they can be used as pseudo random pattern generator or multiple input signature analysing register.


BILBO = Built In Logic Block ObserverI0 I1 I2 I3

q0 q1 q2 q3

B1

B2

Scan in Scan out

I0 I1 I2 I3

q0 q1 q2 q3

B1

B2

B1,B2 = 11, Normal register modeI0 I1 I2 I3

q0 q1 q2 q3

B1

B2

B1,B2 = 00, Scan path mode

I0 I1 I2 I3

q0 q1 q2 q3

B1

B2

B1,B2 = 10, LFSR mode

B1,B2 = 01, Reset of BILBO


Design for testability guidelines

• Use static logic.

• Make design completely synchronous.– use D flip-flops and not latches.

– no clock gating.

• No internal clock generation.

• Prevent large counter like structures.

• Use scan path (JTAG).

• Use built in test of memories.


And if you forget about

testing

Documents

Testing of integrated circuits and design for testability J. Christiansen CERN - EP/MIC [email protected]