Testbench Automation - Test and Verification Safety · PDF fileTestbench Infrastructure Automation UVM Framework Interface VIP Automation QVIP ... Ethernet Family 100G 40G 10G I2S

Adam Rose

Product Market Manager

Questa Verification IP

Testbench Automation

© 2017 Mentor Graphics Corporation

Advanced Verification The promise 15 years ago

ADR, VF17 2

Reuse — From Project to Project — From block level to system level

Coverage and Verification Management — How do we know we’re done ? — Project Management, Metrics

Constrained Random — Directed testing finds the known unknowns — Constrained Random finds the unknown unknowns


Number of Peak Engineers Increasing

Source: Wilson Research Group and Mentor Graphics, 2016 Functional Verification Study

H Foster, WRG Functional Verification Study, July 2016 3 ADR, VF17

7.8 8.1 8.5 10.1 10.5

4.8

7.6 8.4

11.0 11.6

0

5

10

15

20

25

2007 2010 2012 2014 2016

AS

IC/IC

Me

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Verification Engineers

Design Engineers

CAGR Designers 3.6% CAGR Verifiers 10.4%


More Verification Engineers vs Design Engineers



7.80 8.10

8.53

10.05

10.48

4.8

7.6

8.4

11.0

11.6

0

2

4

6

8

10

12

2007 2010 2012 2014 2016

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Design Engineers




More Verification Engineers vs Design Engineers



4.0 4.3 4.3

2.6

3.5 3.6

0

2

4

6

8

10

2012 2014 2016

FP

GA

Me

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Design Engineers


Why so much Time and Money on Verification ?

ADR, VF17

Complexity of Methodology — AVM in 2006 : 6,000 lines of code — UVM in 2016 : 75,000 lines of code — Delivers re-use but hard to get up and running

Complexity of VIP — Protocols themselves are complex and therefore highly configurable — Can be hard to instantiate, configure and bring up

Constrained Random is dumb — Many “useless” repeated tests, consuming compute resource but not

improving coverage — Directed vs Constrained Random trade-off

6


Verification Cookbooks — UVM — Coverage

27 Online Courses — CDC & Formal — SystemVerilog — TB Automation — Planning and Metrics — Many more..

Discussion Forums — More than 40,000 Members

Patterns Library www.verificationacademy.com

Verification Academy : UVM Cookbook De Facto Industry Standard UVM User Guide

ADR, VF17 7

http://www.verificationacademy.com/


But We Need to do More …



7.80 8.10

8.53

10.05

10.48

4.8

7.6

8.4

11.0

11.6

0

2

4

6

8

10

12

2007 2010 2012 2014 2016

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IC/IC

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Design Engineers




Testbench Automation Start earlier, work smarter, finish earlier

ADR, VF17 9


Testbench Infrastructure Automation

UVM Framework

Interface VIP Automation

QVIP Configurator

Intelligent Stimulus

Infact Portable Stimulus

Enterprise Verification Platform

UVM Complexity VIP Complexity Inefficient Stimulus


Testbench Generation : UVM-F and Configurator Become Productive in Hours Rather than Weeks

ADR, VF17

10

UVM Framework — Generates Testbench for SoC and Proprietary Interfaces

QVIP Configurator — Generates Testbench for Standard Interfaces

Creating Infrastructure Get Up and Running Productive Verification

Productive Verification


Intelligent Stimulus with InFact Portable Stimulus Earlier Tapeout and/or Higher Quality

ADR, VF17 11

Graph based stimulus combines strengths of directed and constrained random

Supports Portable Stimulus Standard

Graph Kits available for QVIPs

Directed + Constrained Random Testing

Intelligent Stimulus Testing More Tests

Earliest Tapeout

Date


Testbench Automation Benefits For New UVM Users

ADR, VF17 12

Reduces Ramp-Up Time

Reduces Project Risk

Faster Payback on Investment



UVM Framework


QVIP Configurator



Enterprise Verification

Platform


Testbench Automation Benefits For Experienced UVM Users

ADR, VF17 13

Reduces Ramp-Up Time

Maximizes Productivity

Best Use of Compute Resource



UVM Framework


QVIP Configurator



Enterprise Verification

Platform


Testbench Automation Integrated UVM, VIP and Portable Stimulus Flow

Experienced UVM Customers

New UVM Customers

Reduce Project Risk

Faster Ramp-Up

Maximum Productivity

Faster Payback on Investment

Best Use of Compute Resources

ADR, VF17 14

© 2017 Mentor Graphics Corporation www.mentor.com

ADR, VF17 15


Questa Verification IP A Complete Library for ASIC and FPGA Designs

ADR, VF17

Questa VIP Library Questa Memory Library

Serial

Family

Ethernet

Family

100G

40G

10G

1G

100M

10M

MIPI ®

Family

USB

Family

USB 3.0

USB 2.0

JTAG

SmartCard

Display

Family

I2C

I2S

SPI 4.2

SPI

UART

Unipro

LLI

CSI-2 / CSI-3

HDMI 2.1

DSI

DigRF

HCDP

USB 1.1

eHCI

CEC

oHCI

xHCI

SSIC

3.1 Serial

3.1 Pipe

MPHY

MPHY

I3C

UFS 25/50G

HSI

USB PD

eDP

V-by-One

Automotive

CPHY

DPHY

AMBA ®

Family

AHB5

AXI3

AXI4

PCIe ®

Family

PCIe 3.0

PCIe 2.0

MPHY

PCIe 1.0

ACE

AHB MRIOV

PIE8

RMMI

PCIe 4.0

AHCI

NVMe

APB3

DisplayPort I3C

Interlaken

400G

Automotive

Family

CAN

5G Family

JESD204B

DRAM

Family

DDR2

DDR4

LPDDR4

LPDDR3

LPDDR2

DDR3

DFI

WIDEIO

HBM2

HMC

Flash

Family

SDCard 4.2

eMMc 5.1

ONFI 4.0

UFS

SDIO 4.1

DIMM

Toggle

ParallelNOR

AMBA 5

CHI

CHI

Mil-Aero

Family

Spacewire

1553b

Hyperbus

Hyperram

Hyperflash

PCI

Serial NOR

16

Documents

Testbench Automation - Test and Verification Safety · PDF fileTestbench Infrastructure Automation UVM Framework Interface VIP Automation QVIP ... Ethernet Family 100G 40G 10G I2S