Test Procedures for PCIe4 Compliance Statements · JitterLabs Introduction TEST-2, v1.3 page 3 of 27 1 Introduction JitterLabs is an independent test laboratory providing accurate

Copyright © JitterLabs, LLC. All rights reserved.

TEST SPECIFICATION

Test Procedures for PCIe4 Compliance Statements How JitterLabs characterizes devices and processes data to create PDF Compliance Statements that report reference-clock compliance to PCIe v4.0 BASE specifications.

TEST-2

Version 1.3

December 22, 2017

JitterLabs Introduction

TEST-2, v1.3 page 2 of 27 www.jitterlabs.com

Table of Contents

1 Introduction ............................................................................................................................... 3

2 Test Setup, Acquisition, and Pre-processing ......................................................................... 42.1 Test Environment .................................................................................................................................................. 42.2 Temperature Chamber ......................................................................................................................................... 42.3 Real-time Sampling Oscilloscope ......................................................................................................................... 42.4 Compliance Load Boards ..................................................................................................................................... 6

3 Post-processing for Measurement Metrics ............................................................................ 83.1 AC, DC Parameters .............................................................................................................................................. 8

3.1.1 Specifications ......................................................................................................................................... 83.1.2 Rising and falling edge rate (ER_rising, ER_falling) ............................................................................ 123.1.3 Differential input high and low voltage (Vih, Vil) ................................................................................... 133.1.4 Absolute crossing-point voltage (Vcross) ............................................................................................. 143.1.5 Variation of Vcross for rising edges (Vcross_delta) ............................................................................. 143.1.6 Ring-back voltage margin (Vrb) ............................................................................................................ 153.1.7 Time before Vrb is allowed (Tstable) .................................................................................................... 163.1.8 Average clock period accuracy (Tperiod_avg) ..................................................................................... 173.1.9 Absolute period (Tperiod_abs) ............................................................................................................. 173.1.10 Cycle to cycle jitter (Tcc_jitter) ........................................................................................................... 173.1.11 Absolute maximum, minimum input voltage (Vmax, Vmin) ................................................................ 183.1.12 Duty cycle (Duty_cycle) ...................................................................................................................... 183.1.13 Rising to falling edge-rate matching (ER_matching) .......................................................................... 193.1.14 Clock source output DC impedance (Zc_dc) ...................................................................................... 203.1.15 Spread spectrum clock frequency (Fss) ............................................................................................. 203.1.16 SSC frequency deviation (Tssc_freq_dev) ......................................................................................... 213.1.17 Maximum, minimum SSC frequency slew (Tssc_max_freq_slew) ..................................................... 21

3.2 Low-frequency Jitter Mask .................................................................................................................................. 223.2.1 Specification ......................................................................................................................................... 223.2.2 Low-frequency Jitter Mask (Jitter_mask) .............................................................................................. 22

3.3 Jitter Generation Parameters .............................................................................................................................. 233.3.1 Specifications ....................................................................................................................................... 233.3.2 Jitter GEN-1, GEN-2 (2.5, 5 GT/s) ....................................................................................................... 263.3.3 Jitter GEN-3 (8 GT/s) ........................................................................................................................... 263.3.4 Jitter GEN-4 (16 GT/s) ......................................................................................................................... 26

4 References ............................................................................................................................... 27

5 Revision History ...................................................................................................................... 27

JitterLabs Introduction


1 Introduction JitterLabs is an independent test laboratory providing accurate characterization data for

devices used in timing-critical applications.

This document describes our internal test procedures to measure and analyze devices specifically used to provide reference clocks to the PCI Express market1. We use these procedures to evaluate reference-clock compliance to all required PCIe v4.0 BASE specifications. The following chapters discuss (1) how we use test equipment to extract raw data from a device, and (2) how we process this data to derive results shown in a PCIe4 Compliance Statement.

Note that each digital "PCIe4 Test Report" accessed in the JitterLabs app includes a PCIe4 Compliance Statement in PDF format, plus additional measurements not required by PCI-SIG (such as phase noise, spurious noise, power-supply induced jitter, and much more). This document only discusses test procedures used to create the PCIe4 Compliance Statement; refer to TEST-1 [1] for all other measurements (accessed via the JitterLabs app).

This document is arranged according to the sequence of events that occur. Chapter 2 discusses the physical test environment, how test instruments are used to extract raw data, and how this raw data is pre-processed into a meaningful form.

Chapter 3 discusses post-processing of the pre-processed data to derive a set of metrics for each measurement, which is used to determine compliance reported in a PCIe4 Compliance Statement. To improve readability, where metrics are defined throughout this document, the metric’s formal name is styled in bold, and its definition is written in a fixed-width font.

Note that JitterLabs attempts, whenever possible, to extract raw data from test instruments and post-process it using custom routines (e.g. software code) to derive results. This document describes these routines, including their limitations, to provide insight into the data for readers to assess its suitability for their needs.

Please contact us anytime with your questions, comments, or feedback. Thanks for using JitterLabs services.

1 All opinions, judgments, recommendations, etc. presented herein are the opinions of JitterLabs and do not

necessarily reflect the opinions of the PCI-SIG® association. PCI-SIG®, PCIe® and PCI EXPRESS® are registered trademarks and/or service marks of PCI-SIG.

JitterLabs Test Setup, Acquisition, and Pre-processing


2 Test Setup, Acquisition, and Pre-processing

2.1 Test Environment The test environment is maintained at room temperature (24.5 ± 1.5 °C).

2.2 Temperature Chamber A device under test (DUT), which provides a signal under test (SUT), may be characterized

at various test temperatures using a temperature chamber. The Test Report always lists the exact test temperature used for characterization. This temperature identifies the ambient temperature inside the chamber (the actual junction temperature on-die will be higher).

2.3 Real-time Sampling Oscilloscope PCI-SIG requires a DUT's output clock signal to pass through a differential trace having 15

dB loss at 4 GHz before being analyzed using a real-time sampling oscilloscope. A high impedance probe is used to measure the SUT across 2 pF terminators for all measurements.

An example block diagram in shown in Figure 2.1, where the top setup is used for all PCIe-related measurements, and the bottom setup is additionally used to measure DC impedance. In both setups, a compliance load board with the proper loss characteristic is connected to a customer-provided evaluation board for a product. The bottom setup terminates each conductor in the differential trace using the oscilloscope's internal 50 Ohm termination, whereas the top setup uses 2 pF termination (e.g. open circuit) as required by PCI-SIG.

The oscilloscope captures the SUT as a waveform containing at least 1G points. Differential waveforms are hardware subtracted by the oscilloscope before subsequent processing. JitterLabs saves the oscilloscope’s raw analog-to-digital converter (ADC) data, then applies custom software to extract all measured quantities.

Pre-processing of the raw data is performed as follows. First the raw data is converted to voltage. Then the voltage data is analyzed to determine the minimum required measurement bandwidth for the SUT. An optimum bandwidth is chosen to create a low-pass finite impulse response (FIR) filter that is applied (in software) to the data to remove high-frequency voltage noise. The voltage data is now ready for post-processing as described in Chapter 3.



Figure 2.1 PCIe test setups to measure DC impedance (bottom) and everything else (top).

Data acquisition using a real-time oscilloscope has the following limitations.

• The oscilloscope used by JitterLabs has a 10-90% rise time of 35 ps.

• The oscilloscope acquisition is limited to sampling at 40 GS/s. Linear interpolation is used between sampled data points to improve accuracy when making time-interval measurements in the output voltage waveform.

• The oscilloscope itself may introduce jitter onto the SUT during the measurement process. These sources of jitter, and others introduced by the environment, are mostly removed during post-processing, as discussed in [2].

Oscilloscope

1 3 2 4Temperature Chamber

ComplianceLoad Board #1

DUT Power Supply(s)

Differentialprobe #1

Differentialprobe #2

Out

Out2 pF

2 pF

Oscilloscope

1 3 2 4Temperature Chamber

ComplianceLoad Board #2

DUT Power Supply(s)

Out

Out



2.4 Compliance Load Boards The PCI-SIG association leaves it to clock/timing vendors to create evaluation boards for

reference-clock devices that integrate the required PCIe4 transmission line and 2 pF termination. To save customers this time and expense, JitterLabs has fabricated all necessary compliance load boards (CLBs) to connect to customer-supplied evaluation boards.

For all DUTs, the final test setup connects an eval board to a CLB using short phase-matched cables as shown in Figure 2.2 and Figure 2.3.

Figure 2.2 Test setup showing evaluation board connection to compliance load board (top)

and corresponding electrical model (bottom).

Figure 2.3 Compliance load board with differential probes across 2 pF termination.



Note that the DUT outputs shown above may require additional on-board termination (not shown), such as 50 Ohm pull-downs and/or series termination.

The CLB shown in Figure 2.3 and the top of Figure 2.1 is used for all PCIe-related measurements. A second CLB, illustrated in the bottom of Figure 2.1, is also required to measure the output clock DC impedance. This second CLB has the same layout as the first CLB, shown in Figure 2.3, except the outputs are taken through 3.5 mm connectors, and terminated using the oscilloscope's internal 50 Ohms rather than 2 pF on the board. Both CLBs were fabricated at the same time and are otherwise identical.

The PCIe v4.0 BASE specification requires both CLBs to have a loss of 15 dB at 4 GHz. We measure the CLB loss using a differential 4 GHz signal generator, and phase-matched cables having lengths of 4" and 6" according to the following equation.

𝑇𝑜𝑡𝑎𝑙 𝐿𝑜𝑠𝑠 = 𝑃𝐶𝐵 𝑙𝑜𝑠𝑠 + 4" 𝑐𝑎𝑏𝑙𝑒 𝑙𝑜𝑠𝑠

= 20𝑙𝑜𝑔𝑉!"#_!"𝑉!"#_!"#

+ 20𝑙𝑜𝑔𝑉!"!!"!"#$%&𝑉!"!"#$%

= 20𝑙𝑜𝑔1.6667 𝑉𝑝𝑝0.3053 𝑉𝑝𝑝

+ 20𝑙𝑜𝑔1.645 𝑉𝑝𝑝1.611 𝑉𝑝𝑝

= 14.74 + 0.18 = 14.92 𝑑𝐵

This leaves about 0.1 dB loss for the PCB trace on the evaluation board. We estimate the 14.92 dB loss to be accurate within ±0.2 dB. Figure 2.4 illustrates the CLB loss.

Figure 2.4 FFT magnitude spectrum of 4 GHz differential signal before (blue) and after (green)

passing through a CLB's PCB trace.

3.9995 3.9996 3.9997 3.9998 3.9999 4 4.0001 4.0002 4.0003 4.0004 4.000510−6

10−5

10−4

10−3

10−2

10−1

100

101

FFT

Mag

nitud

e (V

pp) 4 GHz, 0.3053 Vpp

4 GHz, 1.6667 Vpp

Frequency (GHz)

JitterLabs Post-processing for Measurement Metrics


3 Post-processing for Measurement Metrics JitterLabs uses custom software to extract each of the following parameters from voltage

data acquired by a real-time sampling oscilloscope.

3.1 AC, DC Parameters

3.1.1 Specifications

For reference, this section summarizes PCIe v4.0 BASE specifications [3] for reference clocks used in common clock applications.

AC, DC Specifications [3]

Symbol Parameter 100 MHz Input

Unit Note Min Max

ER_rising Rising Edge Rate 0.6 4.0 V/ns 2, 3 ER_falling Falling Edge Rate 0.6 4.0 V/ns 2, 3 Vih Differential Input High Voltage +150 mV 2 Vil Differential Input Low Voltage -150 mV 2 Vcross Absolute crossing point voltage +250 +550 mV 1, 4, 5

Vcross_delta Variation of VCROSS over all rising clock edges +140 mV 1, 4, 9

Vrb Ring-back Voltage Margin -100 +100 mV 2, 12 Tstable Time before VRB is allowed 500 ps 2, 12 Tperiod_avg Average Clock Period Accuracy -300 +2800 ppm 2, 10, 13

Tperiod_abs Absolute Period (including Jitter and Spread Spectrum modulation)

9.847 10.203 ns 2, 6

Tcc_jitter Cycle to Cycle jitter 150 ps 2 Vmax Absolute Max input voltage +1.15 V 1, 7 Vmin Absolute Min input voltage - 0.3 V 1, 8 Duty_cycle Duty Cycle 40 60 % 2

ER_matching Rising edge rate (REFCLK+) to falling edge rate (REFCLK-) matching

20 % 1, 14

Zc_dc Clock source DC impedance 40 60 Ω 1, 11

1. Measurement taken from single ended waveform. 2. Measurement taken from differential waveform. 3. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus

REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. See Figure 3.6.

4. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. See Figure 3.2.



5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Figure 3.2

6. Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread spectrum modulation. See Figure 3.5.

7. Defined as the maximum instantaneous voltage including overshoot. See Figure 3.2. 8. Defined as the minimum instantaneous voltage including undershoot. See Figure 3.2. 9. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-.

This is the maximum allowed variance in VCROSS for any particular system. See Figure 3.3. 10. Refer to Section 4.3.7.1.1 of the PCI Express Base Specification, Revision 3.0 for information

regarding PPM considerations. 11. System board compliance measurements must use the test load card described in Figure 3.1.

REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load CL = 2 pF.

12. TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is allowed to droop back into the VRB ±100 mV differential range. See Figure 3.7.

13. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly or 100 Hz. For 300 PPM, then we have an error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency counter with measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not employ Spread Spectrum Clocking, or that use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500 PPM nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,800 PPM.

14. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 3.4.

Figure 3.1 Refclk test setup. [3]



Figure 3.2 Single-ended measurement points for absolute crossing point and swing. [3]

Figure 3.3 Single-ended measurement points for delta cross point. [3]

Figure 3.4 Single-ended measurement points for rise and fall time matching. [3]

Figure 3.5 Differential measurement points for duty cycle and period. [3]



Figure 3.6 Differential measurement points for rise and fall time. [3]

Figure 3.7 Differential measurement points for ringback. [3]

Data-rate Independent Specifications [3]

Symbol Description Limits Units Notes

- Refclk Frequency 99.97 (min), 100.03 (max) MHz

Fssc SSC frequency range 30 (min), 33 (max) kHz 3

Tssc_freq_dev SSC deviation -0.5 (min), 0.0 (max) % 3

- Tx-Rx transport delay 12 (max) Nsec 1, 4

Tssc_max_freq_slew Max SSC df/dt 1250 ppm/usec 2, 3

1. Parameter is relevant only for common Refclk architecture. 2. Measurement is made over 0.5µsec time interval with an 1st order LPF with an fc of 60x the modulation

frequency. 3. When testing the a device configured for the IR reference clock architecture the SSC related parameters

must be tested with the Tx output data instead of the reference clock. 4. There are form factors (for example topologies including long cables) that may exceed the transport delay

limit. Extra jitter from the large transport delay must be accounted by these form factor specifications.



3.1.2 Rising and falling edge rate (ER_rising, ER_falling)

Figure 3.8 Illustration of edge rate measurement.

The edge (i.e. slew) rate in units of V/s is computed for a differential edge as,

ER_rising = 0.3/Tr, and ER_falling = 0.3/Tf

where Tr and Tf are the edge's rise and fall times defined by ±150 mV around 0V. The edge rate is computed 100 000 times for each edge polarity, creating a set of values used to compute the following metrics.

ER_rising Mean = the average, or mean, value measured for ER_rising.

ER_rising Range (pp) = ER_rising Max (pk) − ER_rising Min (pk).

ER_rising Max (pk) = the maximum value measured for ER_rising.

ER_rising Min (pk) = the minimum value measured for ER_rising.

ER_rising Std Dev = the standard deviation of measured values for ER_rising.

ER_falling Mean = the average, or mean, value measured for ER_falling.

ER_falling Range (pp) = ER_falling Max (pk) − ER_falling Min (pk).

ER_falling Max (pk) = the maximum value measured for ER_falling.

ER_falling Min (pk) = the minimum value measured for ER_falling.

ER_falling Std Dev = the standard deviation of measured values for

ER_falling.

REFCLK+minusREFCLK-

-150 mV0 V

+150 mV

Tr Tf



3.1.3 Differential input high and low voltage (Vih, Vil)

Figure 3.9 Illustration of Vih and Vil measurement.

For each cycle in the differential waveform, Vih and Vil are computed as the maximum and minimum (respectively) voltage observed within that cycle. The parameters Vih and Vil are each computed for 100 000 continuous cycles, creating a set of Vih and Vil values used to compute the following metrics.

Vih Mean = the average, or mean, value measured for Vih.

Vih Range (pp) = Vih Max (pk) − Vih Min (pk).

Vih Max (pk) = the maximum value measured for Vih.

Vih Min (pk) = the minimum value measured for Vih.

Vih Std Dev = the standard deviation of measured values for Vih.

Vil Mean = the average, or mean, value measured for Vil.

Vil Range (pp) = Vil Max (pk) − Vil Min (pk).

Vil Max (pk) = the maximum value measured for Vil.

Vil Min (pk) = the minimum value measured for Vil.

Vil Std Dev = the standard deviation of measured values for Vil.

REFCLK+minusREFCLK-

0 V

Vil

Vih



3.1.4 Absolute crossing-point voltage (Vcross)

Figure 3.10 Illustration of crossing voltage measurement.

For each cycle in the single-ended waveforms, a crossing voltage (Vx_r) is measured when the rising edge of REFCLK+ crosses the falling edge of REFCLK-. The parameter Vx_r is measured for 100 000 continuous cycles, creating a set of Vx_r values used to compute the following metrics.

Vcross Mean = the average, or mean, value measured for Vx_r.

Vcross Range (pp) = Vcross Max (pk) − Vcross Min (pk).

Vcross Max (pk) = the maximum value measured for Vx_r.

Vcross Min (pk) = the minimum value measured for Vx_r.

Vcross Std Dev = the standard deviation of measured values for Vx_r.

3.1.5 Variation of Vcross for rising edges (Vcross_delta)

Vcross_delta is computed from the set of Vx_r values (defined above) as follows.

Vcross_delta = Vcross Range (pp).

REFCLK-

0VREFCLK+

Vx_r



3.1.6 Ring-back voltage margin (Vrb)

Figure 3.11 Illustration of ring-back voltage-margin measurement.

For a positive pulse width (PPW) in a differential cycle, a region of time is defined between where the end of the rising edge begins to fall (a), and the start of the falling edge (b). The ring-back voltage (Vrb) is computed as the minimum voltage in this region.

Similarly, for a negative pulse width (NPW) in a differential cycle, a region of time is defined between where the end of the falling edge begins to rise (c), and the start of the rising edge (d). Vrb is computed as the maximum voltage in this region.

The parameter Vrb for PPW is measured for 100 000 continuous cycles, creating a set of Vrb (PPW) values used to compute the following metrics.

Vrb (PPW) Mean = the average, or mean, value measured for Vrb (PPW).

Vrb (PPW) Range (pp) = Vrb (PPW) Max (pk) − Vrb (PPW) Min (pk).

Vrb (PPW) Max (pk) = the maximum value measured for Vrb (PPW).

Vrb (PPW) Min (pk) = the minimum value measured for Vrb (PPW).

Vrb (PPW) Std Dev = the standard deviation of measured values for Vrb (PPW).

The parameter Vrb for NPW is measured for 100 000 cycles, creating a set of Vrb (NPW) values used to compute the following metrics.

Vrb (NPW) Mean = the average, or mean, value measured for Vrb (NPW).

Vrb (NPW) Range (pp) = Vrb (NPW) Max (pk) − Vrb (NPW) Min (pk).

Vrb (NPW) Max (pk) = the maximum value measured for Vrb (NPW).

Vrb (NPW) Min (pk) = the minimum value measured for Vrb (NPW).

Vrb (NPW) Std Dev = the standard deviation of measured values for Vrb (NPW).

REFCLK+minusREFCLK-

0 V

a b c d

Vrb (PPW)

Vrb (NPW)



3.1.7 Time before Vrb is allowed (Tstable)

Figure 3.12 Illustration of Tstable measurement for positive and negative pulse widths.

For a positive pulse width (PPW) in the differential waveformo, Tstable is the time it takes the waveform to pass above 0.15V and return below 0.15V. For a negative pulse width (NPW), Tstable is the time it takes the waveform to pass below 0.15V and return above 0.15V.

The parameter Tstable for PPW and NPW is measured for 100 000 continuous cycles, creating a set of 200 000 Tstable values used to compute the following metrics.

Tstable Mean = the average, or mean, value measured for Tstable.

Tstable Range (pp) = Tstable Max (pk) − Tstable Min (pk).

Tstable Max (pk) = the maximum value measured for Tstable.

Tstable Min (pk) = the minimum value measured for Tstable.

Tstable Std Dev = the standard deviation of measured values for Tstable.

0.15 V

REFCLK+minusREFCLK-

0 V

0.15 V

-0.15 V

Tstable (PPW) Tstable (NPW)



3.1.8 Average clock period accuracy (Tperiod_avg)

Figure 3.13 Illustration of period measurement.

For a particular cycle in the differential waveform, an instantaneous period (P) is computed. This process is repeated for all cycles in the waveform, to the limit of the memory depth of the instrument. JitterLabs acquires at least 1 Gpts of voltage values with each acquistion, which provides at least 2.6 million continuous cycles (at 100 MHz) for analysis.

An average period from this set of data is computed as PERr_avg, and used to report the average clock period accuracy in units of PPM as follows.

Tperiod_abs (PPM) = (1e8 - 1/PERr_avg)×1e6/1e8.

3.1.9 Absolute period (Tperiod_abs)

For a particular cycle in the differential waveform, the period (P) is computed as described in section 3.1.8. The parameter P is measured for 100 000 continuous cycles, creating a set of P values used to compute the following metrics.

Tperiod_abs Max (pk) = the maximum value measured for P.

Tperiod_abs Min (pk) = the minimum value measured for P.

3.1.10 Cycle to cycle jitter (Tcc_jitter)

Figure 3.14 Illustration of period measurements used to compute cycle to cycle jitter.

Cycle-to-cycle jitter is computed for two neighboring cycles defined by rising edges in the differential waveform as,

C2CJ (rising edges) = |P2 – P1|.

This process is repeated for 100 001 continuous neighboring cycles, to produce a set of 100 000 C2CJ values used to compute the following metrics.

REFCLK+minusREFCLK-

0 V

P

REFCLK+minusREFCLK-

0 V

P1 P2



Tcc_jitter Range (pp) = Tcc_jitter Max (pk) − Tcc_jitter Min (pk).

Tcc_jitter Max (pk) = the maximum value in the Tcc_jitter time trend.

Tcc_jitter Min (pk) = the minimum value in the Tcc_jitter time trend.

3.1.11 Absolute maximum, minimum input voltage (Vmax, Vmin)

Figure 3.15 Illustration of absolute max and min voltage.

The maximum and minimum single-ended voltage from REFCLK+ and REFCLK- waveforms are reported as Vmax and Vmin , respectively, analyzed over 100 000 continuous cycles.

3.1.12 Duty cycle (Duty_cycle)

Figure 3.16 Illustration of duty cycle measurement.

For each cycle in the differential waveform, duty cycle (DC) is computed as,

DC = 100% × T ÷ P

where T is the positive-pulse width, and P is the period for that cycle. The parameter DC is measured for 100 000 continuous cycles, providing a set of DC values used to compute the following metrics.

Duty_cycle Mean = the average, or mean, value measured for DC.

Duty_cycle Range (pp) = Duty_cycle Max (pk) − Duty_cycle Min (pk).

Duty_cycle Max (pk) = the maximum value measured for DC.

Duty_cycle Min (pk) = the minimum value measured for DC.

Duty_cycle Std Dev = the standard deviation of measured values for DC.

0V Vmin

Vmax

REFCLK+

REFCLK-

REFCLK+minusREFCLK-

T

P

0 V



3.1.13 Rising to falling edge-rate matching (ER_matching)

Figure 3.17 Illustration of rising to falling edge-rate matching measurement.

100 000 continuous cycles are analyzed to compute an average crossing voltage (Vx_r_mean) where rising edges cross falling edges. A ±75 mV window is centered around Vx_r_mean and used to compute, for each of the 100 000 crossing voltages, a rise (Trise) and fall (Tfall) time. Rising to falling edge-rate matching is then computed as,

𝑒𝑟𝑚 = 100%×𝑇𝑟𝑖𝑠𝑒 − 𝑇𝑓𝑎𝑙𝑙

𝑚𝑖𝑛(𝑇𝑟𝑖𝑠𝑒,𝑇𝑓𝑎𝑙𝑙)

where 𝑚𝑖𝑛(𝑇𝑟𝑖𝑠𝑒,𝑇𝑓𝑎𝑙𝑙) computes the minimum value of Trise and Tfall [4].

The above equation for 𝑒𝑟𝑚 is computed for each of the 100 000 cycles, and used to compute the following rising to falling edge-rate matching metrics.

ER_matching Mean = the mean value measured for erm.

ER_matching Range (pp) = ER_matching Max (pk) − ER_matching Min (pk).

ER_matching Max (pk) = the maximum value measured for erm.

ER_matching Min (pk) = the minimum value measured for erm.

ER_matching Std Dev = the standard deviation of measured values for erm.

REFCLK-

REFCLK+

Vx_r_mean

Vx_r_mean + 0.075 V

Vx_r_mean – 0.075 VTfall

Trise



3.1.14 Clock source output DC impedance (Zc_dc)

Figure 3.18 Illustration of voltage used to compute output buffer DC impedance.

A single-ended voltage swing is computed separately for REFCLK- (e.g. Vamptd_n1) and REFCLK+ (e.g. Vamptd_p1) waveforms using a first compliance load board having 2 pF termination. This process is repeated for a second compliance load board, which uses an oscilloscope's 50 Ohm termination (see section 2.4) to obtain corresponding values Vamptd_n2 and Vamptd_p2 for REFCLK- and REFCLK+, respectively.

Each output buffer's DC impedance is then computed as follows.

Zo_dc (REFCLK-) = 50× (Vamptd_n1/Vamptd_n2 − 1)

Zo_dc (REFCLK+) = 50× (Vamptd_p1/Vamptd_p2 − 1)

3.1.15 Spread spectrum clock frequency (Fss)

This measurement only applies to spread-spectrum clock (SSC) signals.

The i'th period is computed from the differential waveform as shown in Figure 3.13, from rising to rising edge, and inverted to compute a corresponding frequency denoted as freq(i) (e.g. typically falling between 99.5 and 100 MHz). This process is repeated to obtain a set of frequencies for the waveform to the limit of the oscilloscope's memory depth. These frequencies are ordered in sequence to form a time trend of frequency in the waveform (freq_tt).

To reduce vertical noise, the time trend is passed through a 2 MHz low-pass filter and the spread-spectrum clock frequency is computed by evaluating neighboring spread-spectrum midpoint crossings in the filtered time trend as shown in Figure 3.19.

Figure 3.19 Illustration of spread-spectrum frequency (fssc) measurement.

Vamptd_n Vamptd_p

REFCLK+REFCLK-

Midpoint

Frequency

Time

1/fssc



A set of fssc values is computed from the filtered frequency time trend to derive spread-spectrum clock frequency metrics as follows.

Fssc Range (pp) = Fssc Max (pk) − Fssc Min (pk).

Fssc Max (pk) = the maximum value measured for fssc.

Fssc Min (pk) = the minimum value measured for fssc.

3.1.16 SSC frequency deviation (Tssc_freq_dev)

From the set of freq(i) values computed in section 3.1.15, a minimum frequency is determined as freq_min and used to compute a minimum SSC frequency deviation as follows.

Tssc_freq_dev Min (%) = 100%× (freq_min - 1e8) / 1e8.

Note that although the standard does specify a maximum frequency deviation, there is likely some non-zero ppb offset between what the oscilloscope and DUT timebases each consider 100 MHz to be, leading to zero-margin from this measurement artifact. As this doesn't reflect the spirit of the specification, we don't explicitly report the maximum frequency deviation here. Instead, we rely on the Tperiod_avg and Tperiod_abs tests above (sections 3.1.8 and 3.1.9) to catch failures for maximum frequency deviation.

3.1.17 Maximum, minimum SSC frequency slew (Tssc_max_freq_slew)

Let freq_tt_filt represent the 2 MHz filtered frequency time trend computed in section 3.1.15. The frequency slew rate over a 0.5 μs time interval is then computed as,

freq_slew_tt = [freq_tt_filt(i + 0.5 μs) - freq_tt_filt(i)] / (0.5 μs)

in units of Hz/second. This is converted to units of PPM/seconds using,

freq_slew_tt = (freq_slew_tt × 1e6) / 1e8,

and finally converted to units of PPM/μs using,

freq_slew_tt = freq_slew_tt / 1e6.

The maximum and minimum SSC frequency slew may then be computed as follows.

Tssc_max_freq_slew Min (PPM/μs) = minimum value of freq_slew_tt.

Tssc_max_freq_slew Max (PPM/μs) = maximum value of freq_slew_tt.



3.2 Low-frequency Jitter Mask

3.2.1 Specification

Reference clock low-frequency jitter limits are defined as a continuous piece-wize linear graph from 30 kHz to 500 kHz as shown below. Unfiltered Refclk jitter must fall below this graph.

Figure 3.20 Plot of Refclk low-frequency jitter mask [3].

3.2.2 Low-frequency Jitter Mask (Jitter_mask)

Figure 3.21 Illustration of jitter measurement.

Time-interval error (TIE) jitter is measured differentially for at least 1 million rising edges according to Figure 3.21, where the reference-edge crossings are derived from the average period. To remove skew, the TIE mean value is computed and subtracted from all TIE values.

Frequency (Hz)

Jitte

r (ps

pp)

25000 ps

1000 ps

25 ps

30-33 KHz

100 KHz

500 KHz

Reference-edge Crossings

TIE(i) TIE(i+2) TIE(i+3)

Observed-edge Crossings

0 V

REFCLK+minusREFCLK-



The time trend of TIE jitter is then windowed, padded, and Fast-Fourier Transformed (FFT) into the frequency domain. The FFT magnitude is scaled appropriately to plot in units of ps peak-to-peak, for evaluation against the above mask.

3.3 Jitter Generation Parameters

3.3.1 Specifications

"A common clock (CC) architecture utilizes a single Refclk source that is distributed to both the Tx and Rx. Most of the SSC jitter sourced by the Refclk is propagated equally through Tx and Rx PLLs, and so intrinsically tracks LF jitter. This is particularly true for SSC which tends to be low frequency. Figure 3.22 illustrates the common Refclk Rx architecture, showing key jitter, delay, and PLL and CDR transfer function sources. The amount of jitter appearing at the CDR is then defined by the difference function between the Tx and Rx PLLs multiplied by the CDR highpass characteristic." [3]

Figure 3.22 Common clocking architecture.

"Based on the above clock architecture, it is possible to define a difference function that corresponds to the worst case mismatch between Tx and Rx PLLs. Second order PLL transfer functions are assumed, (even though most PLL transfer functions are 3rd order or higher), since a 2nd order function tends to yield a slightly conservative difference function vis-a-vis most actual PLL implementations. For CC the CDR is assumed to be first order. Actual CDRs of higher order will tend to filter more low frequency jitter, so assuming a 1st order transfer function will yield slightly conservative jitter results in these cases." [3]

"In the common Refclk Rx architecture it is also necessary to comprehend a maximum Transmitter to Receiver transport delay difference. This delay delta is illustrated in Figure 3.22 and represents the delay difference between the Transmitter data and recovered Receiver clock as seen at the inputs to the receive’s data latch." [3]

Tx latchData In

H1(s) =

H3(s) =

Data OutRx latchRx EQ

Tx PLL Rx PLL

CDR

Refclk, X(s)

Channel

T = | T1 ̶ T2 |

2sζ1ωn1+ ωn12

s2 +2sζ1ωn1+ ωn12

H2(s) = 2sζ2ωn2+ ωn2

2

s2 +2sζ2ωn2+ ωn22

s

s + ω3



The following tables define the jitter transfer functions required to evaluate reference clock jitter for all generations of PCI Express.

GEN-1 (2.5 GT/s)

PLL #1 0.01 dB

peaking 3.0 dB

peaking PLL #2 0.01 dB

peaking 3.0 dB

peaking

BWPLL(min)=

1.5 MHz

ωn1=0.336 Mrad/s

ωn1=5.09 Mrad/s

BWPLL(min)= 1.5 MHz

ωn2=0.336 Mrad/s

ωn2=5.09 Mrad/s

ζ1=14 ζ1=0.54 ζ2=14 ζ2=0.54

BWPLL(min)=22 MHz

ωn1=4.93 Mrad/s

ωn1=74.68 Mrad/s

BWPLL(min)= 22 MHz

ωn2=4.93 Mrad/s

ωn2=74.68 Mrad/s

ζ1=14 ζ1=0.54 ζ2=14 ζ2=0.54

CDR BWCDR(min)=

1.5 MHz 16 combinations

GEN-2 (5 GT/s)

PLL #1 0.01 dB

peaking 1.0 dB


peaking 3.0 dB

peaking

BWPLL(min)=

5 MHz

ωn1=1.12 Mrad/s

ωn1=11.01 Mrad/s

BWPLL(min)

= 8 MHz

ωn2=1.79 Mrad/s

ωn2=26.86 Mrad/s

ζ1=14 ζ1=1.16 ζ2=14 ζ2=0.54

BWPLL(min)=16 MHz

ωn1=3.58 Mrad/s

ωn1=35.26 Mrad/s

BWPLL(min)= 16 MHz

ωn2=3.58 Mrad/s

ωn2=53.73 Mrad/s

ζ1=14 ζ1=1.16 ζ2=14 ζ2=0.54

CDR BWCDR(min)=

5 MHz 64 combinations



GEN-3, GEN-4 (8, 16 GT/s)

PLL #1 0.01 dB

peaking 2.0 dB


peaking 1.0 dB

peaking

BWPLL(min)=

2 MHz

ωn1=0.448 Mrad/s

ωn1=6.02 Mrad/s

BWPLL(min)

= 2 MHz

ωn2=0.448 Mrad/s

ωn2=4.62 Mrad/s

ζ1=14 ζ1=0.73 ζ2=14 ζ2=1.15

BWPLL(min)=4 MHz

ωn1=0.893 Mrad/s

ωn1=12.04 Mrad/s

BWPLL(min)= 5 MHz

ωn2=1.12 Mrad/s

ωn2=11.53 Mrad/s

ζ1=14 ζ1=0.73 ζ2=14 ζ2=1.15

CDR BWCDR(min)=

10 MHz 64 combinations

After applying the above filters, reference clock jitter must meet the following limits.

Common Clock Jitter Limits [3]

Data Rate CC jitter Limit Notes

2.5 GT/s 108 ps pp 1, 2

5.0 GT/s 3.1 ps RMS 1, 2

8.0 GT/s 1.0 ps RMS 1, 2

16.0 GT/s 0.5 ps RMS 1, 2, 3, 4

1. The Refclk jitter is measured after applying the required jitter filter functions defined above.

2. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real time oscilloscope with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement.

3. For the 16.0 GT/s CC measurement SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 MHz taking care to minimize removal of any non-SSC content.

4. Note that 0.7 ps RMS is to be used in channel simulations to account for additional noise in a real system.



3.3.2 Jitter GEN-1, GEN-2 (2.5, 5 GT/s)

A single oscilloscope acquisition is used to compute TIE jitter for rising edges as illustrated in Figure 3.21. The resulting TIE jitter time trend is FFT transformed into the frequency domain, and separately filtered for each required transfer-function combination. Each filtered TIE jitter spectrum is then inverse Fourier transformed back to the time domain. This filtered time-domain jitter waveform is then quantified as peak-peak (GEN-1) and RMS (GEN-2) values for a population of 1 million continuous rising edges.

3.3.3 Jitter GEN-3 (8 GT/s)

As the required level of Refclk jitter reduces for higher data rates, the influence of oscilloscope jitter (and other sources of jitter from the test environment) becomes significant. Therefore, starting in GEN-3, after taking the inverse Fourier transform outlined above for GEN-1 and 2, JitterLabs adds a step to remove jitter introduced by the test environment, which is typically dominated by oscilloscope jitter. This process is fully compliant with PCI-SIG test requirements, and is completely documented in reference [2]. The total population for jitter analysis is 1 million continuous rising edges, from which an RMS value is computed. For completeness, the corresponding RMS jitter without removing jitter from the test environment is also computed and reported in each test report.

3.3.4 Jitter GEN-4 (16 GT/s)

The GEN-4 jitter analysis uses the same procedure as GEN-3, except the spurious noise in a spread-spectrum clock signal is removed up to 2 MHz before taking the inverse Fourier transform.

JitterLabs References


4 References [1] "Test Procedures: Test Reports," TEST-1, available from within the JitterLabs app,

https://www.jitterlabs.com/services/webapp.

[2] "Removing Oscilloscope Noise from RMS Jitter Measurements," NOTE-5, JitterLabs, https://www.jitterlabs.com/support/publications.

[3] PCI Express Base Specification, Rev. 4.0, v1.0 (Sept. 27, 2017), PCI-SIG association, available at http://www.pcisig.com.

[4] Equation verified using example provided in "Meeting Minutes for April 1, 2016 ElectroMechanical Work Group Teleconference," revision 1 by Marc Wells, available from http://www.pcisig.com.

5 Revision History Table 5.1 Revision History

Version Date Changes

1.0 August 22, 2017 Initial release.

1.1 November 20, 2017 Updated specification for Tssc_freq_dev.

1.2 December 13, 2017 Added buffer test procedures.

1.3 December 22, 2017 Corrected equation for ER_matching by replacing max() in denominator with min(); changed reference 4; removed reference 5. Removed buffer test procedures.

Documents

Test Procedures for PCIe4 Compliance Statements · JitterLabs Introduction TEST-2, v1.3 page 3 of 27 1 Introduction JitterLabs is an independent test laboratory providing accurate